[PATH,6/6] MIPS: Add Loongson 2K1000 proccessor support

Message ID CAKjxQHmVRJY-j=OM5NVy55eROZeFJg1496o2yp-98_SGJG89=g@mail.gmail.com
State New
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Series
  • Untitled series #6182
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Commit Message

Paul Hua Aug. 4, 2018, 8:20 a.m.
MIPS: Add Loongson 2K1000 proccessor support.

2018-08-04  Chenghua Xu  <paul.hua.gm@gmail.com>

bfd/
        * archures.c (bfd_architecture): New machine
        bfd_mach_mips_gs264e.
        * bfd-in2.h (bfd_architecture): Likewise.
        * cpu-mips.c (enum I_xxx): Likewise.
        (arch_info_struct): Likewise.
        * elfxx-mips.c (_bfd_elf_mips_mach): Handle
        E_MIPS_MACH_GS264E.
        (mips_set_isa_flags): Likewise.
        (mips_mach_extensions): Map bfd_mach_mips_gs264e to
        bfd_mach_mips_gs464e extension.

binutils/
        * NEWS: Mention Loongson 2K1000 proccessor support.
        * readelf.c (get_machine_flags): Handle gs264e.

elfcpp/
        * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.

gas/
        * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
        (mips_cpu_info_table): Add gs264e descriptors.
        * doc/as.texi (march table): Add gs264e.

include/
        * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
        * opcode/mips.h (CPU_XXX): New CPU_GS264E.

ld/
        * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
        gs264e and gs464e.

opcodes/
        * mips-dis.c (mips_arch_choices): Add gs264e descriptors.

Comments

Paul Hua Aug. 4, 2018, 8:33 a.m. | #1
This is the correct version.

MIPS: Add Loongson 2K1000 proccessor support.

2018-08-04  Chenghua Xu  <paul.hua.gm@gmail.com>

bfd/
        * archures.c (bfd_architecture): New machine
        bfd_mach_mips_gs264e.
        * bfd-in2.h (bfd_architecture): Likewise.
        * cpu-mips.c (enum I_xxx): Likewise.
        (arch_info_struct): Likewise.
        * elfxx-mips.c (_bfd_elf_mips_mach): Handle
        E_MIPS_MACH_GS264E.
        (mips_set_isa_flags): Likewise.
        (mips_mach_extensions): Map bfd_mach_mips_gs264e to
        bfd_mach_mips_gs464e extension.

binutils/
        * NEWS: Mention Loongson 2K1000 proccessor support.
        * readelf.c (get_machine_flags): Handle gs264e.

elfcpp/
        * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.

gas/
        * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
        (mips_cpu_info_table): Add gs264e descriptors.
        * doc/as.texi (march table): Add gs264e.

include/
        * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
        * opcode/mips.h (CPU_XXX): New CPU_GS264E.

ld/
        * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
        gs264e and gs464e.

opcodes/
        * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
From d79f39d2c1f35ed4556162769eafeb3045f30e28 Mon Sep 17 00:00:00 2001
From: Chenghua Xu <paul.hua.gm@gmail.com>
Date: Thu, 2 Aug 2018 20:25:36 +0800
Subject: [PATCH 6/6] MIPS: Add Loongson 2K1000 proccessor support.

---
 bfd/archures.c                              | 1 +
 bfd/bfd-in2.h                               | 1 +
 bfd/cpu-mips.c                              | 2 ++
 bfd/elfxx-mips.c                            | 8 ++++++++
 binutils/NEWS                               | 5 +++++
 binutils/readelf.c                          | 1 +
 elfcpp/mips.h                               | 1 +
 gas/config/tc-mips.c                        | 5 ++++-
 gas/doc/c-mips.texi                         | 1 +
 include/elf/mips.h                          | 1 +
 include/opcode/mips.h                       | 1 +
 ld/testsuite/ld-mips-elf/mips-elf-flags.exp | 4 ++++
 opcodes/mips-dis.c                          | 5 +++++
 13 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/bfd/archures.c b/bfd/archures.c
index 2fd9bdac57..e9644fafda 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -177,6 +177,7 @@ DESCRIPTION
 .#define bfd_mach_mips_loongson_2f	3002
 .#define bfd_mach_mips_gs464		3003
 .#define bfd_mach_mips_gs464e		3004
+.#define bfd_mach_mips_gs232e		3005
 .#define bfd_mach_mips_sb1		12310201 {* octal 'SB', 01.  *}
 .#define bfd_mach_mips_octeon		6501
 .#define bfd_mach_mips_octeonp		6601
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index f0fc1cfc71..40ac9ee24d 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2074,6 +2074,7 @@ enum bfd_architecture
 #define bfd_mach_mips_loongson_2f      3002
 #define bfd_mach_mips_gs464            3003
 #define bfd_mach_mips_gs464e           3004
+#define bfd_mach_mips_gs264e           3005
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01.  */
 #define bfd_mach_mips_octeon           6501
 #define bfd_mach_mips_octeonp          6601
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 2617c79b2d..339b1114e1 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -100,6 +100,7 @@ enum
   I_loongson_2f,
   I_gs464,
   I_gs464e,
+  I_gs264e,
   I_mipsocteon,
   I_mipsocteonp,
   I_mipsocteon2,
@@ -153,6 +154,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",	  FALSE, NN(I_loongson_2f)),
   N (64, 64, bfd_mach_mips_gs464, "mips:gs464",	  FALSE, NN(I_gs464)),
   N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e",	  FALSE, NN(I_gs464e)),
+  N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e",	  FALSE, NN(I_gs264e)),
   N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, NN(I_mipsocteon)),
   N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+",  FALSE, NN(I_mipsocteonp)),
   N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2",  FALSE, NN(I_mipsocteon2)),
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 25c2d9cedc..14621cd09e 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -6793,6 +6793,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_GS464E:
       return bfd_mach_mips_gs464e;
 
+    case E_MIPS_MACH_GS264E:
+      return bfd_mach_mips_gs264e;
+
     case E_MIPS_MACH_OCTEON3:
       return bfd_mach_mips_octeon3;
 
@@ -11995,6 +11998,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
       break;
 
+    case bfd_mach_mips_gs264e:
+      val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS264E;
+      break;
+
     case bfd_mach_mips_octeon:
     case bfd_mach_mips_octeonp:
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
@@ -14000,6 +14007,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
   { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
   { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
   { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+  { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
   { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
   { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
 
diff --git a/binutils/NEWS b/binutils/NEWS
index 775436df18..de70c3a23c 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,10 @@
 -*- text -*-
 
+* The MIPS port now supports the Loongson 2K1000 processor which implements
+  the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE, Loongson-ext ASE,
+  Loongson-ext2 ASE and MSA ASE instructions. Add -march=gs264e option for
+  Loongson 2K1000 processor.
+
 * The MIPS port now supports the Loongson 3A2000/3A3000 processor which
   implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE,
   Loongson-ext ASE and Loongson-ext2 ASE instructions. Add -march=gs464e
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 2ed715c606..01aafea042 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3406,6 +3406,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
   	    case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
 	    case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
 	    case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break;
+	    case E_MIPS_MACH_GS264E: strcat (buf, ", gs264e"); break;
 	    case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
 	    case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
 	    case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
diff --git a/elfcpp/mips.h b/elfcpp/mips.h
index 0b15211213..ab9cc13c6f 100644
--- a/elfcpp/mips.h
+++ b/elfcpp/mips.h
@@ -237,6 +237,7 @@ enum
   E_MIPS_MACH_LS2F = 0x00A10000,
   E_MIPS_MACH_GS464 = 0x00A20000,
   E_MIPS_MACH_GS464E = 0x00A30000,
+  E_MIPS_MACH_GS264E = 0x00A40000,
 };
 
 // MIPS architecture
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 9c0a1fd88c..c9fc6c6ec1 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -423,7 +423,8 @@ static int mips_32bitmode = 0;
     || (ISA) == ISA_MIPS64R6		\
     || (CPU) == CPU_R5900)		\
    && ((CPU) != CPU_GS464		\
-    || (CPU) != CPU_GS464E))
+    || (CPU) != CPU_GS464E		\
+    || (CPU) != CPU_GS264E))
 
 /* Return true if ISA supports move to/from high part of a 64-bit
    floating-point register. */
@@ -19817,6 +19818,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
      ISA_MIPS64R2,	CPU_GS464 },
   { "gs464e",         0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
      | ASE_LOONGSON_EXT2,	ISA_MIPS64R2,	CPU_GS464E },
+  { "gs264e",         0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+     | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64,	ISA_MIPS64R2,	CPU_GS264E },
 
   /* Cavium Networks Octeon CPU core */
   { "octeon",	      0, 0,			ISA_MIPS64R2, CPU_OCTEON },
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 2682e36502..7751ce01d6 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -439,6 +439,7 @@ loongson2e,
 loongson2f,
 gs464,
 gs464e,
+gs264e,
 octeon,
 octeon+,
 octeon2,
diff --git a/include/elf/mips.h b/include/elf/mips.h
index e27b6af69b..3858ee38d4 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -301,6 +301,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_LS2F        0x00A10000
 #define E_MIPS_MACH_GS464       0x00A20000
 #define E_MIPS_MACH_GS464E	0x00A30000
+#define E_MIPS_MACH_GS264E	0x00A40000
 
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 4ad65c9fab..fe8d16b1a5 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1374,6 +1374,7 @@ static const unsigned int mips_isa_table[] = {
 #define CPU_LOONGSON_2F 3002
 #define CPU_GS464	3003
 #define CPU_GS464E	3004
+#define CPU_GS264E	3005
 #define CPU_OCTEON	6501
 #define CPU_OCTEONP	6601
 #define CPU_OCTEON2	6502
diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
index 31df38b5a2..b35d13a034 100644
--- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
+++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
@@ -275,3 +275,7 @@ good_combination { "-march=gs464 -32" "-march=gs464e -32" }	\
 		 { gs464e o32 }					\
 		 MIPS64r2 "None"				\
 		 { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
+good_combination { "-march=gs264e -32" "-march=gs464e -32" }	\
+		 { gs264e o32 }					\
+		 MIPS64r2 "None"				\
+		 { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 0f5799d49b..69919486fe 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -645,6 +645,11 @@ const struct mips_arch_choice mips_arch_choices[] =
     | ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
     mips_hwr_names_numeric },
 
+  { "g264e",   1, bfd_mach_mips_gs464e, CPU_GS264E,
+    ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+    | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, mips_cp0_names_numeric, NULL,
+    0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
     ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
     mips_cp1_names_mips3264, mips_hwr_names_numeric },

Patch

From 8c3cf9925e8a47144e1d76351e9134d89a6e2b08 Mon Sep 17 00:00:00 2001
From: Chenghua Xu <paul.hua.gm@gmail.com>
Date: Thu, 2 Aug 2018 20:25:36 +0800
Subject: [PATCH 6/6] MIPS: Add Loongson 2K1000 proccessor support.

---
 bfd/archures.c                              | 1 +
 bfd/bfd-in2.h                               | 1 +
 bfd/cpu-mips.c                              | 2 ++
 bfd/elfxx-mips.c                            | 8 ++++++++
 binutils/NEWS                               | 5 +++++
 binutils/readelf.c                          | 1 +
 elfcpp/mips.h                               | 1 +
 gas/config/tc-mips.c                        | 5 ++++-
 gas/doc/c-mips.texi                         | 1 +
 include/elf/mips.h                          | 1 +
 include/opcode/mips.h                       | 1 +
 ld/testsuite/ld-mips-elf/mips-elf-flags.exp | 4 ++++
 opcodes/mips-dis.c                          | 5 +++++
 13 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/bfd/archures.c b/bfd/archures.c
index 2fd9bdac57..e9644fafda 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -177,6 +177,7 @@  DESCRIPTION
 .#define bfd_mach_mips_loongson_2f	3002
 .#define bfd_mach_mips_gs464		3003
 .#define bfd_mach_mips_gs464e		3004
+.#define bfd_mach_mips_gs232e		3005
 .#define bfd_mach_mips_sb1		12310201 {* octal 'SB', 01.  *}
 .#define bfd_mach_mips_octeon		6501
 .#define bfd_mach_mips_octeonp		6601
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index f0fc1cfc71..40ac9ee24d 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2074,6 +2074,7 @@  enum bfd_architecture
 #define bfd_mach_mips_loongson_2f      3002
 #define bfd_mach_mips_gs464            3003
 #define bfd_mach_mips_gs464e           3004
+#define bfd_mach_mips_gs264e           3005
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01.  */
 #define bfd_mach_mips_octeon           6501
 #define bfd_mach_mips_octeonp          6601
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 2617c79b2d..339b1114e1 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -100,6 +100,7 @@  enum
   I_loongson_2f,
   I_gs464,
   I_gs464e,
+  I_gs264e,
   I_mipsocteon,
   I_mipsocteonp,
   I_mipsocteon2,
@@ -153,6 +154,7 @@  static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",	  FALSE, NN(I_loongson_2f)),
   N (64, 64, bfd_mach_mips_gs464, "mips:gs464",	  FALSE, NN(I_gs464)),
   N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e",	  FALSE, NN(I_gs464e)),
+  N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e",	  FALSE, NN(I_gs264e)),
   N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, NN(I_mipsocteon)),
   N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+",  FALSE, NN(I_mipsocteonp)),
   N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2",  FALSE, NN(I_mipsocteon2)),
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 25c2d9cedc..14621cd09e 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -6793,6 +6793,9 @@  _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_GS464E:
       return bfd_mach_mips_gs464e;
 
+    case E_MIPS_MACH_GS264E:
+      return bfd_mach_mips_gs264e;
+
     case E_MIPS_MACH_OCTEON3:
       return bfd_mach_mips_octeon3;
 
@@ -11995,6 +11998,10 @@  mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
       break;
 
+    case bfd_mach_mips_gs264e:
+      val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS264E;
+      break;
+
     case bfd_mach_mips_octeon:
     case bfd_mach_mips_octeonp:
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
@@ -14000,6 +14007,7 @@  static const struct mips_mach_extension mips_mach_extensions[] =
   { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
   { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
   { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+  { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
   { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
   { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
 
diff --git a/binutils/NEWS b/binutils/NEWS
index 775436df18..de70c3a23c 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,10 @@ 
 -*- text -*-
 
+* The MIPS port now supports the Loongson 2K1000 processor which implements
+  the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE, Loongson-ext ASE,
+  Loongson-ext2 ASE and MSA ASE instructions. Add -march=gs264e option for
+  Loongson 2K1000 processor.
+
 * The MIPS port now supports the Loongson 3A2000/3A3000 processor which
   implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE,
   Loongson-ext ASE and Loongson-ext2 ASE instructions. Add -march=gs464e
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 2ed715c606..01aafea042 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3406,6 +3406,7 @@  get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
   	    case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
 	    case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
 	    case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break;
+	    case E_MIPS_MACH_GS264E: strcat (buf, ", gs264e"); break;
 	    case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
 	    case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
 	    case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
diff --git a/elfcpp/mips.h b/elfcpp/mips.h
index 0b15211213..ab9cc13c6f 100644
--- a/elfcpp/mips.h
+++ b/elfcpp/mips.h
@@ -237,6 +237,7 @@  enum
   E_MIPS_MACH_LS2F = 0x00A10000,
   E_MIPS_MACH_GS464 = 0x00A20000,
   E_MIPS_MACH_GS464E = 0x00A30000,
+  E_MIPS_MACH_GS264E = 0x00A40000,
 };
 
 // MIPS architecture
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 9c0a1fd88c..c9fc6c6ec1 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -423,7 +423,8 @@  static int mips_32bitmode = 0;
     || (ISA) == ISA_MIPS64R6		\
     || (CPU) == CPU_R5900)		\
    && ((CPU) != CPU_GS464		\
-    || (CPU) != CPU_GS464E))
+    || (CPU) != CPU_GS464E		\
+    || (CPU) != CPU_GS264E))
 
 /* Return true if ISA supports move to/from high part of a 64-bit
    floating-point register. */
@@ -19817,6 +19818,8 @@  static const struct mips_cpu_info mips_cpu_info_table[] =
      ISA_MIPS64R2,	CPU_GS464 },
   { "gs464e",         0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
      | ASE_LOONGSON_EXT2,	ISA_MIPS64R2,	CPU_GS464E },
+  { "gs264e",         0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+     | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64,	ISA_MIPS64R2,	CPU_GS264E },
 
   /* Cavium Networks Octeon CPU core */
   { "octeon",	      0, 0,			ISA_MIPS64R2, CPU_OCTEON },
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 2682e36502..7751ce01d6 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -439,6 +439,7 @@  loongson2e,
 loongson2f,
 gs464,
 gs464e,
+gs264e,
 octeon,
 octeon+,
 octeon2,
diff --git a/include/elf/mips.h b/include/elf/mips.h
index e27b6af69b..3858ee38d4 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -301,6 +301,7 @@  END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_LS2F        0x00A10000
 #define E_MIPS_MACH_GS464       0x00A20000
 #define E_MIPS_MACH_GS464E	0x00A30000
+#define E_MIPS_MACH_GS264E	0x00A40000
 
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 4ad65c9fab..fe8d16b1a5 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1374,6 +1374,7 @@  static const unsigned int mips_isa_table[] = {
 #define CPU_LOONGSON_2F 3002
 #define CPU_GS464	3003
 #define CPU_GS464E	3004
+#define CPU_GS264E	3005
 #define CPU_OCTEON	6501
 #define CPU_OCTEONP	6601
 #define CPU_OCTEON2	6502
diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
index 31df38b5a2..8fa137fa9c 100644
--- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
+++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
@@ -275,3 +275,7 @@  good_combination { "-march=gs464 -32" "-march=gs464e -32" }	\
 		 { gs464e o32 }					\
 		 MIPS64r2 "None"				\
 		 { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
+good_combination { "-march=gs264e -32" "-march=gs464e -32" }	\
+		 { gs264e o32 }					\
+		 MIPS64r2 "None"				\
+		 { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" "MSA ASE" }
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 0f5799d49b..69919486fe 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -645,6 +645,11 @@  const struct mips_arch_choice mips_arch_choices[] =
     | ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
     mips_hwr_names_numeric },
 
+  { "g264e",   1, bfd_mach_mips_gs464e, CPU_GS264E,
+    ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+    | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, mips_cp0_names_numeric, NULL,
+    0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
     ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
     mips_cp1_names_mips3264, mips_hwr_names_numeric },
-- 
2.11.0