[1/6] MIPS/GAS: Split Loongson CAM Instructions from loongson3a.

Message ID CAKjxQH=LNvsSe-DCkfaoLDgdo+Td6d7MnTco9QcGjp6YhaLGeg@mail.gmail.com
State Superseded
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  • [1/6] MIPS/GAS: Split Loongson CAM Instructions from loongson3a.
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Commit Message

Paul Hua Aug. 4, 2018, 8:07 a.m.
MIPS/GAS: Split Loongson CAM Instructions from loongson3a.

2018-08-04  Chenghua Xu  <paul.hua.gm@gmail.com>

bfd/
        * elfxx-mips.c (print_mips_ases): Add CAM extension.

binutils/
        * readelf.c (print_mips_ases): Add CAM extension.

gas/
        * NEWS: Mention Loongson Content Address Memory (CAM)
        support.
        * config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and
        OPTION_NO_LOONGSON_CAM.
        (md_longopts): Likewise.
        (mips_ases): Define availability for CAM.
        (mips_convert_ase_flags): Map ASE_LOONGSON_CAM to
        AFL_ASE_LOONGSON_CAM.
        (mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a.
        (md_show_usage): Add help for -mloongson-cam and
        -mno-loongson-cam.
        * doc/as.texi: Document -mloongson-cam, -mno-loongson-cam.
        * doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam,
        .set loongson-cam and .set noloongson-cam.
        * testsuite/gas/mips/loongson-3a-2.d: Move cam test to ...
        * testsuite/gas/mips/loongson-cam.d: Here.  Add ISA/ASE
        flag verification.
        * testsuite/gas/mips/loongson-3a-2.s: Move cam test to ...
        * testsuite/gas/mips/loongson-cam.s: Here.
        * testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag.
        * testsuite/gas/mips/mips.exp: Run loongson-cam test.

include/
        * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
        (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
        * opcode/mips.h (ASE_LOONGSON_CAM): New macro.

opcodes/
        * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
        descriptors.
        (parse_mips_ase_option): Handle -M loongson-cam option.
        (print_mips_disassembler_options): Document -M loongson-cam.
        * mips-opc.c (LCAM): New macro.
        (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
        instructions.

Patch

From efd96c01a072dca8d7da3efcbf032df5045d0bd2 Mon Sep 17 00:00:00 2001
From: Chenghua Xu <paul.hua.gm@gmail.com>
Date: Wed, 1 Aug 2018 14:05:39 +0800
Subject: [PATCH 1/6] MIPS/GAS: Split Loongson CAM Instructions from
 loongson3a.

---
 bfd/elfxx-mips.c                         |  2 ++
 binutils/readelf.c                       |  2 ++
 gas/NEWS                                 |  2 ++
 gas/config/tc-mips.c                     | 19 +++++++++++++++++--
 gas/doc/as.texi                          |  7 +++++++
 gas/doc/c-mips.texi                      | 15 +++++++++++++++
 gas/testsuite/gas/mips/loongson-3a-2.d   |  4 ----
 gas/testsuite/gas/mips/loongson-3a-2.s   |  5 -----
 gas/testsuite/gas/mips/loongson-3a-mmi.d |  1 +
 gas/testsuite/gas/mips/loongson-cam.d    | 27 +++++++++++++++++++++++++++
 gas/testsuite/gas/mips/loongson-cam.s    |  7 +++++++
 gas/testsuite/gas/mips/mips.exp          |  2 ++
 include/elf/mips.h                       |  3 ++-
 include/opcode/mips.h                    |  2 ++
 opcodes/mips-dis.c                       | 15 +++++++++++++--
 opcodes/mips-opc.c                       | 11 +++++++----
 16 files changed, 106 insertions(+), 18 deletions(-)
 create mode 100644 gas/testsuite/gas/mips/loongson-cam.d
 create mode 100644 gas/testsuite/gas/mips/loongson-cam.s

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index e538fd1461..80cc8c0448 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -15677,6 +15677,8 @@  print_mips_ases (FILE *file, unsigned int mask)
     fputs ("\n\tGINV ASE", file);
   if (mask & AFL_ASE_LOONGSON_MMI)
     fputs ("\n\tLoongson MMI ASE", file);
+  if (mask & AFL_ASE_LOONGSON_CAM)
+    fputs ("\n\tLoongson CAM ASE", file);
   if (mask == 0)
     fprintf (file, "\n\t%s", _("None"));
   else if ((mask & ~AFL_ASE_MASK) != 0)
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 90dbdf7e2b..033f6d7eac 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -15619,6 +15619,8 @@  print_mips_ases (unsigned int mask)
     fputs ("\n\tGINV ASE", stdout);
   if (mask & AFL_ASE_LOONGSON_MMI)
     fputs ("\n\tLoongson MMI ASE", stdout);
+  if (mask & AFL_ASE_LOONGSON_CAM)
+    fputs ("\n\tLoongson CAM ASE", stdout);
   if (mask == 0)
     fprintf (stdout, "\n\t%s", _("None"));
   else if ((mask & ~AFL_ASE_MASK) != 0)
diff --git a/gas/NEWS b/gas/NEWS
index 1f441eb672..b710c7acb1 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-
 
+* Add support for the MIPS Loongson Content Address Memory (CAM) ASE.
+
 * Add support for the C-SKY processor series.
 
 * Add support for the MIPS Loongson MultiMedia extensions Instructions (MMI)
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 9bbf59cca6..1f58a6dd8f 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1531,6 +1531,8 @@  enum options
     OPTION_NO_GINV,
     OPTION_LOONGSON_MMI,
     OPTION_NO_LOONGSON_MMI,
+    OPTION_LOONGSON_CAM,
+    OPTION_NO_LOONGSON_CAM,
     OPTION_END_OF_ENUM
   };
 
@@ -1593,6 +1595,8 @@  struct option md_longopts[] =
   {"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
   {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI},
   {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
+  {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
+  {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
 
   /* Old-style architecture options.  Don't add more of these.  */
   {"m4650", no_argument, NULL, OPTION_M4650},
@@ -1795,6 +1799,11 @@  static const struct mips_ase mips_ases[] = {
     OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI,
     0, 0, -1, -1,
     -1 },
+
+  { "loongson-cam", ASE_LOONGSON_CAM, 0,
+    OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
+    0, 0, -1, -1,
+    -1 },
 };
 
 /* The set of ASEs that require -mfp64.  */
@@ -19028,6 +19037,8 @@  mips_convert_ase_flags (int ase)
     ext_ases |= AFL_ASE_GINV;
   if (ase & ASE_LOONGSON_MMI)
     ext_ases |= AFL_ASE_LOONGSON_MMI;
+  if (ase & ASE_LOONGSON_CAM)
+    ext_ases |= AFL_ASE_LOONGSON_CAM;
 
   return ext_ases;
 }
@@ -19773,9 +19784,10 @@  static const struct mips_cpu_info mips_cpu_info_table[] =
   /* Broadcom SB-1A CPU core */
   { "sb1a",           0, ASE_MIPS3D | ASE_MDMX,	ISA_MIPS64,   CPU_SB1 },
 
-  { "loongson3a",     0, ASE_LOONGSON_MMI,	ISA_MIPS64R2, CPU_LOONGSON_3A },
-
   /* MIPS 64 Release 2 */
+  /* Loongson CPU core */
+  { "loongson3a",     0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM,	ISA_MIPS64R2,
+     CPU_LOONGSON_3A },
 
   /* Cavium Networks Octeon CPU core */
   { "octeon",	      0, 0,			ISA_MIPS64R2, CPU_OCTEON },
@@ -20051,6 +20063,9 @@  MIPS options:\n\
 -mloongson-mmi		generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
 -mno-loongson-mmi	do not generate Loongson MultiMedia extensions Instructions\n"));
   fprintf (stream, _("\
+-mloongson-cam		generate Loongson Content Address Memory (CAM) instructions\n\
+-mno-loongson-cam	do not generate Loongson Content Address Memory Instructions\n"));
+  fprintf (stream, _("\
 -minsn32		only generate 32-bit microMIPS instructions\n\
 -mno-insn32		generate all microMIPS instructions\n"));
   fprintf (stream, _("\
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index be84bf227b..5d10e07a3a 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -445,6 +445,7 @@  gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mcrc}] [@b{-mno-crc}]
    [@b{-mginv}] [@b{-mno-ginv}]
    [@b{-mloongson-mmi}] [@b{-mno-loongson-mmi}]
+   [@b{-mloongson-cam}] [@b{-mno-loongson-cam}]
    [@b{-minsn32}] [@b{-mno-insn32}]
    [@b{-mfix7000}] [@b{-mno-fix7000}]
    [@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
@@ -1573,6 +1574,12 @@  Application Specific Extension.  This tells the assembler to accept MMI
 instructions.
 @samp{-mno-loongson-mmi} turns off this option.
 
+@item -mloongson-cam
+@itemx -mno-loongson-cam
+Generate code for the Loongson Content Address Memory (CAM) instructions.
+This tells the assembler to accept Loongson CAM instructions.
+@samp{-mno-loongson-cam} turns off this option.
+
 @item -minsn32
 @itemx -mno-insn32
 Only use 32-bit instruction encodings when generating code for the
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index d10f2d6439..7d5d869bfd 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -253,6 +253,13 @@  Application Specific Extension.  This tells the assembler to accept MMI
 instructions.
 @samp{-mno-loongson-mmi} turns off this option.
 
+@item -mloongson-cam
+@itemx -mno-loongson-cam
+Generate code for the Loongson Content Address Memory (CAM)
+Application Specific Extension.  This tells the assembler to accept CAM
+instructions.
+@samp{-mno-loongson-cam} turns off this option.
+
 @item -minsn32
 @itemx -mno-insn32
 Only use 32-bit instruction encodings when generating code for the
@@ -1152,6 +1159,14 @@  instructions from the MMI Extension from that point on in the assembly.
 The @code{.set noloongson-mmi} directive prevents MMI instructions from
 being accepted.
 
+@cindex Loongson Content Address Memory (CAM) generation override
+@kindex @code{.set loongson-cam}
+@kindex @code{.set noloongson-cam}
+The directive @code{.set loongson-cam} makes the assembler accept
+instructions from the Loongson CAM from that point on in the assembly.
+The @code{.set noloongson-cam} directive prevents Loongson CAM instructions
+from being accepted.
+
 Traditional MIPS assemblers do not support these directives.
 
 @node MIPS Floating-Point
diff --git a/gas/testsuite/gas/mips/loongson-3a-2.d b/gas/testsuite/gas/mips/loongson-3a-2.d
index 8ef4c8e3cf..ff2f553c82 100644
--- a/gas/testsuite/gas/mips/loongson-3a-2.d
+++ b/gas/testsuite/gas/mips/loongson-3a-2.d
@@ -7,10 +7,6 @@ 
 Disassembly of section .text:
 
 [0-9a-f]+ <.text>:
-.*:	70601075 	campi	\$2,\$3
-.*:	70a02035 	campv	\$4,\$5
-.*:	70e830b5 	camwi	\$6,\$7,\$8
-.*:	714048f5 	ramri	\$9,\$10
 .*:	716c0026 	gsle	\$11,\$12
 .*:	71ae0027 	gsgt	\$13,\$14
 .*:	c8622010 	gslble	\$2,\$3,\$4
diff --git a/gas/testsuite/gas/mips/loongson-3a-2.s b/gas/testsuite/gas/mips/loongson-3a-2.s
index 7e35dd35be..551ce6425b 100644
--- a/gas/testsuite/gas/mips/loongson-3a-2.s
+++ b/gas/testsuite/gas/mips/loongson-3a-2.s
@@ -1,11 +1,6 @@ 
 	.text
 	.set noreorder
 
-	campi		$2,$3
-	campv		$4,$5
-	camwi		$6,$7,$8
-	ramri		$9,$10
-
 	gsle		$11,$12
 	gsgt		$13,$14
 
diff --git a/gas/testsuite/gas/mips/loongson-3a-mmi.d b/gas/testsuite/gas/mips/loongson-3a-mmi.d
index de69d3e63c..81503cb127 100644
--- a/gas/testsuite/gas/mips/loongson-3a-mmi.d
+++ b/gas/testsuite/gas/mips/loongson-3a-mmi.d
@@ -15,6 +15,7 @@  FP ABI: .*
 ISA Extension: Loongson 3A
 ASEs:
 	Loongson MMI ASE
+	Loongson CAM ASE
 FLAGS 1: .*
 FLAGS 2: .*
 
diff --git a/gas/testsuite/gas/mips/loongson-cam.d b/gas/testsuite/gas/mips/loongson-cam.d
new file mode 100644
index 0000000000..ae973ea591
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-cam.d
@@ -0,0 +1,27 @@ 
+#as: -mloongson-cam -mabi=64
+#objdump: -M reg-names=numeric -M loongson-cam -dp
+#name: Loongson CAM tests
+
+.*:     file format .*
+
+private flags = .*
+
+MIPS ABI Flags Version: 0
+ISA: .*
+GPR size: .*
+CPR1 size: .*
+CPR2 size: .*
+FP ABI: .*
+ISA Extension: None
+ASEs:
+	Loongson CAM ASE
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+.*:	70601075 	campi	\$2,\$3
+.*:	70a02035 	campv	\$4,\$5
+.*:	70e830b5 	camwi	\$6,\$7,\$8
+.*:	714048f5 	ramri	\$9,\$10
diff --git a/gas/testsuite/gas/mips/loongson-cam.s b/gas/testsuite/gas/mips/loongson-cam.s
new file mode 100644
index 0000000000..688e9d405b
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-cam.s
@@ -0,0 +1,7 @@ 
+	.text
+	.set noreorder
+
+	campi		$2,$3
+	campv		$4,$5
+	camwi		$6,$7,$8
+	ramri		$9,$10
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index ad371e13b5..2f6ddc97a9 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1394,6 +1394,8 @@  if { [istarget mips*-*-vxworks*] } {
     run_dump_test "loongson-2f-mmi"
     run_dump_test "loongson-3a-mmi"
 
+    run_dump_test "loongson-cam"
+
     if { $has_newabi } {
 	run_dump_test_arches "octeon"	[mips_arch_list_matching octeon]
     }
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 4ef51b5e78..f76f14f240 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1239,7 +1239,8 @@  extern void bfd_mips_elf_swap_abiflags_v0_out
 #define AFL_ASE_RESERVED1    0x00010000 /* Reserved by MIPS Tech for WIP.  */
 #define AFL_ASE_GINV         0x00020000 /* GINV ASE.  */
 #define AFL_ASE_LOONGSON_MMI 0x00040000 /* Loongson MMI ASE.  */
-#define AFL_ASE_MASK         0x0006ffff /* All ASEs.  */
+#define AFL_ASE_LOONGSON_CAM 0x00080000 /* Loongson CAM ASE.  */
+#define AFL_ASE_MASK         0x000effff /* All ASEs.  */
 
 /* Values for the isa_ext word of an ABI flags structure.  */
 
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 05614c1648..abcb47d48e 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1304,6 +1304,8 @@  static const unsigned int mips_isa_table[] = {
 #define ASE_GINV		0x00100000
 /* Loongson MultiMedia extensions Instructions (MMI).  */
 #define ASE_LOONGSON_MMI	0x00200000
+/* Loongson Content Address Memory (CAM).  */
+#define ASE_LOONGSON_CAM	0x00400000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 466301637f..832d4dc684 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -630,8 +630,9 @@  const struct mips_arch_choice mips_arch_choices[] =
     NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson3a",   1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
-    ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
-    NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+    ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
+    mips_hwr_names_numeric },
 
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
     ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
@@ -941,6 +942,12 @@  parse_mips_ase_option (const char *option)
       return TRUE;
     }
 
+  if (CONST_STRNEQ (option, "loongson-cam"))
+    {
+      mips_ase |= ASE_LOONGSON_CAM;
+      return TRUE;
+    }
+
   return FALSE;
 }
 
@@ -2592,6 +2599,10 @@  static struct
 		  N_("Recognize the Loongson MultiMedia extensions "
 		     "Instructions (MMI) ASE instructions.\n"),
 		  MIPS_OPTION_ARG_NONE },
+  { "loongson-cam",
+		  N_("Recognize the Loongson Content Address Memory (CAM) "
+		     " instructions.\n"),
+		  MIPS_OPTION_ARG_NONE },
   { "gpr-names=", N_("Print GPR names according to specified ABI.\n\
                   Default: based on binary being disassembled.\n"),
 		  MIPS_OPTION_ARG_ABI },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 31532f88a8..5c9f28a5d1 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -415,6 +415,9 @@  decode_mips_operand (const char *p)
 /* Loongson MultiMedia extensions Instructions (MMI) support.  */
 #define LMMI	ASE_LOONGSON_MMI
 
+/* Loongson Content Address Memory (CAM) support.  */
+#define LCAM	ASE_LOONGSON_CAM
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -459,10 +462,10 @@  const struct mips_opcode mips_builtin_opcodes[] =
 /* Loongson specific instructions.  Loongson 3A redefines the Coprocessor 2
    instructions.  Put them here so that disassembler will find them first.
    The assemblers uses a hash table based on the instruction name anyhow.  */
-{"campi",		"d,s",		0x70000075, 0xfc1f07ff,	WR_1|RD_2,		0,		IL3A,		0,	0 },
-{"campv",		"d,s",		0x70000035, 0xfc1f07ff,	WR_1|RD_2,		0,		IL3A,		0,	0 },
-{"camwi",		"d,s,t",	0x700000b5, 0xfc0007ff,	RD_1|RD_2|RD_3,		0,		IL3A,		0,	0 },
-{"ramri",		"d,s",		0x700000f5, 0xfc1f07ff,	WR_1|RD_2,		0,		IL3A,		0,	0 },
+{"campi",		"d,s",		0x70000075, 0xfc1f07ff,	WR_1|RD_2,		0,		0,		LCAM,	0 },
+{"campv",		"d,s",		0x70000035, 0xfc1f07ff,	WR_1|RD_2,		0,		0,		LCAM,	0 },
+{"camwi",		"d,s,t",	0x700000b5, 0xfc0007ff,	RD_1|RD_2|RD_3,		0,		0,		LCAM,	0 },
+{"ramri",		"d,s",		0x700000f5, 0xfc1f07ff,	WR_1|RD_2,		0,		0,		LCAM,	0 },
 {"gsle",		"s,t",		0x70000026, 0xfc00ffff,	RD_1|RD_2,		0,		IL3A,		0,	0 },
 {"gsgt",		"s,t",		0x70000027, 0xfc00ffff,	RD_1|RD_2,		0,		IL3A,		0,	0 },
 {"gslble",		"t,b,d",	0xc8000010, 0xfc0007ff,	WR_1|RD_2|RD_3|LM,	0,		IL3A,		0,	0 },
-- 
2.11.0