[45/55] rs6000: Builtin expansion, part 2

Message ID 76032999efd830fe06da8fa1c70478d56251b9b8.1623941442.git.wschmidt@linux.ibm.com
State Superseded
Headers show
Series
  • Replace the Power target-specific builtin machinery
Related show

Commit Message

Richard Biener via Gcc-patches June 17, 2021, 3:19 p.m.
2021-03-05  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin):
	Implement.
	(rs6000_expand_ldst_mask): Likewise.
	(rs6000_init_builtins): Initialize altivec_builtin_mask_for_load.
---
 gcc/config/rs6000/rs6000-call.c | 101 +++++++++++++++++++++++++++++++-
 1 file changed, 100 insertions(+), 1 deletion(-)

-- 
2.27.0

Comments

Richard Biener via Gcc-patches July 27, 2021, 9:06 p.m. | #1
On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> 2021-03-05  Bill Schmidt  <wschmidt@linux.ibm.com>

> 


Hi,

> gcc/

> 	* config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin):

> 	Implement.

> 	(rs6000_expand_ldst_mask): Likewise.

> 	(rs6000_init_builtins): Initialize altivec_builtin_mask_for_load.


ok

> ---

>  gcc/config/rs6000/rs6000-call.c | 101 +++++++++++++++++++++++++++++++-

>  1 file changed, 100 insertions(+), 1 deletion(-)

> 

> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c

> index 8693836cd5a..754cd46b1c1 100644

> --- a/gcc/config/rs6000/rs6000-call.c

> +++ b/gcc/config/rs6000/rs6000-call.c

> @@ -11671,6 +11671,75 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode)

>  static void

>  rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode)

>  {

> +  size_t uns_fncode = (size_t) fncode;

> +  const char *name = rs6000_builtin_info_x[uns_fncode].bifname;

> +

> +  switch (rs6000_builtin_info_x[uns_fncode].enable)

> +    {

> +    case ENB_P5:

> +      error ("%qs requires the %qs option", name, "-mcpu=power5");

> +      break;

> +    case ENB_P6:

> +      error ("%qs requires the %qs option", name, "-mcpu=power6");

> +      break;

> +    case ENB_ALTIVEC:

> +      error ("%qs requires the %qs option", name, "-maltivec");

> +      break;

> +    case ENB_CELL:

> +      error ("%qs is only valid for the cell processor", name);

> +      break;

> +    case ENB_VSX:

> +      error ("%qs requires the %qs option", name, "-mvsx");

> +      break;

> +    case ENB_P7:

> +      error ("%qs requires the %qs option", name, "-mcpu=power7");

> +      break;

> +    case ENB_P7_64:

> +      error ("%qs requires the %qs option and either the %qs or %qs option",

> +	     name, "-mcpu=power7", "-m64", "-mpowerpc64");

> +      break;

> +    case ENB_P8:

> +      error ("%qs requires the %qs option", name, "-mcpu=power8");

> +      break;

> +    case ENB_P8V:

> +      error ("%qs requires the %qs option", name, "-mpower8-vector");

> +      break;

> +    case ENB_P9:

> +      error ("%qs requires the %qs option", name, "-mcpu=power9");

> +      break;

> +    case ENB_P9_64:

> +      error ("%qs requires the %qs option and either the %qs or %qs option",

> +	     name, "-mcpu=power9", "-m64", "-mpowerpc64");

> +      break;

> +    case ENB_P9V:

> +      error ("%qs requires the %qs option", name, "-mpower9-vector");

> +      break;

> +    case ENB_IEEE128_HW:

> +      error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name);

> +      break;

> +    case ENB_DFP:

> +      error ("%qs requires the %qs option", name, "-mhard-dfp");

> +      break;

> +    case ENB_CRYPTO:

> +      error ("%qs requires the %qs option", name, "-mcrypto");

> +      break;

> +    case ENB_HTM:

> +      error ("%qs requires the %qs option", name, "-mhtm");

> +      break;

> +    case ENB_P10:

> +      error ("%qs requires the %qs option", name, "-mcpu=power10");

> +      break;

> +    case ENB_P10_64:

> +      error ("%qs requires the %qs option and either the %qs or %qs option",

> +	     name, "-mcpu=power10", "-m64", "-mpowerpc64");

> +      break;

> +    case ENB_MMA:

> +      error ("%qs requires the %qs option", name, "-mmma");

> +      break;

> +    default:

> +    case ENB_ALWAYS:

> +      gcc_unreachable ();

> +    };


ok

>  }

> 

>  /* Target hook for early folding of built-ins, shamelessly stolen

> @@ -14501,7 +14570,33 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,

>  rtx

>  rs6000_expand_ldst_mask (rtx target, tree arg0)

>   {

> -  return target;

> +  int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct

> +		: (int) CODE_FOR_altivec_lvsl_direct);

> +  machine_mode tmode = insn_data[icode2].operand[0].mode;

> +  machine_mode mode = insn_data[icode2].operand[1].mode;

> +  rtx op, addr, pat;

> +

> +  gcc_assert (TARGET_ALTIVEC);

> +

> +  gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg0)));

> +  op = expand_expr (arg0, NULL_RTX, Pmode, EXPAND_NORMAL);

> +  addr = memory_address (mode, op);

> +  /* We need to negate the address.  */

> +  op = gen_reg_rtx (GET_MODE (addr));

> +  emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));

> +  op = gen_rtx_MEM (mode, op);

> +

> +  if (target == 0

> +      || GET_MODE (target) != tmode

> +      || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))

> +    target = gen_reg_rtx (tmode);

> +

> +  pat = GEN_FCN (icode2) (target, op);

> +  if (!pat)

> +    return 0;

> +  emit_insn (pat);

> +

> +   return target;


ok

>   }

> 

>  /* Expand the CPU builtin in FCODE and store the result in TARGET.  */

> @@ -15401,6 +15496,10 @@ rs6000_init_builtins (void)

>    /* Execute the autogenerated initialization code for builtins.  */

>    rs6000_autoinit_builtins ();

> 

> +  if (new_builtins_are_live)

> +    altivec_builtin_mask_for_load

> +      = rs6000_builtin_decls_x[RS6000_BIF_MASK_FOR_LOAD];

> +


ok

>    if (new_builtins_are_live)

>      {

>  #ifdef SUBTARGET_INIT_BUILTINS

Patch

diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 8693836cd5a..754cd46b1c1 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -11671,6 +11671,75 @@  rs6000_invalid_builtin (enum rs6000_builtins fncode)
 static void
 rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode)
 {
+  size_t uns_fncode = (size_t) fncode;
+  const char *name = rs6000_builtin_info_x[uns_fncode].bifname;
+
+  switch (rs6000_builtin_info_x[uns_fncode].enable)
+    {
+    case ENB_P5:
+      error ("%qs requires the %qs option", name, "-mcpu=power5");
+      break;
+    case ENB_P6:
+      error ("%qs requires the %qs option", name, "-mcpu=power6");
+      break;
+    case ENB_ALTIVEC:
+      error ("%qs requires the %qs option", name, "-maltivec");
+      break;
+    case ENB_CELL:
+      error ("%qs is only valid for the cell processor", name);
+      break;
+    case ENB_VSX:
+      error ("%qs requires the %qs option", name, "-mvsx");
+      break;
+    case ENB_P7:
+      error ("%qs requires the %qs option", name, "-mcpu=power7");
+      break;
+    case ENB_P7_64:
+      error ("%qs requires the %qs option and either the %qs or %qs option",
+	     name, "-mcpu=power7", "-m64", "-mpowerpc64");
+      break;
+    case ENB_P8:
+      error ("%qs requires the %qs option", name, "-mcpu=power8");
+      break;
+    case ENB_P8V:
+      error ("%qs requires the %qs option", name, "-mpower8-vector");
+      break;
+    case ENB_P9:
+      error ("%qs requires the %qs option", name, "-mcpu=power9");
+      break;
+    case ENB_P9_64:
+      error ("%qs requires the %qs option and either the %qs or %qs option",
+	     name, "-mcpu=power9", "-m64", "-mpowerpc64");
+      break;
+    case ENB_P9V:
+      error ("%qs requires the %qs option", name, "-mpower9-vector");
+      break;
+    case ENB_IEEE128_HW:
+      error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name);
+      break;
+    case ENB_DFP:
+      error ("%qs requires the %qs option", name, "-mhard-dfp");
+      break;
+    case ENB_CRYPTO:
+      error ("%qs requires the %qs option", name, "-mcrypto");
+      break;
+    case ENB_HTM:
+      error ("%qs requires the %qs option", name, "-mhtm");
+      break;
+    case ENB_P10:
+      error ("%qs requires the %qs option", name, "-mcpu=power10");
+      break;
+    case ENB_P10_64:
+      error ("%qs requires the %qs option and either the %qs or %qs option",
+	     name, "-mcpu=power10", "-m64", "-mpowerpc64");
+      break;
+    case ENB_MMA:
+      error ("%qs requires the %qs option", name, "-mmma");
+      break;
+    default:
+    case ENB_ALWAYS:
+      gcc_unreachable ();
+    };
 }
 
 /* Target hook for early folding of built-ins, shamelessly stolen
@@ -14501,7 +14570,33 @@  rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
 rtx
 rs6000_expand_ldst_mask (rtx target, tree arg0)
  {
-  return target;
+  int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
+		: (int) CODE_FOR_altivec_lvsl_direct);
+  machine_mode tmode = insn_data[icode2].operand[0].mode;
+  machine_mode mode = insn_data[icode2].operand[1].mode;
+  rtx op, addr, pat;
+
+  gcc_assert (TARGET_ALTIVEC);
+
+  gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg0)));
+  op = expand_expr (arg0, NULL_RTX, Pmode, EXPAND_NORMAL);
+  addr = memory_address (mode, op);
+  /* We need to negate the address.  */
+  op = gen_reg_rtx (GET_MODE (addr));
+  emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
+  op = gen_rtx_MEM (mode, op);
+
+  if (target == 0
+      || GET_MODE (target) != tmode
+      || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
+    target = gen_reg_rtx (tmode);
+
+  pat = GEN_FCN (icode2) (target, op);
+  if (!pat)
+    return 0;
+  emit_insn (pat);
+
+   return target;
  }
 
 /* Expand the CPU builtin in FCODE and store the result in TARGET.  */
@@ -15401,6 +15496,10 @@  rs6000_init_builtins (void)
   /* Execute the autogenerated initialization code for builtins.  */
   rs6000_autoinit_builtins ();
 
+  if (new_builtins_are_live)
+    altivec_builtin_mask_for_load
+      = rs6000_builtin_decls_x[RS6000_BIF_MASK_FOR_LOAD];
+
   if (new_builtins_are_live)
     {
 #ifdef SUBTARGET_INIT_BUILTINS