i386: Fix up V2SFmode vcond* with -mxop [PR100581]

Message ID CAFULd4YHCJ_CtLjcH3zTn-Dw0WF-kXrQ7pGkPVpjOy-VFSROEA@mail.gmail.com
State New
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  • i386: Fix up V2SFmode vcond* with -mxop [PR100581]
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Commit Message

H.J. Lu via Gcc-patches May 13, 2021, 9:12 a.m.
ix86_expand_sse_movcc has special TARGET_XOP handling and the recent
addition of support of v*cond* patterns for V2SFmode results in
ICEs because the expected pattern doesn't exist.  We can handle it
using 128-bit vpcmov (if we ignore the upper 64 bits like we ignore in
other TARGET_MMX_WITH_SSE support).

2021-05-13  UroŇ° Bizjak  <ubizjak@gmail.com>

gcc/
    PR target/100581
    * config/i386/i386-expand.c (ix86_expand_sse_movcc): Force mode
    sizes < 16 to a register when constructing vpcmov pattern.
    * config/i386/mmx.md (*xop_pcmov_<mode>): Use MMXMODE124 mode.

gcc/testsuite/

    PR target/100581
    * g++.target/i386/pr100581.C: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Pushed to master.

Uros.

Patch

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index dd230081b16..92488b869ec 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -3661,7 +3661,8 @@  ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
     {
       op_true = force_reg (mode, op_true);
 
-      if (!nonimmediate_operand (op_false, mode))
+      if (GET_MODE_SIZE (mode) < 16
+	  || !nonimmediate_operand (op_false, mode))
 	op_false = force_reg (mode, op_false);
 
       emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cmp,
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index d433c524652..7fc2e5d781c 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1816,11 +1816,11 @@  (define_insn "mmx_pblendvb"
 
 ;; XOP parallel XMM conditional moves
 (define_insn "*xop_pcmov_<mode>"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
-        (if_then_else:MMXMODEI
-          (match_operand:MMXMODEI 3 "register_operand" "x")
-          (match_operand:MMXMODEI 1 "register_operand" "x")
-          (match_operand:MMXMODEI 2 "register_operand" "x")))]
+  [(set (match_operand:MMXMODE124 0 "register_operand" "=x")
+        (if_then_else:MMXMODE124
+          (match_operand:MMXMODE124 3 "register_operand" "x")
+          (match_operand:MMXMODE124 1 "register_operand" "x")
+          (match_operand:MMXMODE124 2 "register_operand" "x")))]
   "TARGET_XOP && TARGET_MMX_WITH_SSE"
   "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "sse4arg")])
diff --git a/gcc/testsuite/g++.target/i386/pr100581.C b/gcc/testsuite/g++.target/i386/pr100581.C
new file mode 100644
index 00000000000..37cc9f11f18
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr100581.C
@@ -0,0 +1,9 @@ 
+/* PR target/100581 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mxop" } */
+
+typedef float __attribute__((__vector_size__(8))) v64f32;
+
+v64f32 af, bf, ff_a, ff_b;
+
+v64f32 f() { return ff_a > ff_b ? af : bf; }