[01/24] RISC-V sim: Fix fence.i.

Message ID 20210417175831.16413-2-jimw@sifive.com
State New
Headers show
Series
  • RISC-V sim: Update from riscv-gnu-toolchain.
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Commit Message

Jim Wilson April 17, 2021, 5:58 p.m.
The fence.i instruction was moved to the zifencei extension.

	sim/riscv/
	* sim-main.c (execute_i): Drop MATCH_FENCE_I here.
	(execute_zifencei): New function, with MATCH_FENCE_I support.
	(execute_one): Call execute_zifencei.
---
 sim/riscv/sim-main.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

-- 
2.7.4

Comments

Mike Frysinger via Gdb-patches April 17, 2021, 8:36 p.m. | #1
On 17 Apr 2021 10:58, Jim Wilson wrote:
> The fence.i instruction was moved to the zifencei extension.


lgtm, thanks
-mike

Patch

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index ff328a0..ccab3ba 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -580,9 +580,6 @@  execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_FENCE:
       TRACE_INSN (cpu, "fence;");
       break;
-    case MATCH_FENCE_I:
-      TRACE_INSN (cpu, "fence.i;");
-      break;
     case MATCH_SBREAK:
       TRACE_INSN (cpu, "sbreak;");
       /* GDB expects us to step over SBREAK.  */
@@ -922,6 +919,26 @@  execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 }
 
 static sim_cia
+execute_zifencei (SIM_CPU *cpu, unsigned_word iw,
+		  const struct riscv_opcode *op)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  sim_cia pc = cpu->pc + 4;
+
+  switch (op->match)
+    {
+    case MATCH_FENCE_I:
+      TRACE_INSN (cpu, "fence.i;");
+      break;
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+  return pc;
+}
+
+static sim_cia
 execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 {
   SIM_DESC sd = CPU_STATE (cpu);
@@ -939,6 +956,8 @@  execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
       return execute_m (cpu, iw, op);
+    case INSN_CLASS_ZIFENCEI:
+      return execute_zifencei (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
       sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);