[1/6] Compute type mode and register class mapping

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  • [1/6] Compute type mode and register class mapping
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Commit Message

Bin Cheng May 4, 2018, 4:21 p.m.
Hi,
This is the updated version patch set computing register pressure on TREE SSA
and use that information to direct other loop optimizers (predcom only for now).
This version of change is to follow Jeff's comment that we should reuse existing
tree-ssa-live.c infrastructure for live range computation, rather than inventing
another one.
Jeff had another concern about exposing ira.h and low-level register stuff in
GIMPLE world.  Unfortunately I haven't got a clear solution to it.  I found it's
a bit hard to relate type/type_mode with register class and with available regs
without exposing the information, especially there are multiple possible register
classes for vector types and it's not fixed.  I am open to any suggestions here.

This is the first patch estimating the map from type mode to register class.
This one doesn't need update and it's the same as the original version patch
at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html

Bootstrap and test on x86_64 and AArch64 ongoing.  Any comments?

Thanks,
bin
2018-04-27  Bin Cheng  <bin.cheng@arm.com>

	* ira.c (setup_mode_classes): New function.
	(find_reg_classes): Call above function.
	* ira.h (struct target_ira): New field x_ira_mode_classes.
	(ira_mode_classes): New macro.

Comments

Bin.Cheng May 18, 2018, 8:40 a.m. | #1
On Fri, May 4, 2018 at 5:21 PM, Bin Cheng <Bin.Cheng@arm.com> wrote:
> Hi,

> This is the updated version patch set computing register pressure on TREE SSA

> and use that information to direct other loop optimizers (predcom only for now).

> This version of change is to follow Jeff's comment that we should reuse existing

> tree-ssa-live.c infrastructure for live range computation, rather than inventing

> another one.

> Jeff had another concern about exposing ira.h and low-level register stuff in

> GIMPLE world.  Unfortunately I haven't got a clear solution to it.  I found it's

> a bit hard to relate type/type_mode with register class and with available regs

> without exposing the information, especially there are multiple possible register

> classes for vector types and it's not fixed.  I am open to any suggestions here.

>

> This is the first patch estimating the map from type mode to register class.

> This one doesn't need update and it's the same as the original version patch

> at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html

>

> Bootstrap and test on x86_64 and AArch64 ongoing.  Any comments?

Hi,
The original version of this patch was approved by Jeff
@https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01808.html
Jeff, some new comment now or the old approval is still valid?
Guess your major concern is about exporting ira.h to gimple world?

Thanks,
bin

>

> Thanks,

> bin

> 2018-04-27  Bin Cheng  <bin.cheng@arm.com>

>

>         * ira.c (setup_mode_classes): New function.

>         (find_reg_classes): Call above function.

>         * ira.h (struct target_ira): New field x_ira_mode_classes.

>         (ira_mode_classes): New macro.
Jeff Law May 24, 2018, 10:55 p.m. | #2
On 05/18/2018 02:40 AM, Bin.Cheng wrote:
> On Fri, May 4, 2018 at 5:21 PM, Bin Cheng <Bin.Cheng@arm.com> wrote:

>> Hi,

>> This is the updated version patch set computing register pressure on TREE SSA

>> and use that information to direct other loop optimizers (predcom only for now).

>> This version of change is to follow Jeff's comment that we should reuse existing

>> tree-ssa-live.c infrastructure for live range computation, rather than inventing

>> another one.

>> Jeff had another concern about exposing ira.h and low-level register stuff in

>> GIMPLE world.  Unfortunately I haven't got a clear solution to it.  I found it's

>> a bit hard to relate type/type_mode with register class and with available regs

>> without exposing the information, especially there are multiple possible register

>> classes for vector types and it's not fixed.  I am open to any suggestions here.

>>

>> This is the first patch estimating the map from type mode to register class.

>> This one doesn't need update and it's the same as the original version patch

>> at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html

>>

>> Bootstrap and test on x86_64 and AArch64 ongoing.  Any comments?

> Hi,

> The original version of this patch was approved by Jeff

> @https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01808.html

> Jeff, some new comment now or the old approval is still valid?

> Guess your major concern is about exporting ira.h to gimple world?

Yea, that was by far my biggest concern -- IRA is very much in the RTL
world and exposing it into the gimple world seems like a major layering
violation.

So I have no inherent issues with this patch in isolation, but I may
have issues with subsequent patches if they introduce that kind of
layering violation.  So let's avoid installing until we have agreement
on the full set of patches.

jeff
Richard Biener May 25, 2018, 7:14 a.m. | #3
On Fri, May 25, 2018 at 12:55 AM Jeff Law <law@redhat.com> wrote:

> On 05/18/2018 02:40 AM, Bin.Cheng wrote:

> > On Fri, May 4, 2018 at 5:21 PM, Bin Cheng <Bin.Cheng@arm.com> wrote:

> >> Hi,

> >> This is the updated version patch set computing register pressure on

TREE SSA
> >> and use that information to direct other loop optimizers (predcom only

for now).
> >> This version of change is to follow Jeff's comment that we should

reuse existing
> >> tree-ssa-live.c infrastructure for live range computation, rather than

inventing
> >> another one.

> >> Jeff had another concern about exposing ira.h and low-level register

stuff in
> >> GIMPLE world.  Unfortunately I haven't got a clear solution to it.  I

found it's
> >> a bit hard to relate type/type_mode with register class and with

available regs
> >> without exposing the information, especially there are multiple

possible register
> >> classes for vector types and it's not fixed.  I am open to any

suggestions here.
> >>

> >> This is the first patch estimating the map from type mode to register

class.
> >> This one doesn't need update and it's the same as the original version

patch
> >> at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html

> >>

> >> Bootstrap and test on x86_64 and AArch64 ongoing.  Any comments?

> > Hi,

> > The original version of this patch was approved by Jeff

> > @https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01808.html

> > Jeff, some new comment now or the old approval is still valid?

> > Guess your major concern is about exporting ira.h to gimple world?

> Yea, that was by far my biggest concern -- IRA is very much in the RTL

> world and exposing it into the gimple world seems like a major layering

> violation.


> So I have no inherent issues with this patch in isolation, but I may

> have issues with subsequent patches if they introduce that kind of

> layering violation.  So let's avoid installing until we have agreement

> on the full set of patches.


I guess we should make Vlad aware of this as well.

Richard.

> jeff
Bin.Cheng May 25, 2018, 8:31 a.m. | #4
On Thu, May 24, 2018 at 11:55 PM, Jeff Law <law@redhat.com> wrote:
> On 05/18/2018 02:40 AM, Bin.Cheng wrote:

>> On Fri, May 4, 2018 at 5:21 PM, Bin Cheng <Bin.Cheng@arm.com> wrote:

>>> Hi,

>>> This is the updated version patch set computing register pressure on TREE SSA

>>> and use that information to direct other loop optimizers (predcom only for now).

>>> This version of change is to follow Jeff's comment that we should reuse existing

>>> tree-ssa-live.c infrastructure for live range computation, rather than inventing

>>> another one.

>>> Jeff had another concern about exposing ira.h and low-level register stuff in

>>> GIMPLE world.  Unfortunately I haven't got a clear solution to it.  I found it's

>>> a bit hard to relate type/type_mode with register class and with available regs

>>> without exposing the information, especially there are multiple possible register

>>> classes for vector types and it's not fixed.  I am open to any suggestions here.

>>>

>>> This is the first patch estimating the map from type mode to register class.

>>> This one doesn't need update and it's the same as the original version patch

>>> at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html

>>>

>>> Bootstrap and test on x86_64 and AArch64 ongoing.  Any comments?

>> Hi,

>> The original version of this patch was approved by Jeff

>> @https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01808.html

>> Jeff, some new comment now or the old approval is still valid?

>> Guess your major concern is about exporting ira.h to gimple world?

> Yea, that was by far my biggest concern -- IRA is very much in the RTL

> world and exposing it into the gimple world seems like a major layering

> violation.

>

> So I have no inherent issues with this patch in isolation, but I may

> have issues with subsequent patches if they introduce that kind of

> layering violation.  So let's avoid installing until we have agreement

> on the full set of patches.

Sure, in the meantime, I will think again if there is way to avoid
this shortage.

The 3rd/4th patches are pure change to current live range and
coalescing stuff which
are irrelevant to this issue, I suppose it's okay to commit that two.

Thanks,
bin
>

> jeff
Richard Biener May 25, 2018, 10:26 a.m. | #5
On Fri, May 25, 2018 at 10:45 AM Bin.Cheng <amker.cheng@gmail.com> wrote:

> On Thu, May 24, 2018 at 11:55 PM, Jeff Law <law@redhat.com> wrote:

> > On 05/18/2018 02:40 AM, Bin.Cheng wrote:

> >> On Fri, May 4, 2018 at 5:21 PM, Bin Cheng <Bin.Cheng@arm.com> wrote:

> >>> Hi,

> >>> This is the updated version patch set computing register pressure on

TREE SSA
> >>> and use that information to direct other loop optimizers (predcom

only for now).
> >>> This version of change is to follow Jeff's comment that we should

reuse existing
> >>> tree-ssa-live.c infrastructure for live range computation, rather

than inventing
> >>> another one.

> >>> Jeff had another concern about exposing ira.h and low-level register

stuff in
> >>> GIMPLE world.  Unfortunately I haven't got a clear solution to it.  I

found it's
> >>> a bit hard to relate type/type_mode with register class and with

available regs
> >>> without exposing the information, especially there are multiple

possible register
> >>> classes for vector types and it's not fixed.  I am open to any

suggestions here.
> >>>

> >>> This is the first patch estimating the map from type mode to register

class.
> >>> This one doesn't need update and it's the same as the original

version patch
> >>> at https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01021.html

> >>>

> >>> Bootstrap and test on x86_64 and AArch64 ongoing.  Any comments?

> >> Hi,

> >> The original version of this patch was approved by Jeff

> >> @https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01808.html

> >> Jeff, some new comment now or the old approval is still valid?

> >> Guess your major concern is about exporting ira.h to gimple world?

> > Yea, that was by far my biggest concern -- IRA is very much in the RTL

> > world and exposing it into the gimple world seems like a major layering

> > violation.

> >

> > So I have no inherent issues with this patch in isolation, but I may

> > have issues with subsequent patches if they introduce that kind of

> > layering violation.  So let's avoid installing until we have agreement

> > on the full set of patches.

> Sure, in the meantime, I will think again if there is way to avoid

> this shortage.


> The 3rd/4th patches are pure change to current live range and

> coalescing stuff which

> are irrelevant to this issue, I suppose it's okay to commit that two.


Yes.

> Thanks,

> bin

> >

> > jeff

Patch

From d65c160a37f785cff29172f1335e87d01fc260ba Mon Sep 17 00:00:00 2001
From: Bin Cheng <binche01@e108451-lin.cambridge.arm.com>
Date: Mon, 24 Apr 2017 14:41:28 +0100
Subject: [PATCH 1/6] ira-mode-reg_class-map-20170316.txt

---
 gcc/ira.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/ira.h |  7 ++++++
 2 files changed, 84 insertions(+)

diff --git a/gcc/ira.c b/gcc/ira.c
index b7bcc15..f132a7a 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -1154,6 +1154,82 @@  setup_class_translate (void)
 			       ira_pressure_classes_num, ira_pressure_classes);
 }
 
+/* Find desired register class for machine mode from information about
+   register pressure class.  On RTL level, we can compute preferred
+   register class infomation for each pseudo register or allocno.  On
+   GIMPLE level, we need to infer register class from variable's type,
+   i.e, we need map from type mode to register class.
+
+   The map information is computed by simple guess, it's good enough
+   for use on GIMPLE.  */
+void
+setup_mode_classes (void)
+{
+  int i, j;
+  machine_mode mode;
+  enum reg_class vector_class = NO_REGS;
+
+  for (i = 0; i < NUM_MACHINE_MODES; i++)
+    {
+      mode = (machine_mode) i;
+      ira_mode_classes[mode] = NO_REGS;
+
+      /* Only care about integer, float and vector modes on GIMPLE.  */
+      if (!INTEGRAL_MODE_P (mode)
+	  && !FLOAT_MODE_P (mode) && !VECTOR_MODE_P (mode))
+	continue;
+
+      /* Integers must be in GENERAL_REGS by default.  */
+      if (SCALAR_INT_MODE_P (mode))
+	{
+	  ira_mode_classes[mode] = GENERAL_REGS;
+	  continue;
+	}
+
+      /* Iterate over pressure classes and find the most appropriate
+	 one for this mode.  */
+      for (j = 0; j < ira_pressure_classes_num; j++)
+	{
+	  HARD_REG_SET valid_for_cl;
+	  enum reg_class cl = ira_pressure_classes[j];
+
+	  if (!contains_reg_of_mode[cl][mode])
+	    continue;
+
+	  COPY_HARD_REG_SET (valid_for_cl, reg_class_contents[cl]);
+	  AND_COMPL_HARD_REG_SET (valid_for_cl,
+				  ira_prohibited_class_mode_regs[cl][mode]);
+	  AND_COMPL_HARD_REG_SET (valid_for_cl, ira_no_alloc_regs);
+	  if (hard_reg_set_empty_p (valid_for_cl))
+	    continue;
+
+	  if (ira_mode_classes[mode] == NO_REGS)
+	    {
+	      ira_mode_classes[mode] = cl;
+
+	      /* Record reg_class for vector mode.  */
+	      if (VECTOR_MODE_P (mode) && cl != NO_REGS)
+		vector_class = cl;
+
+	      continue;
+	    }
+	  /* Prefer non GENERAL_REGS for floating points.  */
+	  if ((FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
+	      && cl != GENERAL_REGS && ira_mode_classes[mode] == GENERAL_REGS)
+	    ira_mode_classes[mode] = cl;
+	}
+    }
+
+  /* Setup vector modes that are missed previously.  */
+  if (vector_class != NO_REGS)
+    for (i = 0; i < NUM_MACHINE_MODES; i++)
+      {
+	mode = (machine_mode) i;
+	if (ira_mode_classes[mode] == NO_REGS && VECTOR_MODE_P (mode))
+	  ira_mode_classes[mode] = vector_class;
+      }
+}
+
 /* Order numbers of allocno classes in original target allocno class
    array, -1 for non-allocno classes.  */
 static int allocno_class_order[N_REG_CLASSES];
@@ -1430,6 +1506,7 @@  find_reg_classes (void)
   setup_class_translate ();
   reorder_important_classes ();
   setup_reg_class_relations ();
+  setup_mode_classes ();
 }
 
 
diff --git a/gcc/ira.h b/gcc/ira.h
index 9df983c..3471d4c 100644
--- a/gcc/ira.h
+++ b/gcc/ira.h
@@ -66,6 +66,11 @@  struct target_ira
      class.  */
   enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
 
+  /* Map of machine mode to register pressure class.  With this map,
+     coarse-grained register pressure can be computed on GIMPLE, where
+     we don't have insn pattern to compute preferred reg class.  */
+  enum reg_class x_ira_mode_classes[MAX_MACHINE_MODE];
+
   /* Biggest pressure register class containing stack registers.
      NO_REGS if there are no stack registers.  */
   enum reg_class x_ira_stack_reg_pressure_class;
@@ -140,6 +145,8 @@  extern struct target_ira *this_target_ira;
   (this_target_ira->x_ira_pressure_classes)
 #define ira_pressure_class_translate \
   (this_target_ira->x_ira_pressure_class_translate)
+#define ira_mode_classes \
+  (this_target_ira->x_ira_mode_classes)
 #define ira_stack_reg_pressure_class \
   (this_target_ira->x_ira_stack_reg_pressure_class)
 #define ira_reg_class_max_nregs \
-- 
1.9.1