x86: Fix up ssse3_pshufbv8qi splitter

Message ID 20200830092116.GE18149@tucnak
State New
Headers show
Series
  • x86: Fix up ssse3_pshufbv8qi splitter
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Commit Message

Uros Bizjak via Gcc-patches Aug. 30, 2020, 9:21 a.m.
Hi!

The constant pool size optimization I was testing resulted in various ICEs
in gcc.target/i386/ testsuite, the problem is that the ssse3_pshufbv8qi
splitter emits invalid RTL, in V4SImode 0xf7f7f7f7 CONST_INTs shouldn't
appear, instead they should have been -0x8080809 (0xf7f7f7f7 sign extended
into 64 bits).

Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
trunk?

2020-08-30  Jakub Jelinek  <jakub@redhat.com>

	* config/i386/sse.md (ssse3_pshufbv8qi): Use gen_int_mode instead of
	GEN_INT, and ix86_build_const_vector instead of gen_rtvec and
	gen_rtx_CONT_VECTOR.


	Jakub

Comments

Uros Bizjak via Gcc-patches Aug. 30, 2020, 9:52 a.m. | #1
On Sun, Aug 30, 2020 at 11:21 AM Jakub Jelinek <jakub@redhat.com> wrote:
>

> Hi!

>

> The constant pool size optimization I was testing resulted in various ICEs

> in gcc.target/i386/ testsuite, the problem is that the ssse3_pshufbv8qi

> splitter emits invalid RTL, in V4SImode 0xf7f7f7f7 CONST_INTs shouldn't

> appear, instead they should have been -0x8080809 (0xf7f7f7f7 sign extended

> into 64 bits).

>

> Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for

> trunk?

>

> 2020-08-30  Jakub Jelinek  <jakub@redhat.com>

>

>         * config/i386/sse.md (ssse3_pshufbv8qi): Use gen_int_mode instead of

>         GEN_INT, and ix86_build_const_vector instead of gen_rtvec and

>         gen_rtx_CONT_VECTOR.


OK.

Thanks,
Uros.

> --- gcc/config/i386/sse.md.jj   2020-08-25 13:46:35.669087203 +0200

> +++ gcc/config/i386/sse.md      2020-08-29 10:23:57.747456523 +0200

> @@ -16938,11 +16938,8 @@ (define_insn_and_split "ssse3_pshufbv8qi

>                                 GET_MODE (operands[2]));

>    operands[4] = lowpart_subreg (V16QImode, operands[3],

>                                 GET_MODE (operands[3]));

> -  rtvec par = gen_rtvec (4, GEN_INT (0xf7f7f7f7),

> -                        GEN_INT (0xf7f7f7f7),

> -                        GEN_INT (0xf7f7f7f7),

> -                        GEN_INT (0xf7f7f7f7));

> -  rtx vec_const = gen_rtx_CONST_VECTOR (V4SImode, par);

> +  rtx vec_const = ix86_build_const_vector (V4SImode, true,

> +                                          gen_int_mode (0xf7f7f7f7, SImode));

>    operands[5] = force_const_mem (V4SImode, vec_const);

>  }

>    [(set_attr "mmx_isa" "native,sse_noavx,avx")

>

>         Jakub

>

Patch

--- gcc/config/i386/sse.md.jj	2020-08-25 13:46:35.669087203 +0200
+++ gcc/config/i386/sse.md	2020-08-29 10:23:57.747456523 +0200
@@ -16938,11 +16938,8 @@  (define_insn_and_split "ssse3_pshufbv8qi
 				GET_MODE (operands[2]));
   operands[4] = lowpart_subreg (V16QImode, operands[3],
 				GET_MODE (operands[3]));
-  rtvec par = gen_rtvec (4, GEN_INT (0xf7f7f7f7),
-			 GEN_INT (0xf7f7f7f7),
-			 GEN_INT (0xf7f7f7f7),
-			 GEN_INT (0xf7f7f7f7));
-  rtx vec_const = gen_rtx_CONST_VECTOR (V4SImode, par);
+  rtx vec_const = ix86_build_const_vector (V4SImode, true,
+					   gen_int_mode (0xf7f7f7f7, SImode));
   operands[5] = force_const_mem (V4SImode, vec_const);
 }
   [(set_attr "mmx_isa" "native,sse_noavx,avx")