Fix ICE PR94144

Message ID gkry2rrxf2g.fsf@arm.com
State New
Headers show
Series
  • Fix ICE PR94144
Related show

Commit Message

Andrea Corallo March 23, 2020, 3:32 p.m.
Hi all,

I'd like to submit this for PR94144.

The patch prevent 'simplify_logical_relational_operation' to generate
insn with a float only operator with non float operands.


In the PR the following

(ior:SI (gt:SI (reg:CC 66 cc)
               (const_int 0 [0]))
	(le:SI (reg:CC 66 cc)
               (const_int 0 [0])))

was simplified into

(ordered:SI (reg:CC 66 cc)
	    (const_int 0 [0]))

causing ICE.

Bootstrapped on x86_64-linux-gnu and aarch64-unknown-linux-gnu does
not introduce testsuite regressions.

Andrea

gcc/ChangeLog

2020-??-??  Andrea Corallo  <andrea.corallo@arm.com>

	PR target/94144
	* simplify-rtx.c (simplify_logical_relational_operation): Guard
	against incoherent insn generation.

gcc/testsuite/ChangeLog

2020-??-??  Andrea Corallo  <andrea.corallo@arm.com>

	PR target/94144
	* gcc.dg/pr94144.c: New test.

Comments

Sergei Trofimovich via Gcc-patches March 23, 2020, 3:51 p.m. | #1
On Mon, 2020-03-23 at 16:32 +0100, Andrea Corallo wrote:
> Hi all,

> 

> I'd like to submit this for PR94144.

> 

> The patch prevent 'simplify_logical_relational_operation' to generate

> insn with a float only operator with non float operands.

> 

> 

> In the PR the following

> 

> (ior:SI (gt:SI (reg:CC 66 cc)

>                (const_int 0 [0]))

> 	(le:SI (reg:CC 66 cc)

>                (const_int 0 [0])))

> 

> was simplified into

> 

> (ordered:SI (reg:CC 66 cc)

> 	    (const_int 0 [0]))

> 

> causing ICE.

> 

> Bootstrapped on x86_64-linux-gnu and aarch64-unknown-linux-gnu does

> not introduce testsuite regressions.

> 

> Andrea

> 

> gcc/ChangeLog

> 

> 2020-??-??  Andrea Corallo  <andrea.corallo@arm.com>

> 

> 	PR target/94144

> 	* simplify-rtx.c (simplify_logical_relational_operation): Guard

> 	against incoherent insn generation.

I've got a more complete fix for this that I'll be submitting today.
jeff

Patch

From c2e9e920f4b65327753e75cede3312e70154190b Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Fri, 20 Mar 2020 16:36:40 +0000
Subject: [PATCH] PR94144

---
 gcc/simplify-rtx.c             | 13 +++++++++++++
 gcc/testsuite/gcc.dg/pr94144.c | 24 ++++++++++++++++++++++++
 2 files changed, 37 insertions(+)
 create mode 100644 gcc/testsuite/gcc.dg/pr94144.c

diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index dd3d85156c3e..758088ce5b97 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -2255,6 +2255,19 @@  simplify_logical_relational_operation (enum rtx_code code, machine_mode mode,
   op0 = XEXP (op1, 0);
   op1 = XEXP (op1, 1);
 
+  /* If 'code' is floating point only then the two ops must both be
+     float, otherwise give up.  */
+  if ((!FLOAT_MODE_P (GET_MODE (op0))
+       || !FLOAT_MODE_P (GET_MODE (op1)))
+      && (code == ORDERED
+	  || code == UNORDERED
+	  || code == UNLT
+	  || code == UNLE
+	  || code == UNGT
+	  || code == UNGE
+	  || code == UNEQ))
+    return 0;
+
   return simplify_gen_relational (code, mode, VOIDmode, op0, op1);
 }
 
diff --git a/gcc/testsuite/gcc.dg/pr94144.c b/gcc/testsuite/gcc.dg/pr94144.c
new file mode 100644
index 000000000000..ed8cee7ce591
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94144.c
@@ -0,0 +1,24 @@ 
+/* PR target/94144 */
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+int a, b, z;
+int c(int d, int e) {
+  return d && e > 0 && d > 5 - e ? 0 : d + e;
+}
+int k();
+
+void h(int);
+
+void f(short d) {
+  int g = !(0 < d);
+  h(d);
+  if (b) {
+    unsigned i[1];
+    i[0] = g = 0;
+    for (; g <= 8; g++)
+      d || k();
+    if (c(!(i[0] <= z) >= d, d) != a)
+      k();
+  }
+}
-- 
2.17.1