[committed] arc: Update tumaddsidi4 test.

Message ID 20200306143942.192613-1-claziss@gmail.com
State New
Headers show
Series
  • [committed] arc: Update tumaddsidi4 test.
Related show

Commit Message

Claudiu Zissulescu March 6, 2020, 2:39 p.m.
The test is using -O1 and, the macu instruction is generated by the
combiner and not in the expand step. My previous "arc: Improve code
gen for 64bit add/sub operations." is actually splitting the 64-bit
add in the expand, leading to the impossibility to match the multiply
and accumulate on 64 bit datum by the combiner, hence, the error. This
patch is stepping up the optimization level which will generate the
macu instruction at the expand time.

xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/tumaddsidi4.c: Step-up optimization level.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>

---
 gcc/testsuite/ChangeLog                    | 4 ++++
 gcc/testsuite/gcc.target/arc/tumaddsidi4.c | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

-- 
2.24.1

Comments

Jeff Law March 6, 2020, 3:25 p.m. | #1
On Fri, 2020-03-06 at 16:39 +0200, Claudiu Zissulescu wrote:
> The test is using -O1 and, the macu instruction is generated by the

> combiner and not in the expand step. My previous "arc: Improve code

> gen for 64bit add/sub operations." is actually splitting the 64-bit

> add in the expand, leading to the impossibility to match the multiply

> and accumulate on 64 bit datum by the combiner, hence, the error. This

> patch is stepping up the optimization level which will generate the

> macu instruction at the expand time.

> 

> xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

> 

> 	* gcc.target/arc/tumaddsidi4.c: Step-up optimization level.

THanks.  I've started an off-cycle spin on the ARC toolchain:

http://gcc.gnu.org/jenkins/job/arc-elf/609/

Jeff

Patch

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 13da5a8581d..ea9bc42ff75 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@ 
+2020-03-06  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* gcc.target/arc/tumaddsidi4.c: Step-up optimization level.
+
 2020-03-06  Delia Burduv  <delia.burduv@arm.com>
 
 	* gcc.target/arm/simd/bf16_vldn_1.c: New test.
diff --git a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
index d5dc2944d9b..0298a2456f5 100644
--- a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
+++ b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-mcpu=archs -O1 -mmpy-option=plus_dmpy -w" } */
+/* { dg-options "-mcpu=archs -O2 -mmpy-option=plus_dmpy -w" } */
 
 /* Check how we generate umaddsidi4 patterns.  */
 long a;
@@ -11,4 +11,4 @@  void fn1(void)
   b = d * (long long)c + a;
 }
 
-/* { dg-final { scan-assembler "macu 0,r" } } */
+/* { dg-final { scan-assembler "macu" } } */