x86: Set Vex=1 on VEX.128 only vmovq

Message ID 20180915215342.21963-1-hjl.tools@gmail.com
State New
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Series
  • x86: Set Vex=1 on VEX.128 only vmovq
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Commit Message

H.J. Lu Sept. 15, 2018, 9:53 p.m.
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be
encoded with VEX.128.  Set Vex=1 on VEX.128 only vmovq and update
assembler tests.

gas/

	PR gas/23665
	* testsuite/gas/i386/avx-scalar-intel.d: Updated.
	* testsuite/gas/i386/avx-scalar.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-scalar.d: Likewise.

opcodes/

	PR gas/23665
	* i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
	VEX_LEN_0FD6_P_2 entries.
	* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
	* i386-tbl.h: Regenerated.
---
 gas/ChangeLog                                    |  8 ++++++++
 gas/testsuite/gas/i386/avx-scalar-intel.d        | 16 ++++++++--------
 gas/testsuite/gas/i386/avx-scalar.d              | 16 ++++++++--------
 gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d | 16 ++++++++--------
 gas/testsuite/gas/i386/x86-64-avx-scalar.d       | 16 ++++++++--------
 opcodes/ChangeLog                                |  8 ++++++++
 opcodes/i386-dis.c                               |  2 --
 opcodes/i386-opc.tbl                             |  4 ++--
 opcodes/i386-tbl.h                               |  4 ++--
 9 files changed, 52 insertions(+), 38 deletions(-)

-- 
2.17.1

Comments

Jan Beulich Sept. 16, 2018, 8:37 a.m. | #1
>>> "H.J. Lu" <hjl.tools@gmail.com> 09/15/18 11:54 PM >>>

>AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be

>encoded with VEX.128.  Set Vex=1 on VEX.128 only vmovq and update

>assembler tests.


Indeed, but ...


>--- a/opcodes/i386-opc.tbl

>+++ b/opcodes/i386-opc.tbl

>@@ -2030,8 +2030,8 @@ vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|

>vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }

 >vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }

>vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }

>-vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }

>-vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

>+vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }

>+vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

>vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }

>vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }

>vmovsd, 3, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }


... you then also ought to change the respective SSE2AVX movq instances (one of the
undesirable side effects of these requiring separate templates). Furthermore their AVX512
counterparts appear to have the same issue, using Evex=4 currently instead of Evex=2.
And yet further, the other encodings (with the 32-bit variants named VMOVD) all look to
have the same issue as well.


Jan
H.J. Lu Sept. 16, 2018, 12:18 p.m. | #2
On Sun, Sep 16, 2018 at 1:37 AM, Jan Beulich <jbeulich@suse.com> wrote:
>>>> "H.J. Lu" <hjl.tools@gmail.com> 09/15/18 11:54 PM >>>

>>AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be

>>encoded with VEX.128.  Set Vex=1 on VEX.128 only vmovq and update

>>assembler tests.

>

> Indeed, but ...

>

>

>>--- a/opcodes/i386-opc.tbl

>>+++ b/opcodes/i386-opc.tbl

>>@@ -2030,8 +2030,8 @@ vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|

>>vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }

>  >vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }

>>vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }

>>-vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }

>>-vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

>>+vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }

>>+vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

>>vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }

>>vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }

>>vmovsd, 3, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }

>

> ... you then also ought to change the respective SSE2AVX movq instances (one of the

> undesirable side effects of these requiring separate templates). Furthermore their AVX512

> counterparts appear to have the same issue, using Evex=4 currently instead of Evex=2.

> And yet further, the other encodings (with the 32-bit variants named VMOVD) all look to

> have the same issue as well.


I will check.

-- 
H.J.
H.J. Lu Sept. 16, 2018, 3:07 p.m. | #3
On Sun, Sep 16, 2018 at 5:18 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Sun, Sep 16, 2018 at 1:37 AM, Jan Beulich <jbeulich@suse.com> wrote:

>>>>> "H.J. Lu" <hjl.tools@gmail.com> 09/15/18 11:54 PM >>>

>>>AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be

>>>encoded with VEX.128.  Set Vex=1 on VEX.128 only vmovq and update

>>>assembler tests.

>>

>> Indeed, but ...

>>

>>

>>>--- a/opcodes/i386-opc.tbl

>>>+++ b/opcodes/i386-opc.tbl

>>>@@ -2030,8 +2030,8 @@ vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|

>>>vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }

>>  >vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }

>>>vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }

>>>-vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }

>>>-vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

>>>+vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }

>>>+vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

>>>vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }

>>>vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }

>>>vmovsd, 3, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }

>>

>> ... you then also ought to change the respective SSE2AVX movq instances (one of the


It fixed on users/hjl/wig branch.

>> undesirable side effects of these requiring separate templates). Furthermore their AVX512

>> counterparts appear to have the same issue, using Evex=4 currently instead of Evex=2.

>> And yet further, the other encodings (with the 32-bit variants named VMOVD) all look to

>> have the same issue as well.

>

> I will check.


I opened:

https://sourceware.org/bugzilla/show_bug.cgi?id=23670


-- 
H.J.
Jan Beulich Sept. 17, 2018, 12:20 p.m. | #4
>>> On 16.09.18 at 17:07, <hjl.tools@gmail.com> wrote:

> On Sun, Sep 16, 2018 at 5:18 AM, H.J. Lu <hjl.tools@gmail.com> wrote:

>> On Sun, Sep 16, 2018 at 1:37 AM, Jan Beulich <jbeulich@suse.com> wrote:

>>>>>> "H.J. Lu" <hjl.tools@gmail.com> 09/15/18 11:54 PM >>>

>>>>AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be

>>>>encoded with VEX.128.  Set Vex=1 on VEX.128 only vmovq and update

>>>>assembler tests.

>>>

>>> Indeed, but ...

>>>

>>>

>>>>--- a/opcodes/i386-opc.tbl

>>>>+++ b/opcodes/i386-opc.tbl

>>>>@@ -2030,8 +2030,8 @@ vmovntdq, 2, 0x66e7, None, 1, CpuAVX, 

> Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|

>>>>vmovntdqa, 2, 0x662a, None, 1, CpuAVX, 

> Modrm|Vex|VexOpcode=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf

> , { Xmmword|Unspecified|BaseIndex, RegXMM }

>>>  >vmovntpd, 2, 0x662b, None, 1, CpuAVX, 

> Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_

> qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }

>>>>vmovntps, 2, 0x2b, None, 1, CpuAVX, 

> Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_

> qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }

>>>>-vmovq, 2, 0xf37e, None, 1, CpuAVX, 

> Load|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSu

> f|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }

>>>>-vmovq, 2, 0x66d6, None, 1, CpuAVX, 

> Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_

> qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

>>>>+vmovq, 2, 0xf37e, None, 1, CpuAVX, 

> Load|Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSu

> f|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }

>>>>+vmovq, 2, 0x66d6, None, 1, CpuAVX, 

> Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_

> qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

>>>>vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, 

> D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N

> o_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }

>>>>vmovsd, 2, 0xf210, None, 1, CpuAVX, 

> D|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N

> o_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }

>>>>vmovsd, 3, 0xf210, None, 1, CpuAVX, 

> D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No

> _qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }

>>>

>>> ... you then also ought to change the respective SSE2AVX movq instances (one 

> of the

> 

> It fixed on users/hjl/wig branch.


The two top-most commits, aiui. This looks fine then, thanks.

Jan

Patch

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2a0d429aed..ca20c80cf1 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@ 
+2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/23665
+	* testsuite/gas/i386/avx-scalar-intel.d: Updated.
+	* testsuite/gas/i386/avx-scalar.d: Likewise.
+	* testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise.
+	* testsuite/gas/i386/x86-64-avx-scalar.d: Likewise.
+
 2018-09-15  Alan Modra  <amodra@gmail.com>
 
 	* testsuite/config/default.exp: Make tmpdir.
diff --git a/gas/testsuite/gas/i386/avx-scalar-intel.d b/gas/testsuite/gas/i386/avx-scalar-intel.d
index 83837d30e3..b02ea19dd5 100644
--- a/gas/testsuite/gas/i386/avx-scalar-intel.d
+++ b/gas/testsuite/gas/i386/avx-scalar-intel.d
@@ -15,8 +15,8 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fd 2e 21          	vucomisd xmm4,QWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	c5 ff 10 21          	vmovsd xmm4,QWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	c5 ff 11 21          	vmovsd QWORD PTR \[ecx\],xmm4
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  QWORD PTR \[ecx\],xmm4
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  xmm4,QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  QWORD PTR \[ecx\],xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  xmm4,QWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	c5 ff 2d cc          	vcvtsd2si ecx,xmm4
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si ecx,QWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	c5 ff 2c cc          	vcvttsd2si ecx,xmm4
@@ -211,7 +211,7 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 ce c2 11 07       	vcmpordss xmm2,xmm6,DWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a d4 07    	vroundss xmm2,xmm6,xmm4,0x7
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7
-[ 	]*[a-f0-9]+:	c5 fe 7e f4          	vmovq  xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 cf 10 d4          	vmovsd xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 ce 10 d4          	vmovss xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 fd 7e 05 34 12 00 00 	vmovd  DWORD PTR ds:0x1234,xmm0
@@ -246,10 +246,10 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 ff 10 21          	vmovsd xmm4,QWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	c5 ff 11 21          	vmovsd QWORD PTR \[ecx\],xmm4
 [ 	]*[a-f0-9]+:	c5 ff 11 21          	vmovsd QWORD PTR \[ecx\],xmm4
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  QWORD PTR \[ecx\],xmm4
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  xmm4,QWORD PTR \[ecx\]
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  QWORD PTR \[ecx\],xmm4
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  xmm4,QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  QWORD PTR \[ecx\],xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  xmm4,QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  QWORD PTR \[ecx\],xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  xmm4,QWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	c5 ff 2d cc          	vcvtsd2si ecx,xmm4
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si ecx,QWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si ecx,QWORD PTR \[ecx\]
@@ -542,7 +542,7 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a d4 07    	vroundss xmm2,xmm6,xmm4,0x7
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7
-[ 	]*[a-f0-9]+:	c5 fe 7e f4          	vmovq  xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 cf 10 d4          	vmovsd xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 ce 10 d4          	vmovss xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 fd 7e 05 34 12 00 00 	vmovd  DWORD PTR ds:0x1234,xmm0
diff --git a/gas/testsuite/gas/i386/avx-scalar.d b/gas/testsuite/gas/i386/avx-scalar.d
index b1a89e5cf6..0d20bd56e3 100644
--- a/gas/testsuite/gas/i386/avx-scalar.d
+++ b/gas/testsuite/gas/i386/avx-scalar.d
@@ -14,8 +14,8 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fd 2e 21          	vucomisd \(%ecx\),%xmm4
 [ 	]*[a-f0-9]+:	c5 ff 10 21          	vmovsd \(%ecx\),%xmm4
 [ 	]*[a-f0-9]+:	c5 ff 11 21          	vmovsd %xmm4,\(%ecx\)
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  %xmm4,\(%ecx\)
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  \(%ecx\),%xmm4
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  %xmm4,\(%ecx\)
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  \(%ecx\),%xmm4
 [ 	]*[a-f0-9]+:	c5 ff 2d cc          	vcvtsd2si %xmm4,%ecx
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si \(%ecx\),%ecx
 [ 	]*[a-f0-9]+:	c5 ff 2c cc          	vcvttsd2si %xmm4,%ecx
@@ -210,7 +210,7 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 ce c2 11 07       	vcmpordss \(%ecx\),%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a d4 07    	vroundss \$0x7,%xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss \$0x7,\(%ecx\),%xmm6,%xmm2
-[ 	]*[a-f0-9]+:	c5 fe 7e f4          	vmovq  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 cf 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c5 ce 10 d4          	vmovss %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c5 fd 7e 05 34 12 00 00 	vmovd  %xmm0,0x1234
@@ -245,10 +245,10 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 ff 10 21          	vmovsd \(%ecx\),%xmm4
 [ 	]*[a-f0-9]+:	c5 ff 11 21          	vmovsd %xmm4,\(%ecx\)
 [ 	]*[a-f0-9]+:	c5 ff 11 21          	vmovsd %xmm4,\(%ecx\)
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  %xmm4,\(%ecx\)
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  \(%ecx\),%xmm4
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  %xmm4,\(%ecx\)
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  \(%ecx\),%xmm4
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  %xmm4,\(%ecx\)
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  \(%ecx\),%xmm4
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  %xmm4,\(%ecx\)
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  \(%ecx\),%xmm4
 [ 	]*[a-f0-9]+:	c5 ff 2d cc          	vcvtsd2si %xmm4,%ecx
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si \(%ecx\),%ecx
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si \(%ecx\),%ecx
@@ -541,7 +541,7 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a d4 07    	vroundss \$0x7,%xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss \$0x7,\(%ecx\),%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss \$0x7,\(%ecx\),%xmm6,%xmm2
-[ 	]*[a-f0-9]+:	c5 fe 7e f4          	vmovq  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 cf 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c5 ce 10 d4          	vmovss %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c5 fd 7e 05 34 12 00 00 	vmovd  %xmm0,0x1234
diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d b/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d
index 8766c7c217..6362bf170f 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d
@@ -19,8 +19,8 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c4 e1 fd 6e e1       	vmovq  xmm4,rcx
 [ 	]*[a-f0-9]+:	c4 e1 fd 7e e1       	vmovq  rcx,xmm4
 [ 	]*[a-f0-9]+:	c4 e1 fd 6e e1       	vmovq  xmm4,rcx
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  QWORD PTR \[rcx\],xmm4
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  xmm4,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  QWORD PTR \[rcx\],xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  xmm4,QWORD PTR \[rcx\]
 [ 	]*[a-f0-9]+:	c5 ff 2d cc          	vcvtsd2si ecx,xmm4
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si ecx,QWORD PTR \[rcx\]
 [ 	]*[a-f0-9]+:	c5 ff 2c cc          	vcvttsd2si ecx,xmm4
@@ -227,7 +227,7 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 ce c2 11 07       	vcmpordss xmm2,xmm6,DWORD PTR \[rcx\]
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a d4 07    	vroundss xmm2,xmm6,xmm4,0x7
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7
-[ 	]*[a-f0-9]+:	c5 fe 7e f4          	vmovq  xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 cf 10 d4          	vmovsd xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 ce 10 d4          	vmovss xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 7d 7e 04 25 78 56 34 12 	vmovd  DWORD PTR ds:0x12345678,xmm8
@@ -283,10 +283,10 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fd 6e 21          	vmovd  xmm4,DWORD PTR \[rcx\]
 [ 	]*[a-f0-9]+:	c4 e1 fd 7e e1       	vmovq  rcx,xmm4
 [ 	]*[a-f0-9]+:	c4 e1 fd 6e e1       	vmovq  xmm4,rcx
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  QWORD PTR \[rcx\],xmm4
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  xmm4,QWORD PTR \[rcx\]
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  QWORD PTR \[rcx\],xmm4
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  xmm4,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  QWORD PTR \[rcx\],xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  xmm4,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  QWORD PTR \[rcx\],xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  xmm4,QWORD PTR \[rcx\]
 [ 	]*[a-f0-9]+:	c5 ff 2d cc          	vcvtsd2si ecx,xmm4
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si ecx,QWORD PTR \[rcx\]
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si ecx,QWORD PTR \[rcx\]
@@ -595,7 +595,7 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a d4 07    	vroundss xmm2,xmm6,xmm4,0x7
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7
-[ 	]*[a-f0-9]+:	c5 fe 7e f4          	vmovq  xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 cf 10 d4          	vmovsd xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 ce 10 d4          	vmovss xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 7d 7e 04 25 78 56 34 12 	vmovd  DWORD PTR ds:0x12345678,xmm8
diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar.d b/gas/testsuite/gas/i386/x86-64-avx-scalar.d
index f93413d917..93f14fd9bd 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-scalar.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-scalar.d
@@ -18,8 +18,8 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c4 e1 fd 6e e1       	vmovq  %rcx,%xmm4
 [ 	]*[a-f0-9]+:	c4 e1 fd 7e e1       	vmovq  %xmm4,%rcx
 [ 	]*[a-f0-9]+:	c4 e1 fd 6e e1       	vmovq  %rcx,%xmm4
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  %xmm4,\(%rcx\)
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  \(%rcx\),%xmm4
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  %xmm4,\(%rcx\)
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  \(%rcx\),%xmm4
 [ 	]*[a-f0-9]+:	c5 ff 2d cc          	vcvtsd2si %xmm4,%ecx
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si \(%rcx\),%ecx
 [ 	]*[a-f0-9]+:	c5 ff 2c cc          	vcvttsd2si %xmm4,%ecx
@@ -226,7 +226,7 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 ce c2 11 07       	vcmpordss \(%rcx\),%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a d4 07    	vroundss \$0x7,%xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss \$0x7,\(%rcx\),%xmm6,%xmm2
-[ 	]*[a-f0-9]+:	c5 fe 7e f4          	vmovq  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 cf 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c5 ce 10 d4          	vmovss %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c5 7d 7e 04 25 78 56 34 12 	vmovd  %xmm8,0x12345678
@@ -282,10 +282,10 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fd 6e 21          	vmovd  \(%rcx\),%xmm4
 [ 	]*[a-f0-9]+:	c4 e1 fd 7e e1       	vmovq  %xmm4,%rcx
 [ 	]*[a-f0-9]+:	c4 e1 fd 6e e1       	vmovq  %rcx,%xmm4
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  %xmm4,\(%rcx\)
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  \(%rcx\),%xmm4
-[ 	]*[a-f0-9]+:	c5 fd d6 21          	vmovq  %xmm4,\(%rcx\)
-[ 	]*[a-f0-9]+:	c5 fe 7e 21          	vmovq  \(%rcx\),%xmm4
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  %xmm4,\(%rcx\)
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  \(%rcx\),%xmm4
+[ 	]*[a-f0-9]+:	c5 f9 d6 21          	vmovq  %xmm4,\(%rcx\)
+[ 	]*[a-f0-9]+:	c5 fa 7e 21          	vmovq  \(%rcx\),%xmm4
 [ 	]*[a-f0-9]+:	c5 ff 2d cc          	vcvtsd2si %xmm4,%ecx
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si \(%rcx\),%ecx
 [ 	]*[a-f0-9]+:	c5 ff 2d 09          	vcvtsd2si \(%rcx\),%ecx
@@ -594,7 +594,7 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a d4 07    	vroundss \$0x7,%xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss \$0x7,\(%rcx\),%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c4 e3 4d 0a 11 07    	vroundss \$0x7,\(%rcx\),%xmm6,%xmm2
-[ 	]*[a-f0-9]+:	c5 fe 7e f4          	vmovq  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 cf 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c5 ce 10 d4          	vmovss %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	c5 7d 7e 04 25 78 56 34 12 	vmovd  %xmm8,0x12345678
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7d5f796a77..408512c5bf 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@ 
+2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/23665
+	* i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
+	VEX_LEN_0FD6_P_2 entries.
+	* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
+	* i386-tbl.h: Regenerated.
+
 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR gas/23642
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 9453e52d64..52521745bc 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9848,7 +9848,6 @@  static const struct dis386 vex_len_table[][2] = {
   /* VEX_LEN_0F7E_P_1 */
   {
     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
-    { VEX_W_TABLE (VEX_W_0F7E_P_1) },
   },
 
   /* VEX_LEN_0F7E_P_2 */
@@ -9962,7 +9961,6 @@  static const struct dis386 vex_len_table[][2] = {
   /* VEX_LEN_0FD6_P_2 */
   {
     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
-    { VEX_W_TABLE (VEX_W_0FD6_P_2) },
   },
 
   /* VEX_LEN_0FF7_P_2 */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 5a8e79ca77..d37a08c20d 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2030,8 +2030,8 @@  vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|
 vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }
 vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
 vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
-vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
+vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
 vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
 vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
 vmovsd, 3, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 8966d5201b..f99daa0a01 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -36679,7 +36679,7 @@  const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
-      3, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      1, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
 	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0,
@@ -36696,7 +36696,7 @@  const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
-      3, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      1, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,