[rs6000] Updates for vec_abs() gimple-folding vector tests

Message ID 1516812362.11602.239.camel@brimstone.rchland.ibm.com
State New
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  • [rs6000] Updates for vec_abs() gimple-folding vector tests
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Commit Message

will schmidt Jan. 24, 2018, 4:46 p.m.
Hi,

Assorted testcase updates to handle codegen variations between P7,p8,p9.
This breaks out the tests into p7,p8,p9 -specific versions of the same.

Sniff-tested on multiple systems, this clears up multiple errors
currently seen on P9.

OK for trunk?
Thanks
-Will

    
[testsuite]
    
2018-01-24  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-abs-int.c:  remove scan-assembler stanzas.
	* gcc.target/powerpc/fold-vec-abs-int-fwrap.c:  Same.
	* gcc.target/powerpc/fold-vec-abs-int.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-int.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-int.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.c:  remove scan-assembler stanzas.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrap.c:  Same.
	* gcc.target/powerpc/fold-vec-abs-longlong.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p7.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: New.
	* gcc.target/powerpc/fold-vec-abs-short.c:  Add xxspltib to valid instruction list.
	* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c:  Same.

Comments

Segher Boessenkool Jan. 25, 2018, 7:15 p.m. | #1
Hi!

On Wed, Jan 24, 2018 at 10:46:02AM -0600, Will Schmidt wrote:
> 2018-01-24  Will Schmidt  <will_schmidt@vnet.ibm.com>

> 

> 	* gcc.target/powerpc/fold-vec-abs-int.c:  remove scan-assembler stanzas.


Only one space after : and start with a cap.

> 	* gcc.target/powerpc/fold-vec-abs-int-fwrap.c:  Same.

> 	* gcc.target/powerpc/fold-vec-abs-int.p7.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-int.p8.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-int.p9.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-longlong.c:  remove scan-assembler stanzas.

> 	* gcc.target/powerpc/fold-vec-abs-longlong-fwrap.c:  Same.

> 	* gcc.target/powerpc/fold-vec-abs-longlong.p7.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-longlong.p8.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-longlong.p9.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p7.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: New.

> 	* gcc.target/powerpc/fold-vec-abs-short.c:  Add xxspltib to valid instruction list.

> 	* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c:  Same.


More of that in the other entries, please check all.

This looks fine.  One question: should we also test expected code
generation for systems that only have AltiVec, not VSX?  So something
older than p7?  That goes for this whole series of course.

But, okay for trunk either way.  Thanks!


Segher

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
index 34dead4..22eec38 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
@@ -11,8 +11,6 @@  vector signed int
 test1 (vector signed int x)
 {
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-int-fwrapv.p*.c tests.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c
new file mode 100644
index 0000000..739f1c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c
@@ -0,0 +1,20 @@ 
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power7 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power7 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c
new file mode 100644
index 0000000..8c284ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c
@@ -0,0 +1,20 @@ 
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power8 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power8 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c
new file mode 100644
index 0000000..cde86b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c
@@ -0,0 +1,19 @@ 
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results when -mcpu=power9 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power9 -fwrapv" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegw" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
index 77d9ca5..4fb3fbe 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
@@ -11,8 +11,6 @@  vector signed int
 test1 (vector signed int x)
 {
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+/* scan-assembler entries moved to fold-vec-abs-int.p*.c files. */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c
new file mode 100644
index 0000000..81b0fc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p7.c
@@ -0,0 +1,19 @@ 
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power7 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power7" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c
new file mode 100644
index 0000000..4e55e0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p8.c
@@ -0,0 +1,20 @@ 
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power8 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c
new file mode 100644
index 0000000..6f2c686
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c
@@ -0,0 +1,18 @@ 
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right code when -mcpu=power9 is specified.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegw" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
index 934618b..6c3108c 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
@@ -11,8 +11,7 @@  vector signed long long
 test3 (vector signed long long x)
 {
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-longlong.p*.c.  */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c
new file mode 100644
index 0000000..244c247
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c
@@ -0,0 +1,20 @@ 
+
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c
new file mode 100644
index 0000000..8f1545d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c
@@ -0,0 +1,18 @@ 
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mpower9-vector -O2 -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegd" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
index 5b59d19..4f5148e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
@@ -11,8 +11,6 @@  vector signed long long
 test3 (vector signed long long x)
 {
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
+/* scan-assembler stanzas moved to fold-vec-abs-longlong.p*.c . */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c
new file mode 100644
index 0000000..4fa0b6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c
@@ -0,0 +1,18 @@ 
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c
new file mode 100644
index 0000000..16906ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c
@@ -0,0 +1,17 @@ 
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mpower9-vector -O2 -mcpu=power9" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegd" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
index 2562179..a1e0e05 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
@@ -11,8 +11,8 @@  vector signed short
 test3 (vector signed short x)
 {
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "xxspltib|vspltisw|vxor" 1 } } */
 /* { dg-final { scan-assembler-times "vsubuhm" 1 } } */
 /* { dg-final { scan-assembler-times "vmaxsh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
index d312000..3cb4d83 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
@@ -11,8 +11,8 @@  vector signed short
 test3 (vector signed short x)
 {
   return vec_abs (x);
 }
 
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "xxspltib|vspltisw|vxor" 1 } } */
 /* { dg-final { scan-assembler-times "vsubuhm" 1 } } */
 /* { dg-final { scan-assembler-times "vmaxsh" 1 } } */