[committed] RISC-V: Accept constant operands in la and lla

Message ID 20180620052725.20998-1-sebastian.huber@embedded-brains.de
State New
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  • [committed] RISC-V: Accept constant operands in la and lla
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Commit Message

Sebastian Huber June 20, 2018, 5:27 a.m.
opcodes/
	PR gas/23305
	* riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
	la and lla.

gas/
	PR gas/23305
	* config/tc-riscv.c (riscv_ip): Add format specifier 'B' for
	constants and symbols.
	* testsuite/gas/riscv/lla32.d: New file.
	* testsuite/gas/riscv/lla32.s: Likewise.
	* testsuite/gas/riscv/lla64-fail.d: Likewise.
	* testsuite/gas/riscv/lla64-fail.l: Likewise.
	* testsuite/gas/riscv/lla64-fail.s: Likewise.
	* testsuite/gas/riscv/lla64.d: Likewise.
	* testsuite/gas/riscv/lla64.s: Likewise.
---
 gas/ChangeLog                        | 13 +++++++++++++
 gas/config/tc-riscv.c                | 11 +++++++++++
 gas/testsuite/gas/riscv/lla32.d      | 19 +++++++++++++++++++
 gas/testsuite/gas/riscv/lla32.s      | 15 +++++++++++++++
 gas/testsuite/gas/riscv/lla64-fail.d |  3 +++
 gas/testsuite/gas/riscv/lla64-fail.l |  2 ++
 gas/testsuite/gas/riscv/lla64-fail.s |  3 +++
 gas/testsuite/gas/riscv/lla64.d      | 20 ++++++++++++++++++++
 gas/testsuite/gas/riscv/lla64.s      | 17 +++++++++++++++++
 opcodes/ChangeLog                    |  6 ++++++
 opcodes/riscv-opc.c                  |  4 ++--
 11 files changed, 111 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/lla32.d
 create mode 100644 gas/testsuite/gas/riscv/lla32.s
 create mode 100644 gas/testsuite/gas/riscv/lla64-fail.d
 create mode 100644 gas/testsuite/gas/riscv/lla64-fail.l
 create mode 100644 gas/testsuite/gas/riscv/lla64-fail.s
 create mode 100644 gas/testsuite/gas/riscv/lla64.d
 create mode 100644 gas/testsuite/gas/riscv/lla64.s

-- 
2.13.7

Comments

Palmer Dabbelt June 20, 2018, 10:53 p.m. | #1
On Tue, 19 Jun 2018 22:27:25 PDT (-0700), sebastian.huber@embedded-brains.de wrote:
> opcodes/

> 	PR gas/23305

> 	* riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for

> 	la and lla.

>

> gas/

> 	PR gas/23305

> 	* config/tc-riscv.c (riscv_ip): Add format specifier 'B' for

> 	constants and symbols.

> 	* testsuite/gas/riscv/lla32.d: New file.

> 	* testsuite/gas/riscv/lla32.s: Likewise.

> 	* testsuite/gas/riscv/lla64-fail.d: Likewise.

> 	* testsuite/gas/riscv/lla64-fail.l: Likewise.

> 	* testsuite/gas/riscv/lla64-fail.s: Likewise.

> 	* testsuite/gas/riscv/lla64.d: Likewise.

> 	* testsuite/gas/riscv/lla64.s: Likewise.

> ---

>  gas/ChangeLog                        | 13 +++++++++++++

>  gas/config/tc-riscv.c                | 11 +++++++++++

>  gas/testsuite/gas/riscv/lla32.d      | 19 +++++++++++++++++++

>  gas/testsuite/gas/riscv/lla32.s      | 15 +++++++++++++++

>  gas/testsuite/gas/riscv/lla64-fail.d |  3 +++

>  gas/testsuite/gas/riscv/lla64-fail.l |  2 ++

>  gas/testsuite/gas/riscv/lla64-fail.s |  3 +++

>  gas/testsuite/gas/riscv/lla64.d      | 20 ++++++++++++++++++++

>  gas/testsuite/gas/riscv/lla64.s      | 17 +++++++++++++++++

>  opcodes/ChangeLog                    |  6 ++++++

>  opcodes/riscv-opc.c                  |  4 ++--

>  11 files changed, 111 insertions(+), 2 deletions(-)

>  create mode 100644 gas/testsuite/gas/riscv/lla32.d

>  create mode 100644 gas/testsuite/gas/riscv/lla32.s

>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.d

>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.l

>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.s

>  create mode 100644 gas/testsuite/gas/riscv/lla64.d

>  create mode 100644 gas/testsuite/gas/riscv/lla64.s


I'm not opposed to this, but did you check with a RISC-V maintainer before 
committing it?  In general we try to keep our assembly syntax compatible 
between the various assemblers, so any interface addition should be discussed 
to make sure it's feasible everywhere.

This addition shouldn't be a problem, though.

> diff --git a/gas/ChangeLog b/gas/ChangeLog

> index 332a063d55..33ba540ed2 100644

> --- a/gas/ChangeLog

> +++ b/gas/ChangeLog

> @@ -1,3 +1,16 @@

> +2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>

> +

> +	PR gas/23305

> +	* config/tc-riscv.c (riscv_ip): Add format specifier 'B' for

> +	constants and symbols.

> +	* testsuite/gas/riscv/lla32.d: New file.

> +	* testsuite/gas/riscv/lla32.s: Likewise.

> +	* testsuite/gas/riscv/lla64-fail.d: Likewise.

> +	* testsuite/gas/riscv/lla64-fail.l: Likewise.

> +	* testsuite/gas/riscv/lla64-fail.s: Likewise.

> +	* testsuite/gas/riscv/lla64.d: Likewise.

> +	* testsuite/gas/riscv/lla64.s: Likewise.

> +

>  2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>

>

>  	* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects.

> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c

> index a0ea87a3fa..bdec30741b 100644

> --- a/gas/config/tc-riscv.c

> +++ b/gas/config/tc-riscv.c

> @@ -1935,6 +1935,17 @@ rvc_lui:

>  	      s = expr_end;

>  	      continue;

>

> +	    case 'B':

> +	      my_getExpression (imm_expr, s);

> +	      normalize_constant_expr (imm_expr);

> +	      /* The 'B' format specifier must be a symbol or a constant.  */

> +	      if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)

> +	        break;

> +	      if (imm_expr->X_op == O_symbol)

> +	        *imm_reloc = BFD_RELOC_32;

> +	      s = expr_end;

> +	      continue;

> +

>  	    case 'j': /* Sign-extended immediate.  */

>  	      *imm_reloc = BFD_RELOC_RISCV_LO12_I;

>  	      p = percent_op_itype;

> diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d

> new file mode 100644

> index 0000000000..ab766b4e3b

> --- /dev/null

> +++ b/gas/testsuite/gas/riscv/lla32.d

> @@ -0,0 +1,19 @@

> +#as: -march=rv32i -mabi=ilp32

> +#objdump: -dr

> +

> +.*:     file format elf32-littleriscv

> +

> +

> +Disassembly of section .text:

> +

> +0+000 <.text>:

> +   0:	00100513          	li	a0,1

> +   4:	00001537          	lui	a0,0x1

> +   8:	00001537          	lui	a0,0x1

> +   c:	00150513          	addi	a0,a0,1 # 1001 <c>

> +  10:	00001537          	lui	a0,0x1

> +  14:	fff50513          	addi	a0,a0,-1 # fff <d>

> +  18:	80000537          	lui	a0,0x80000

> +  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <h\+0x80000000>

> +  20:	00000513          	li	a0,0

> +  24:	fff00513          	li	a0,-1

> diff --git a/gas/testsuite/gas/riscv/lla32.s b/gas/testsuite/gas/riscv/lla32.s

> new file mode 100644

> index 0000000000..8d5773e929

> --- /dev/null

> +++ b/gas/testsuite/gas/riscv/lla32.s

> @@ -0,0 +1,15 @@

> +.set a, 0x1

> +.set b, 0x1000

> +.set c, 0x1001

> +.set d, 0xfff

> +.set e, 0x7fffffff

> +.set g, 0x0

> +.set h, 0xffffffff

> +.text

> +	lla a0, a

> +	lla a0, b

> +	lla a0, c

> +	lla a0, d

> +	lla a0, e

> +	lla a0, g

> +	lla a0, h

> diff --git a/gas/testsuite/gas/riscv/lla64-fail.d b/gas/testsuite/gas/riscv/lla64-fail.d

> new file mode 100644

> index 0000000000..97b2e105c8

> --- /dev/null

> +++ b/gas/testsuite/gas/riscv/lla64-fail.d

> @@ -0,0 +1,3 @@

> +#as: -march=rv64i -mabi=lp64

> +#source: lla64-fail.s

> +#error-output: lla64-fail.l

> diff --git a/gas/testsuite/gas/riscv/lla64-fail.l b/gas/testsuite/gas/riscv/lla64-fail.l

> new file mode 100644

> index 0000000000..088f18e530

> --- /dev/null

> +++ b/gas/testsuite/gas/riscv/lla64-fail.l

> @@ -0,0 +1,2 @@

> +.*: Assembler messages:

> +.*: Error: offset too large

> diff --git a/gas/testsuite/gas/riscv/lla64-fail.s b/gas/testsuite/gas/riscv/lla64-fail.s

> new file mode 100644

> index 0000000000..e8379bfbe8

> --- /dev/null

> +++ b/gas/testsuite/gas/riscv/lla64-fail.s

> @@ -0,0 +1,3 @@

> +.set a, 0xffffffff

> +.text

> +	lla a0, a


I don't think this should fail on 64-bit systems.  We already have patterns to 
make this work for 'li' so it shouldn't be too much extra work.  As it stands 
it's just odd to have la/lla only support some constants.

> diff --git a/gas/testsuite/gas/riscv/lla64.d b/gas/testsuite/gas/riscv/lla64.d

> new file mode 100644

> index 0000000000..7848eecdfb

> --- /dev/null

> +++ b/gas/testsuite/gas/riscv/lla64.d

> @@ -0,0 +1,20 @@

> +#as: -march=rv64i -mabi=lp64

> +#objdump: -dr

> +

> +.*:     file format elf64-littleriscv

> +

> +

> +Disassembly of section .text:

> +

> +0+000 <.text>:

> +   0:	0010051b          	addiw	a0,zero,1

> +   4:	00001537          	lui	a0,0x1

> +   8:	00001537          	lui	a0,0x1

> +   c:	0015051b          	addiw	a0,a0,1

> +  10:	00001537          	lui	a0,0x1

> +  14:	fff5051b          	addiw	a0,a0,-1

> +  18:	80000537          	lui	a0,0x80000

> +  1c:	fff5051b          	addiw	a0,a0,-1

> +  20:	0000051b          	sext.w	a0,zero

> +  24:	fff0051b          	addiw	a0,zero,-1

> +  28:	80000537          	lui	a0,0x80000

> diff --git a/gas/testsuite/gas/riscv/lla64.s b/gas/testsuite/gas/riscv/lla64.s

> new file mode 100644

> index 0000000000..4be5082451

> --- /dev/null

> +++ b/gas/testsuite/gas/riscv/lla64.s

> @@ -0,0 +1,17 @@

> +.set a, 0x1

> +.set b, 0x1000

> +.set c, 0x1001

> +.set d, 0xfff

> +.set e, 0x7fffffff

> +.set g, 0x0

> +.set h, 0xffffffffffffffff

> +.set i, 0xffffffff80000000

> +.text

> +	lla a0, a

> +	lla a0, b

> +	lla a0, c

> +	lla a0, d

> +	lla a0, e

> +	lla a0, g

> +	lla a0, h

> +	lla a0, i

> diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog

> index 0cfb8065ee..c5ef6a367e 100644

> --- a/opcodes/ChangeLog

> +++ b/opcodes/ChangeLog

> @@ -1,3 +1,9 @@

> +2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>

> +

> +	PR gas/23305

> +	* riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for

> +	la and lla.

> +

>  2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>

>

>  	* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.

> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c

> index 47e9659c97..8e55916451 100644

> --- a/opcodes/riscv-opc.c

> +++ b/opcodes/riscv-opc.c

> @@ -278,8 +278,8 @@ const struct riscv_opcode riscv_opcodes[] =

>     applied to an add instruction, for relaxation to use.  */

>  {"add",       "I",   "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },

>  {"add",       "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },

> -{"la",        "I",   "d,A",  0,    (int) M_LA,  match_never, INSN_MACRO },

> -{"lla",       "I",   "d,A",  0,    (int) M_LLA,  match_never, INSN_MACRO },

> +{"la",        "I",   "d,B",  0,    (int) M_LA,  match_never, INSN_MACRO },

> +{"lla",       "I",   "d,B",  0,    (int) M_LLA,  match_never, INSN_MACRO },

>  {"la.tls.gd", "I",   "d,A",  0,    (int) M_LA_TLS_GD,  match_never, INSN_MACRO },

>  {"la.tls.ie", "I",   "d,A",  0,    (int) M_LA_TLS_IE,  match_never, INSN_MACRO },

>  {"neg",       "I",   "d,t",  MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */


Thanks for the patch!
Sebastian Huber June 21, 2018, 4:17 a.m. | #2
On 21/06/18 00:53, Palmer Dabbelt wrote:
> On Tue, 19 Jun 2018 22:27:25 PDT (-0700), 

> sebastian.huber@embedded-brains.de wrote:

>> opcodes/

>>     PR gas/23305

>>     * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for

>>     la and lla.

>>

>> gas/

>>     PR gas/23305

>>     * config/tc-riscv.c (riscv_ip): Add format specifier 'B' for

>>     constants and symbols.

>>     * testsuite/gas/riscv/lla32.d: New file.

>>     * testsuite/gas/riscv/lla32.s: Likewise.

>>     * testsuite/gas/riscv/lla64-fail.d: Likewise.

>>     * testsuite/gas/riscv/lla64-fail.l: Likewise.

>>     * testsuite/gas/riscv/lla64-fail.s: Likewise.

>>     * testsuite/gas/riscv/lla64.d: Likewise.

>>     * testsuite/gas/riscv/lla64.s: Likewise.

>> ---

>>  gas/ChangeLog                        | 13 +++++++++++++

>>  gas/config/tc-riscv.c                | 11 +++++++++++

>>  gas/testsuite/gas/riscv/lla32.d      | 19 +++++++++++++++++++

>>  gas/testsuite/gas/riscv/lla32.s      | 15 +++++++++++++++

>>  gas/testsuite/gas/riscv/lla64-fail.d |  3 +++

>>  gas/testsuite/gas/riscv/lla64-fail.l |  2 ++

>>  gas/testsuite/gas/riscv/lla64-fail.s |  3 +++

>>  gas/testsuite/gas/riscv/lla64.d      | 20 ++++++++++++++++++++

>>  gas/testsuite/gas/riscv/lla64.s      | 17 +++++++++++++++++

>>  opcodes/ChangeLog                    |  6 ++++++

>>  opcodes/riscv-opc.c                  |  4 ++--

>>  11 files changed, 111 insertions(+), 2 deletions(-)

>>  create mode 100644 gas/testsuite/gas/riscv/lla32.d

>>  create mode 100644 gas/testsuite/gas/riscv/lla32.s

>>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.d

>>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.l

>>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.s

>>  create mode 100644 gas/testsuite/gas/riscv/lla64.d

>>  create mode 100644 gas/testsuite/gas/riscv/lla64.s

>

> I'm not opposed to this, but did you check with a RISC-V maintainer 

> before committing it?  In general we try to keep our assembly syntax 

> compatible between the various assemblers, so any interface addition 

> should be discussed to make sure it's feasible everywhere. 


Sorry, I should have mentioned that this was pre-approved by Jim Wilson 
in the referenced PR:

https://sourceware.org/bugzilla/show_bug.cgi?id=23305

Which other assemblers are there to consider?

I try to add a documentation of "lla". See also:

https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/sDQWmHyzHi8

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
Palmer Dabbelt June 21, 2018, 4:06 p.m. | #3
On Wed, 20 Jun 2018 21:17:55 PDT (-0700), sebastian.huber@embedded-brains.de wrote:
> On 21/06/18 00:53, Palmer Dabbelt wrote:

>> On Tue, 19 Jun 2018 22:27:25 PDT (-0700), 

>> sebastian.huber@embedded-brains.de wrote:

>>> opcodes/

>>>     PR gas/23305

>>>     * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for

>>>     la and lla.

>>>

>>> gas/

>>>     PR gas/23305

>>>     * config/tc-riscv.c (riscv_ip): Add format specifier 'B' for

>>>     constants and symbols.

>>>     * testsuite/gas/riscv/lla32.d: New file.

>>>     * testsuite/gas/riscv/lla32.s: Likewise.

>>>     * testsuite/gas/riscv/lla64-fail.d: Likewise.

>>>     * testsuite/gas/riscv/lla64-fail.l: Likewise.

>>>     * testsuite/gas/riscv/lla64-fail.s: Likewise.

>>>     * testsuite/gas/riscv/lla64.d: Likewise.

>>>     * testsuite/gas/riscv/lla64.s: Likewise.

>>> ---

>>>  gas/ChangeLog                        | 13 +++++++++++++

>>>  gas/config/tc-riscv.c                | 11 +++++++++++

>>>  gas/testsuite/gas/riscv/lla32.d      | 19 +++++++++++++++++++

>>>  gas/testsuite/gas/riscv/lla32.s      | 15 +++++++++++++++

>>>  gas/testsuite/gas/riscv/lla64-fail.d |  3 +++

>>>  gas/testsuite/gas/riscv/lla64-fail.l |  2 ++

>>>  gas/testsuite/gas/riscv/lla64-fail.s |  3 +++

>>>  gas/testsuite/gas/riscv/lla64.d      | 20 ++++++++++++++++++++

>>>  gas/testsuite/gas/riscv/lla64.s      | 17 +++++++++++++++++

>>>  opcodes/ChangeLog                    |  6 ++++++

>>>  opcodes/riscv-opc.c                  |  4 ++--

>>>  11 files changed, 111 insertions(+), 2 deletions(-)

>>>  create mode 100644 gas/testsuite/gas/riscv/lla32.d

>>>  create mode 100644 gas/testsuite/gas/riscv/lla32.s

>>>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.d

>>>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.l

>>>  create mode 100644 gas/testsuite/gas/riscv/lla64-fail.s

>>>  create mode 100644 gas/testsuite/gas/riscv/lla64.d

>>>  create mode 100644 gas/testsuite/gas/riscv/lla64.s

>>

>> I'm not opposed to this, but did you check with a RISC-V maintainer 

>> before committing it?  In general we try to keep our assembly syntax 

>> compatible between the various assemblers, so any interface addition 

>> should be discussed to make sure it's feasible everywhere. 

>

> Sorry, I should have mentioned that this was pre-approved by Jim Wilson 

> in the referenced PR:

>

> https://sourceware.org/bugzilla/show_bug.cgi?id=23305


Ah, OK, sorry I missed that.

> Which other assemblers are there to consider?


At least LLVM, which is spinning up.  There's also a bunch of proprietary tools 
companies, which is what I'm more worried about -- I don't want to have to deal 
with users complaining about undocumented assembly extensions those toolchains 
add so it really wouldn't be fair to have stuff of our own.

> I try to add a documentation of "lla". See also:

>

> https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/sDQWmHyzHi8


Thanks.  I suppose this should be documented in the GAS manual, though we don't 
have any of the pseudos in there.  Do you mind adding a section to

    gas/doc/c-riscv.texi

for pseduo ops that contains lla?  We can add the rest later...

Additionally, we've been collecting all the standard interfaces in RISC-V 
specific manuals.  Do you mind adding a bit here about lla (and then modifying 
the la bit to include that it can take constants)

    https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md

I also left a comment in the middle of the source about "lla 0xFFFFFFFF" on 
RV64I, which I think should be supported.

Thanks for the patch, and sorry for making so much more work :)
Sebastian Huber June 22, 2018, 4:17 a.m. | #4
On 21/06/18 18:06, Palmer Dabbelt wrote:
>

>> I try to add a documentation of "lla". See also:

>>

>> https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/sDQWmHyzHi8 

>>

>

> Thanks.  I suppose this should be documented in the GAS manual, though 

> we don't have any of the pseudos in there.  Do you mind adding a 

> section to

>

>    gas/doc/c-riscv.texi

>

> for pseduo ops that contains lla?  We can add the rest later...


Should the GAS manual really duplicate the RISC-V manuals? I would only 
describe the command line options and add a links to the relevant RISC-V 
manuals.

>

> Additionally, we've been collecting all the standard interfaces in 

> RISC-V specific manuals.  Do you mind adding a bit here about lla (and 

> then modifying the la bit to include that it can take constants)

>

> https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md

>

> I also left a comment in the middle of the source about "lla 

> 0xFFFFFFFF" on RV64I, which I think should be supported.

>

> Thanks for the patch, and sorry for making so much more work :)


My original plan was to add this lla documentation to:

https://github.com/riscv/riscv-isa-manual

Why do you have two places for assembler documentation?

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
Palmer Dabbelt June 22, 2018, 4:54 p.m. | #5
On Thu, 21 Jun 2018 21:17:09 PDT (-0700), sebastian.huber@embedded-brains.de wrote:
> On 21/06/18 18:06, Palmer Dabbelt wrote:

>>

>>> I try to add a documentation of "lla". See also:

>>>

>>> https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/sDQWmHyzHi8 

>>>

>>

>> Thanks.  I suppose this should be documented in the GAS manual, though 

>> we don't have any of the pseudos in there.  Do you mind adding a 

>> section to

>>

>>    gas/doc/c-riscv.texi

>>

>> for pseduo ops that contains lla?  We can add the rest later...

>

> Should the GAS manual really duplicate the RISC-V manuals? I would only 

> describe the command line options and add a links to the relevant RISC-V 

> manuals.


I'm OK with that.

>> Additionally, we've been collecting all the standard interfaces in 

>> RISC-V specific manuals.  Do you mind adding a bit here about lla (and 

>> then modifying the la bit to include that it can take constants)

>>

>> https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md

>>

>> I also left a comment in the middle of the source about "lla 

>> 0xFFFFFFFF" on RV64I, which I think should be supported.

>>

>> Thanks for the patch, and sorry for making so much more work :)

>

> My original plan was to add this lla documentation to:

>

> https://github.com/riscv/riscv-isa-manual

>

> Why do you have two places for assembler documentation?


We're trying to separate the ISA constructs from toolchain constructs.  It's 
the same reason we keep the ABI document separate from the ISA manual.  I guess 
at this point it's really a RISC-V thing more than a binutils thing, so feel 
free to open teh PR you were planning on and then we can talk about it in 
RISC-V land.

Thanks!
Andrew Waterman June 22, 2018, 10:49 p.m. | #6
On Thu, Jun 21, 2018 at 9:17 PM, Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
> On 21/06/18 18:06, Palmer Dabbelt wrote:

>>

>>

>>> I try to add a documentation of "lla". See also:

>>>

>>>

>>> https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/sDQWmHyzHi8

>>

>>

>> Thanks.  I suppose this should be documented in the GAS manual, though we

>> don't have any of the pseudos in there.  Do you mind adding a section to

>>

>>    gas/doc/c-riscv.texi

>>

>> for pseduo ops that contains lla?  We can add the rest later...

>

>

> Should the GAS manual really duplicate the RISC-V manuals? I would only

> describe the command line options and add a links to the relevant RISC-V

> manuals.

>

>>

>> Additionally, we've been collecting all the standard interfaces in RISC-V

>> specific manuals.  Do you mind adding a bit here about lla (and then

>> modifying the la bit to include that it can take constants)

>>

>> https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md

>>

>> I also left a comment in the middle of the source about "lla 0xFFFFFFFF"

>> on RV64I, which I think should be supported.

>>

>> Thanks for the patch, and sorry for making so much more work :)

>

>

> My original plan was to add this lla documentation to:

>

> https://github.com/riscv/riscv-isa-manual

>

> Why do you have two places for assembler documentation?


We are removing the assembly-programming section of the ISA manual to
separate it into its own separate assembly programming manual, located
here: https://github.com/riscv/riscv-asm-manual/ -- please contribute
the documentation there.

>

>

> --

> Sebastian Huber, embedded brains GmbH

>

> Address : Dornierstr. 4, D-82178 Puchheim, Germany

> Phone   : +49 89 189 47 41-16

> Fax     : +49 89 189 47 41-09

> E-Mail  : sebastian.huber@embedded-brains.de

> PGP     : Public key available on request.

>

> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

>

Patch

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 332a063d55..33ba540ed2 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,16 @@ 
+2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
+
+	PR gas/23305
+	* config/tc-riscv.c (riscv_ip): Add format specifier 'B' for
+	constants and symbols.
+	* testsuite/gas/riscv/lla32.d: New file.
+	* testsuite/gas/riscv/lla32.s: Likewise.
+	* testsuite/gas/riscv/lla64-fail.d: Likewise.
+	* testsuite/gas/riscv/lla64-fail.l: Likewise.
+	* testsuite/gas/riscv/lla64-fail.s: Likewise.
+	* testsuite/gas/riscv/lla64.d: Likewise.
+	* testsuite/gas/riscv/lla64.s: Likewise.
+
 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 
 	* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a0ea87a3fa..bdec30741b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1935,6 +1935,17 @@  rvc_lui:
 	      s = expr_end;
 	      continue;
 
+	    case 'B':
+	      my_getExpression (imm_expr, s);
+	      normalize_constant_expr (imm_expr);
+	      /* The 'B' format specifier must be a symbol or a constant.  */
+	      if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
+	        break;
+	      if (imm_expr->X_op == O_symbol)
+	        *imm_reloc = BFD_RELOC_32;
+	      s = expr_end;
+	      continue;
+
 	    case 'j': /* Sign-extended immediate.  */
 	      *imm_reloc = BFD_RELOC_RISCV_LO12_I;
 	      p = percent_op_itype;
diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d
new file mode 100644
index 0000000000..ab766b4e3b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -0,0 +1,19 @@ 
+#as: -march=rv32i -mabi=ilp32
+#objdump: -dr
+
+.*:     file format elf32-littleriscv
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+   0:	00100513          	li	a0,1
+   4:	00001537          	lui	a0,0x1
+   8:	00001537          	lui	a0,0x1
+   c:	00150513          	addi	a0,a0,1 # 1001 <c>
+  10:	00001537          	lui	a0,0x1
+  14:	fff50513          	addi	a0,a0,-1 # fff <d>
+  18:	80000537          	lui	a0,0x80000
+  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <h\+0x80000000>
+  20:	00000513          	li	a0,0
+  24:	fff00513          	li	a0,-1
diff --git a/gas/testsuite/gas/riscv/lla32.s b/gas/testsuite/gas/riscv/lla32.s
new file mode 100644
index 0000000000..8d5773e929
--- /dev/null
+++ b/gas/testsuite/gas/riscv/lla32.s
@@ -0,0 +1,15 @@ 
+.set a, 0x1
+.set b, 0x1000
+.set c, 0x1001
+.set d, 0xfff
+.set e, 0x7fffffff
+.set g, 0x0
+.set h, 0xffffffff
+.text
+	lla a0, a
+	lla a0, b
+	lla a0, c
+	lla a0, d
+	lla a0, e
+	lla a0, g
+	lla a0, h
diff --git a/gas/testsuite/gas/riscv/lla64-fail.d b/gas/testsuite/gas/riscv/lla64-fail.d
new file mode 100644
index 0000000000..97b2e105c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/lla64-fail.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv64i -mabi=lp64
+#source: lla64-fail.s
+#error-output: lla64-fail.l
diff --git a/gas/testsuite/gas/riscv/lla64-fail.l b/gas/testsuite/gas/riscv/lla64-fail.l
new file mode 100644
index 0000000000..088f18e530
--- /dev/null
+++ b/gas/testsuite/gas/riscv/lla64-fail.l
@@ -0,0 +1,2 @@ 
+.*: Assembler messages:
+.*: Error: offset too large
diff --git a/gas/testsuite/gas/riscv/lla64-fail.s b/gas/testsuite/gas/riscv/lla64-fail.s
new file mode 100644
index 0000000000..e8379bfbe8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/lla64-fail.s
@@ -0,0 +1,3 @@ 
+.set a, 0xffffffff
+.text
+	lla a0, a
diff --git a/gas/testsuite/gas/riscv/lla64.d b/gas/testsuite/gas/riscv/lla64.d
new file mode 100644
index 0000000000..7848eecdfb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/lla64.d
@@ -0,0 +1,20 @@ 
+#as: -march=rv64i -mabi=lp64
+#objdump: -dr
+
+.*:     file format elf64-littleriscv
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+   0:	0010051b          	addiw	a0,zero,1
+   4:	00001537          	lui	a0,0x1
+   8:	00001537          	lui	a0,0x1
+   c:	0015051b          	addiw	a0,a0,1
+  10:	00001537          	lui	a0,0x1
+  14:	fff5051b          	addiw	a0,a0,-1
+  18:	80000537          	lui	a0,0x80000
+  1c:	fff5051b          	addiw	a0,a0,-1
+  20:	0000051b          	sext.w	a0,zero
+  24:	fff0051b          	addiw	a0,zero,-1
+  28:	80000537          	lui	a0,0x80000
diff --git a/gas/testsuite/gas/riscv/lla64.s b/gas/testsuite/gas/riscv/lla64.s
new file mode 100644
index 0000000000..4be5082451
--- /dev/null
+++ b/gas/testsuite/gas/riscv/lla64.s
@@ -0,0 +1,17 @@ 
+.set a, 0x1
+.set b, 0x1000
+.set c, 0x1001
+.set d, 0xfff
+.set e, 0x7fffffff
+.set g, 0x0
+.set h, 0xffffffffffffffff
+.set i, 0xffffffff80000000
+.text
+	lla a0, a
+	lla a0, b
+	lla a0, c
+	lla a0, d
+	lla a0, e
+	lla a0, g
+	lla a0, h
+	lla a0, i
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0cfb8065ee..c5ef6a367e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@ 
+2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
+
+	PR gas/23305
+	* riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
+	la and lla.
+
 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 
 	* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 47e9659c97..8e55916451 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -278,8 +278,8 @@  const struct riscv_opcode riscv_opcodes[] =
    applied to an add instruction, for relaxation to use.  */
 {"add",       "I",   "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },
 {"add",       "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
-{"la",        "I",   "d,A",  0,    (int) M_LA,  match_never, INSN_MACRO },
-{"lla",       "I",   "d,A",  0,    (int) M_LLA,  match_never, INSN_MACRO },
+{"la",        "I",   "d,B",  0,    (int) M_LA,  match_never, INSN_MACRO },
+{"lla",       "I",   "d,B",  0,    (int) M_LLA,  match_never, INSN_MACRO },
 {"la.tls.gd", "I",   "d,A",  0,    (int) M_LA_TLS_GD,  match_never, INSN_MACRO },
 {"la.tls.ie", "I",   "d,A",  0,    (int) M_LA_TLS_IE,  match_never, INSN_MACRO },
 {"neg",       "I",   "d,t",  MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */