x86/Intel: accept "oword ptr" for INVPCID

Message ID 5B0E559D02000078001C6D86@prv1-mh.provo.novell.com
State New
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Series
  • x86/Intel: accept "oword ptr" for INVPCID
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Commit Message

Jan Beulich May 30, 2018, 7:41 a.m.
The insn is no different in this reagrd from INVEPT and INVVPID.

gas/
2018-05-30  Jan Beulich  <jbeulich@suse.com>

	*  testsuite/gas/i386/invpcid.s,
	testsuite/gas/i386/x86-64-invpcid.s: Add test with explicit
	"oword ptr".
	* testsuite/gas/i386/invpcid.d,
	testsuite/gas/i386/invpcid-intel.d,
	testsuite/gas/i386/x86-64-invpcid.d,
	testsuite/gas/i386/x86-64-invpcid-intel.d: Adjust expectations.

opcodes/
2018-05-30  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (invpcid): Add Oword.
	* i386-tbl.h: Re-generate.

Comments

H.J. Lu May 30, 2018, 12:40 p.m. | #1
On Wed, May 30, 2018 at 12:41 AM, Jan Beulich <JBeulich@suse.com> wrote:
> The insn is no different in this reagrd from INVEPT and INVVPID.

>

> gas/

> 2018-05-30  Jan Beulich  <jbeulich@suse.com>

>

>         *  testsuite/gas/i386/invpcid.s,

>         testsuite/gas/i386/x86-64-invpcid.s: Add test with explicit

>         "oword ptr".

>         * testsuite/gas/i386/invpcid.d,

>         testsuite/gas/i386/invpcid-intel.d,

>         testsuite/gas/i386/x86-64-invpcid.d,

>         testsuite/gas/i386/x86-64-invpcid-intel.d: Adjust expectations.

>

> opcodes/

> 2018-05-30  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-opc.tbl (invpcid): Add Oword.

>         * i386-tbl.h: Re-generate.

>


OK.

Thanks.

-- 
H.J.

Patch

--- a/gas/testsuite/gas/i386/invpcid-intel.d
+++ b/gas/testsuite/gas/i386/invpcid-intel.d
@@ -11,4 +11,5 @@  Disassembly of section .text:
 0+ <foo>:
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid edx,\[eax\]
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid edx,\[eax\]
+[ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid edx,\[eax\]
 #pass
--- a/gas/testsuite/gas/i386/invpcid.d
+++ b/gas/testsuite/gas/i386/invpcid.d
@@ -10,4 +10,5 @@  Disassembly of section .text:
 0+ <foo>:
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%eax\),%edx
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%eax\),%edx
+[ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%eax\),%edx
 #pass
--- a/gas/testsuite/gas/i386/invpcid.s
+++ b/gas/testsuite/gas/i386/invpcid.s
@@ -6,3 +6,4 @@  foo:
 
 	.intel_syntax noprefix
 	invpcid	edx,[eax]
+	invpcid	edx,oword ptr [eax]
--- a/gas/testsuite/gas/i386/x86-64-invpcid-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-invpcid-intel.d
@@ -11,4 +11,5 @@  Disassembly of section .text:
 0+ <foo>:
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid rdx,\[rax\]
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid rdx,\[rax\]
+[ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid rdx,\[rax\]
 #pass
--- a/gas/testsuite/gas/i386/x86-64-invpcid.d
+++ b/gas/testsuite/gas/i386/x86-64-invpcid.d
@@ -10,4 +10,5 @@  Disassembly of section .text:
 0+ <foo>:
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%rax\),%rdx
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%rax\),%rdx
 #pass
--- a/gas/testsuite/gas/i386/x86-64-invpcid.s
+++ b/gas/testsuite/gas/i386/x86-64-invpcid.s
@@ -6,3 +6,4 @@  foo:
 
 	.intel_syntax noprefix
 	invpcid	rdx,[rax]
+	invpcid	rdx,oword ptr [rax]
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1583,8 +1583,8 @@  invvpid, 2, 0x660f3881, None, 3, CpuEPT|
 
 // INVPCID instruction
 
-invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex, Reg32 }
-invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Unspecified|BaseIndex, Reg64 }
+invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
+invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
 
 // SSSE3 instructions.