[4/5] x86: FMA4 scalar insns ignore VEX.L

Message ID 950a16e2-8e6d-f267-4d25-b85443eb7f0f@suse.com
State New
Headers show
Series
  • x86: XOP disassembler corrections and improvements
Related show

Commit Message

Jan Beulich July 7, 2020, 4:15 p.m.
Just like other VEX-encoded scalar insns do.

Besides a testcase for this behavior also introduce one to verify that
XOP scalar insns don't honor -mavxscalar=256, as they don't ignore
XOP.L.

gas/
2020-07-XX  Jan Beulich  <jbeulich@suse.com>

	* testsuite/gas/i386/fma4-lig.d, testsuite/gas/i386/xop-lig.d:
	New.
	* testsuite/gas/i386/i386.exp: Run new tests.

opcodes/
2020-07-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (XMVexScalarI4): Define.
	(VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
	VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
	VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
	(vex_len_table): Move scalar FMA4 entries ...
	(prefix_table): ... here.
	(OP_REG_VexI4): Handle scalar_mode.
	* i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
	* i386-tbl.h: Re-generate.

Patch

--- /dev/null
+++ b/gas/testsuite/gas/i386/fma4-lig.d
@@ -0,0 +1,97 @@ 
+#as: -mavxscalar=256
+#objdump: -dw
+#name: i386 FMA4 w/ -mavxscalar=256
+#source: fma4.s
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 e3 ed 69 fc 60    	vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 69 39 60    	vfmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 68 fc 60    	vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 68 39 60    	vfmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 59 68 6c da 01 30 	vfmaddps %xmm3,0x1\(%edx,%ebx,8\),%xmm4,%xmm5
+[ 	]*[a-f0-9]+:	c4 e3 49 68 8c 81 80 00 00 00 70 	vfmaddps %xmm7,0x80\(%ecx,%eax,4\),%xmm6,%xmm1
+[ 	]*[a-f0-9]+:	c4 e3 ed 5d fc 60    	vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 5d 39 60    	vfmaddsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 5c fc 60    	vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 5c 39 60    	vfmaddsubps \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 5f fc 60    	vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 5f 39 60    	vfmsubaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 5e fc 60    	vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 5e 39 60    	vfmsubaddps \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6d fc 60    	vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6d 39 60    	vfmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6c fc 60    	vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6c 39 60    	vfmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 69 fc 60    	vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 69 39 60    	vfmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 69 39 40    	vfmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 68 fc 60    	vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 68 39 60    	vfmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 68 39 40    	vfmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 5d fc 60    	vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 5d 39 60    	vfmaddsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 5d 39 40    	vfmaddsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 5c fc 60    	vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 5c 39 60    	vfmaddsubps \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 5c 39 40    	vfmaddsubps %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 5f fc 60    	vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 5f 39 60    	vfmsubaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 5f 39 40    	vfmsubaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 5e fc 60    	vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 5e 39 60    	vfmsubaddps \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 5e 39 40    	vfmsubaddps %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 6d fc 60    	vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 6d 39 60    	vfmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 6d 39 40    	vfmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 6c fc 60    	vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 6c 39 60    	vfmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 6c 39 40    	vfmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6b fc 60    	vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6b 39 60    	vfmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 6b 39 40    	vfmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6f fc 60    	vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6f 39 60    	vfmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 6f 39 40    	vfmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6a fc 60    	vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6a 39 60    	vfmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 6a 39 40    	vfmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6e fc 60    	vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 6e 39 60    	vfmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 6e 39 40    	vfmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 79 fc 60    	vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 79 39 60    	vfnmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 78 fc 60    	vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 78 39 60    	vfnmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7d fc 60    	vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7d 39 60    	vfnmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7c fc 60    	vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7c 39 60    	vfnmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 79 fc 60    	vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 79 39 60    	vfnmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 79 39 40    	vfnmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 78 fc 60    	vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 78 39 60    	vfnmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 78 39 40    	vfnmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 7d fc 60    	vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 7d 39 60    	vfnmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 7d 39 40    	vfnmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 7c fc 60    	vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 7c 39 60    	vfnmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 69 7c 39 40    	vfnmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7b fc 60    	vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7b 39 60    	vfnmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 7b 39 40    	vfnmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7f fc 60    	vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7f 39 60    	vfnmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 7f 39 40    	vfnmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7a fc 60    	vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7a 39 60    	vfnmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 7a 39 40    	vfnmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7e fc 60    	vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 ed 7e 39 60    	vfnmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 7e 39 40    	vfnmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
+#pass
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -302,9 +302,11 @@  if [expr ([istarget "i*86-*-*"] ||  [ist
     run_dump_test "rtm"
     run_dump_test "rtm-intel"
     run_dump_test "fma4"
+    run_dump_test "fma4-lig"
     run_dump_test "lwp"
     run_dump_test "lwp-16bit"
     run_dump_test "xop"
+    run_dump_test "xop-lig"
     run_dump_test "xop32reg"
     run_dump_test "bmi"
     run_dump_test "bmi-intel"
--- /dev/null
+++ b/gas/testsuite/gas/i386/xop-lig.d
@@ -0,0 +1,5 @@ 
+#as: -mavxscalar=256
+#objdump: -dw
+#name: i386 XOP w/ -mavxscalar=256
+#source: xop.s
+#dump: xop.d
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -421,6 +421,7 @@  fetch_data (struct disassemble_info *inf
 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 #define XMVexI4 { OP_REG_VexI4, x_mode }
+#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 #define VexI4 { OP_VexI4, 0 }
 #define PCLMUL { PCLMUL_Fixup, 0 }
 #define VCMP { VCMP_Fixup, 0 }
@@ -1788,14 +1789,6 @@  enum
   VEX_LEN_0F3A61_P_2,
   VEX_LEN_0F3A62_P_2,
   VEX_LEN_0F3A63_P_2,
-  VEX_LEN_0F3A6A_P_2,
-  VEX_LEN_0F3A6B_P_2,
-  VEX_LEN_0F3A6E_P_2,
-  VEX_LEN_0F3A6F_P_2,
-  VEX_LEN_0F3A7A_P_2,
-  VEX_LEN_0F3A7B_P_2,
-  VEX_LEN_0F3A7E_P_2,
-  VEX_LEN_0F3A7F_P_2,
   VEX_LEN_0F3ADF_P_2,
   VEX_LEN_0F3AF0_P_3,
   VEX_LEN_0FXOP_08_CC,
@@ -6512,14 +6505,14 @@  static const struct dis386 prefix_table[
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
+    { "vfmaddss",	{ XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
   },
 
   /* PREFIX_VEX_0F3A6B */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
+    { "vfmaddsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
   },
 
   /* PREFIX_VEX_0F3A6C */
@@ -6540,14 +6533,14 @@  static const struct dis386 prefix_table[
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
+    { "vfmsubss",	{ XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
   },
 
   /* PREFIX_VEX_0F3A6F */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
+    { "vfmsubsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
   },
 
   /* PREFIX_VEX_0F3A78 */
@@ -6568,14 +6561,14 @@  static const struct dis386 prefix_table[
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
+    { "vfnmaddss",	{ XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
   },
 
   /* PREFIX_VEX_0F3A7B */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
+    { "vfnmaddsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
   },
 
   /* PREFIX_VEX_0F3A7C */
@@ -6597,14 +6590,14 @@  static const struct dis386 prefix_table[
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
+    { "vfnmsubss",	{ XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
   },
 
   /* PREFIX_VEX_0F3A7F */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
+    { "vfnmsubsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
   },
 
   /* PREFIX_VEX_0F3ACE */
@@ -9620,46 +9613,6 @@  static const struct dis386 vex_len_table
     { "vpcmpistri",	{ XM, EXx, Ib }, 0 },
   },
 
-  /* VEX_LEN_0F3A6A_P_2 */
-  {
-    { "vfmaddss",	{ XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
-  },
-
-  /* VEX_LEN_0F3A6B_P_2 */
-  {
-    { "vfmaddsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
-  },
-
-  /* VEX_LEN_0F3A6E_P_2 */
-  {
-    { "vfmsubss",	{ XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
-  },
-
-  /* VEX_LEN_0F3A6F_P_2 */
-  {
-    { "vfmsubsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
-  },
-
-  /* VEX_LEN_0F3A7A_P_2 */
-  {
-    { "vfnmaddss",	{ XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
-  },
-
-  /* VEX_LEN_0F3A7B_P_2 */
-  {
-    { "vfnmaddsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
-  },
-
-  /* VEX_LEN_0F3A7E_P_2 */
-  {
-    { "vfnmsubss",	{ XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
-  },
-
-  /* VEX_LEN_0F3A7F_P_2 */
-  {
-    { "vfnmsubsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
-  },
-
   /* VEX_LEN_0F3ADF_P_2 */
   {
     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
@@ -15865,29 +15818,21 @@  static void
 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
 {
   int reg;
-  const char **names;
+  const char **names = names_xmm;
 
   FETCH_DATA (the_info, codep + 1);
   reg = *codep++;
 
-  if (bytemode != x_mode)
+  if (bytemode != x_mode && bytemode != scalar_mode)
     abort ();
 
   reg >>= 4;
   if (address_mode != mode_64bit)
     reg &= 7;
 
-  switch (vex.length)
-    {
-    case 128:
-      names = names_xmm;
-      break;
-    case 256:
-      names = names_ymm;
-      break;
-    default:
-      abort ();
-    }
+  if (bytemode == x_mode && vex.length == 256)
+    names = names_ymm;
+
   oappend (names[reg]);
 
   if (vex.w)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2331,10 +2331,10 @@  vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, M
 vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@@ -2347,26 +2347,26 @@  vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, M
 vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|VexLIG|VexOpcode=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 
 // XOP instructions