[committed] arc: update error messages when assembly and update vector instructions

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  • [committed] arc: update error messages when assembly and update vector instructions
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Commit Message

Alan Modra via Binutils July 7, 2020, 1:13 p.m.
Two committed small patches which improves the error messages thrown by the assembler, and an update vector instructions.

Cheers,
Claudiu

Patch

From f337259fbd5ee31c6794158457dcd0d23e5c0f13 Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu <claziss@gmail.com>
Date: Tue, 7 Jul 2020 16:01:48 +0300
Subject: [PATCH 1/2] arc: Update vector instructions.

Update vadd2, vadd4h, vmac2h, vmpy2h, vsub4h vector instructions
arguments to discriminate between double/single register operands.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (insert_rbd): New function.
	(RBD): Define.
	(RBDdup): Likewise.
	* arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
	instructions.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
---
 gas/testsuite/gas/arc/dsp.d |   4 +-
 opcodes/ChangeLog           |   8 ++
 opcodes/arc-opc.c           |  22 +++++-
 opcodes/arc-tbl.h           | 150 ++++++++++++++++++------------------
 4 files changed, 105 insertions(+), 79 deletions(-)

diff --git a/gas/testsuite/gas/arc/dsp.d b/gas/testsuite/gas/arc/dsp.d
index 22961aee9d..d5f9744ae6 100644
--- a/gas/testsuite/gas/arc/dsp.d
+++ b/gas/testsuite/gas/arc/dsp.d
@@ -70,13 +70,13 @@  Disassembly of section .text:
 0x[0-9a-f]+ 282f 00a4           	vext2bhl	r0,r2
 0x[0-9a-f]+ 282f 00a5           	vext2bhm	r0,r2
 0x[0-9a-f]+ 2a23 0100           	vlsr2h	r0,r2,r4
-0x[0-9a-f]+ 2a1e 0100           	vmac2h	r0,r2,r4
+0x[0-9a-f]+ 2a1e 0100           	vmac2h	r0r1,r2,r4
 0x[0-9a-f]+ 2a1e 8100           	vmac2hf	r0,r2,r4
 0x[0-9a-f]+ 2a1f 8100           	vmac2hfr	r0,r2,r4
 0x[0-9a-f]+ 2a1f 0100           	vmac2hu	r0,r2,r4
 0x[0-9a-f]+ 2a24 8100           	vmax2h	r0,r2,r4
 0x[0-9a-f]+ 2a25 8100           	vmin2h	r0,r2,r4
-0x[0-9a-f]+ 2a1c 0100           	vmpy2h	r0,r2,r4
+0x[0-9a-f]+ 2a1c 0100           	vmpy2h	r0r1,r2,r4
 0x[0-9a-f]+ 2a1c 8100           	vmpy2hf	r0,r2,r4
 0x[0-9a-f]+ 2a1d 8100           	vmpy2hfr	r0,r2,r4
 0x[0-9a-f]+ 2a1d 0100           	vmpy2hu	r0,r2,r4
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 32bc8e786a..07f2594661 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@ 
+2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* arc-opc.c (insert_rbd): New function.
+	(RBD): Define.
+	(RBDdup): Likewise.
+	* arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
+	instructions.
+
 2020-07-07  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 675738aa6b..94adde4783 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -103,6 +103,19 @@  insert_rcd (unsigned long long  insn,
   return insn | ((value & 0x3F) << 6);
 }
 
+static unsigned long long
+insert_rbd (unsigned long long  insn,
+	    long long           value,
+	    const char **       errmsg)
+{
+  if (value & 0x01)
+    *errmsg = _("cannot use odd number source register");
+  if (value == 60)
+    *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+  return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
 /* Dummy insert ZERO operand function.  */
 
 static unsigned long long
@@ -1826,11 +1839,16 @@  const struct arc_operand arc_operands[] =
   { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
 #define RCD		(RAD_CHK + 1)
   { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
+#define RBD		(RCD + 1)
+  { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb },
+#define RBDdup		(RBD + 1)
+  { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE,
+    insert_rbd, extract_rb },
 
   /* The plain integer register fields.  Used by short
      instructions.  */
-#define RA16		(RCD + 1)
-#define RA_S		(RCD + 1)
+#define RA16		(RBDdup + 1)
+#define RA_S		(RBDdup + 1)
   { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
 #define RB16		(RA16 + 1)
 #define RB_S		(RA16 + 1)
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 10625f1b36..d00110fa8a 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -17131,46 +17131,46 @@ 
 { "vabss2h", 0x2E2F7FA9, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM }, { 0 }},
 
 /* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA.  */
-{ "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+{ "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, RCD }, { 0 }},
 
 /* vadd2 0,b,c 00101bbb001111000BBBCCCCCC111110.  */
-{ "vadd2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+{ "vadd2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, RCD }, { 0 }},
 
 /* vadd2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ.  */
-{ "vadd2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+{ "vadd2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, RC }, { C_CC }},
 
 /* vadd2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA.  */
-{ "vadd2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+{ "vadd2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, UIMM6_20 }, { 0 }},
 
 /* vadd2 0,b,u6 00101bbb011111000BBBuuuuuu111110.  */
-{ "vadd2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+{ "vadd2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, UIMM6_20 }, { 0 }},
 
 /* vadd2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ.  */
-{ "vadd2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+{ "vadd2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, UIMM6_20 }, { C_CC }},
 
 /* vadd2 b,b,s12 00101bbb101111000BBBssssssSSSSSS.  */
-{ "vadd2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+{ "vadd2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, SIMM12_20 }, { 0 }},
 
 /* vadd2 a,limm,c 00101110001111000111CCCCCCAAAAAA.  */
-{ "vadd2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+{ "vadd2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, RCD }, { 0 }},
 
 /* vadd2 a,b,limm 00101bbb001111000BBB111110AAAAAA.  */
-{ "vadd2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+{ "vadd2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, LIMM }, { 0 }},
 
 /* vadd2 0,limm,c 00101110001111000111CCCCCC111110.  */
-{ "vadd2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+{ "vadd2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RCD }, { 0 }},
 
 /* vadd2 0,b,limm 00101bbb001111000BBB111110111110.  */
-{ "vadd2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+{ "vadd2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, LIMM }, { 0 }},
 
 /* vadd2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ.  */
-{ "vadd2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+{ "vadd2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, LIMM }, { C_CC }},
 
 /* vadd2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ.  */
-{ "vadd2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+{ "vadd2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RCD }, { C_CC }},
 
 /* vadd2 a,limm,u6 00101110011111000111uuuuuuAAAAAA.  */
-{ "vadd2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+{ "vadd2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, UIMM6_20 }, { 0 }},
 
 /* vadd2 0,limm,u6 00101110011111000111uuuuuu111110.  */
 { "vadd2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -17182,7 +17182,7 @@ 
 { "vadd2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
 
 /* vadd2 a,limm,limm 00101110001111000111111110AAAAAA.  */
-{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, LIMMdup }, { 0 }},
 
 /* vadd2 0,limm,limm 00101110001111000111111110111110.  */
 { "vadd2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -17311,46 +17311,46 @@ 
 { "vadd4b", 0x2EE47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
 
 /* vadd4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA.  */
-{ "vadd4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+{ "vadd4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, RCD }, { 0 }},
 
 /* vadd4h 0,b,c 00101bbb001110000BBBCCCCCC111110.  */
-{ "vadd4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+{ "vadd4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, RCD }, { 0 }},
 
 /* vadd4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ.  */
-{ "vadd4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+{ "vadd4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, RCD }, { C_CC }},
 
 /* vadd4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA.  */
-{ "vadd4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+{ "vadd4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, UIMM6_20 }, { 0 }},
 
 /* vadd4h 0,b,u6 00101bbb011110000BBBuuuuuu111110.  */
-{ "vadd4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+{ "vadd4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, UIMM6_20 }, { 0 }},
 
 /* vadd4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ.  */
-{ "vadd4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+{ "vadd4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, UIMM6_20 }, { C_CC }},
 
 /* vadd4h b,b,s12 00101bbb101110000BBBssssssSSSSSS.  */
-{ "vadd4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+{ "vadd4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, SIMM12_20 }, { 0 }},
 
 /* vadd4h a,limm,c 00101110001110000111CCCCCCAAAAAA.  */
-{ "vadd4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+{ "vadd4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, RCD }, { 0 }},
 
 /* vadd4h a,b,limm 00101bbb001110000BBB111110AAAAAA.  */
-{ "vadd4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+{ "vadd4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, LIMM }, { 0 }},
 
 /* vadd4h 0,limm,c 00101110001110000111CCCCCC111110.  */
-{ "vadd4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+{ "vadd4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RCD }, { 0 }},
 
 /* vadd4h 0,b,limm 00101bbb001110000BBB111110111110.  */
-{ "vadd4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+{ "vadd4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, LIMM }, { 0 }},
 
 /* vadd4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ.  */
-{ "vadd4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+{ "vadd4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, LIMM }, { C_CC }},
 
 /* vadd4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ.  */
-{ "vadd4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+{ "vadd4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RCD }, { C_CC }},
 
 /* vadd4h a,limm,u6 00101110011110000111uuuuuuAAAAAA.  */
-{ "vadd4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+{ "vadd4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, UIMM6_20 }, { 0 }},
 
 /* vadd4h 0,limm,u6 00101110011110000111uuuuuu111110.  */
 { "vadd4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -17362,7 +17362,7 @@ 
 { "vadd4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
 
 /* vadd4h a,limm,limm 00101110001110000111111110AAAAAA.  */
-{ "vadd4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+{ "vadd4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, LIMMdup }, { 0 }},
 
 /* vadd4h 0,limm,limm 00101110001110000111111110111110.  */
 { "vadd4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -18421,31 +18421,31 @@ 
 { "vlsr2h", 0x2EE37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
 
 /* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA.  */
-{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, RB, RC }, { 0 }},
 
 /* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110.  */
 { "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, RC }, { 0 }},
 
 /* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ.  */
-{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RBD, RBdup, RC }, { C_CC }},
 
 /* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA.  */
-{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, RB, UIMM6_20 }, { 0 }},
 
 /* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110.  */
 { "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
 
 /* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ.  */
-{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RBD, RBdup, UIMM6_20 }, { C_CC }},
 
 /* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS.  */
-{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RBD, RBdup, SIMM12_20 }, { 0 }},
 
 /* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA.  */
-{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, LIMM, RC }, { 0 }},
 
 /* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA.  */
-{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, RB, LIMM }, { 0 }},
 
 /* vmac2h 0,limm,c 00101110000111100111CCCCCC111110.  */
 { "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -18454,13 +18454,13 @@ 
 { "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
 
 /* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ.  */
-{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RBD, RBdup, LIMM }, { C_CC }},
 
 /* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ.  */
 { "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
 
 /* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA.  */
-{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, LIMM, UIMM6_20 }, { 0 }},
 
 /* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110.  */
 { "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -18472,7 +18472,7 @@ 
 { "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
 
 /* vmac2h a,limm,limm 00101110000111100111111110AAAAAA.  */
-{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, LIMM, LIMMdup }, { 0 }},
 
 /* vmac2h 0,limm,limm 00101110000111100111111110111110.  */
 { "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -18841,52 +18841,52 @@ 
 { "vmin2h", 0x2EE5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
 
 /* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA.  */
-{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, RB, RC }, { 0 }},
 
 /* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110.  */
 { "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, RC }, { 0 }},
 
 /* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ.  */
-{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RBD, RBdup, RC }, { C_CC }},
 
 /* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA.  */
-{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RA_CHK, RB, RC }, { 0 }},
+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RAD, RB, RC }, { 0 }},
 
 /* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110.  */
 { "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { ZA, RB, RC }, { 0 }},
 
 /* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ.  */
-{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_CC }},
+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RBD, RBdup, RC }, { C_CC }},
 
 /* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA.  */
-{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, RB, UIMM6_20 }, { 0 }},
 
 /* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110.  */
 { "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
 
 /* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ.  */
-{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RBD, RBdup, UIMM6_20 }, { C_CC }},
 
 /* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA.  */
-{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RAD, RB, UIMM6_20 }, { 0 }},
 
 /* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110.  */
 { "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }},
 
 /* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ.  */
-{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RBD, RBdup, UIMM6_20 }, { C_CC }},
 
 /* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS.  */
-{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RBD, RBdup, SIMM12_20 }, { 0 }},
 
 /* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS.  */
-{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RBD, RBdup, SIMM12_20 }, { 0 }},
 
 /* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA.  */
-{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, LIMM, RC }, { 0 }},
 
 /* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA.  */
-{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, RB, LIMM }, { 0 }},
 
 /* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110.  */
 { "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -18895,16 +18895,16 @@ 
 { "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
 
 /* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ.  */
-{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RBD, RBdup, LIMM }, { C_CC }},
 
 /* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ.  */
 { "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
 
 /* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA.  */
-{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RA_CHK, LIMM, RC }, { 0 }},
+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RAD, LIMM, RC }, { 0 }},
 
 /* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA.  */
-{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RA_CHK, RB, LIMM }, { 0 }},
+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RAD, RB, LIMM }, { 0 }},
 
 /* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110.  */
 { "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { ZA, LIMM, RC }, { 0 }},
@@ -18913,13 +18913,13 @@ 
 { "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { ZA, RB, LIMM }, { 0 }},
 
 /* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ.  */
-{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RBD, RBdup, LIMM }, { C_CC }},
 
 /* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ.  */
 { "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { ZA, LIMM, RC }, { C_CC }},
 
 /* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA.  */
-{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, LIMM, UIMM6_20 }, { 0 }},
 
 /* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110.  */
 { "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -18928,7 +18928,7 @@ 
 { "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
 
 /* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA.  */
-{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RAD, LIMM, UIMM6_20 }, { 0 }},
 
 /* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110.  */
 { "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -18943,7 +18943,7 @@ 
 { "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }},
 
 /* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA.  */
-{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RAD, LIMM, LIMMdup }, { 0 }},
 
 /* vmpy2h 0,limm,limm 00101110000111000111111110111110.  */
 { "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -18952,7 +18952,7 @@ 
 { "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
 
 /* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA.  */
-{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { RAD, LIMM, LIMMdup }, { 0 }},
 
 /* vmpy2h 0,limm,limm 00101110000111000111111110111110.  */
 { "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -19999,46 +19999,46 @@ 
 { "vsub4b", 0x2EE57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
 
 /* vsub4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA.  */
-{ "vsub4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+{ "vsub4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, RCD }, { 0 }},
 
 /* vsub4h 0,b,c 00101bbb001110010BBBCCCCCC111110.  */
-{ "vsub4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+{ "vsub4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, RCD }, { 0 }},
 
 /* vsub4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ.  */
-{ "vsub4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+{ "vsub4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, RCD }, { C_CC }},
 
 /* vsub4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA.  */
-{ "vsub4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+{ "vsub4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, UIMM6_20 }, { 0 }},
 
 /* vsub4h 0,b,u6 00101bbb011110010BBBuuuuuu111110.  */
-{ "vsub4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+{ "vsub4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, UIMM6_20 }, { 0 }},
 
 /* vsub4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ.  */
-{ "vsub4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+{ "vsub4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, UIMM6_20 }, { C_CC }},
 
 /* vsub4h b,b,s12 00101bbb101110010BBBssssssSSSSSS.  */
-{ "vsub4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+{ "vsub4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, SIMM12_20 }, { 0 }},
 
 /* vsub4h a,limm,c 00101110001110010111CCCCCCAAAAAA.  */
-{ "vsub4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+{ "vsub4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, RCD }, { 0 }},
 
 /* vsub4h a,b,limm 00101bbb001110010BBB111110AAAAAA.  */
-{ "vsub4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+{ "vsub4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, RBD, LIMM }, { 0 }},
 
 /* vsub4h 0,limm,c 00101110001110010111CCCCCC111110.  */
-{ "vsub4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+{ "vsub4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RCD }, { 0 }},
 
 /* vsub4h 0,b,limm 00101bbb001110010BBB111110111110.  */
-{ "vsub4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+{ "vsub4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, RBD, LIMM }, { 0 }},
 
 /* vsub4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ.  */
-{ "vsub4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+{ "vsub4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RBD, RBDdup, LIMM }, { C_CC }},
 
 /* vsub4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ.  */
-{ "vsub4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+{ "vsub4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, RCD }, { C_CC }},
 
 /* vsub4h a,limm,u6 00101110011110010111uuuuuuAAAAAA.  */
-{ "vsub4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+{ "vsub4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, UIMM6_20 }, { 0 }},
 
 /* vsub4h 0,limm,u6 00101110011110010111uuuuuu111110.  */
 { "vsub4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -20050,7 +20050,7 @@ 
 { "vsub4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
 
 /* vsub4h a,limm,limm 00101110001110010111111110AAAAAA.  */
-{ "vsub4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+{ "vsub4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RAD, LIMM, LIMMdup }, { 0 }},
 
 /* vsub4h 0,limm,limm 00101110001110010111111110111110.  */
 { "vsub4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
-- 
2.26.2