x86: introduce %BW to avoid going through vex_w_table[]

Message ID 672b778c-49bb-0459-916c-d5b9ccb2afba@suse.com
State New
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Series
  • x86: introduce %BW to avoid going through vex_w_table[]
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Commit Message

Jan Beulich July 6, 2020, 11:54 a.m.
This parallels %LW and %XW.

opcodes/
2020-07-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
	EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
	EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
	EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
	Delete.
	(putop): Handle "BW".
	* i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
	0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
	and 0F3A3F ...
	* i386-dis-evex-prefix.h: ... here.

---
A question is whether %LW wouldn't be nice to get converted to %DQ, to
make more immediately visible both its effect and its relationship to
%BW. (Introducing new multi-character macros has become quite a bit
easier recently, after all.)

Comments

Jose E. Marchesi via Binutils July 6, 2020, 11:57 a.m. | #1
On Mon, Jul 6, 2020 at 4:54 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> This parallels %LW and %XW.

>

> opcodes/

> 2020-07-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,

>         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,

>         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,

>         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):

>         Delete.

>         (putop): Handle "BW".

>         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,

>         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,

>         and 0F3A3F ...

>         * i386-dis-evex-prefix.h: ... here.

>


OK.

Thanks.

-- 
H.J.
Jan Beulich July 6, 2020, 12:04 p.m. | #2
On 06.07.2020 13:57, H.J. Lu wrote:
> On Mon, Jul 6, 2020 at 4:54 AM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> This parallels %LW and %XW.

>>

>> opcodes/

>> 2020-07-XX  Jan Beulich  <jbeulich@suse.com>

>>

>>         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,

>>         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,

>>         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,

>>         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):

>>         Delete.

>>         (putop): Handle "BW".

>>         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,

>>         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,

>>         and 0F3A3F ...

>>         * i386-dis-evex-prefix.h: ... here.

>>

> 

> OK.


Thanks. Any thoughts on the post-commit-message question, either way?

Jan
Jose E. Marchesi via Binutils July 6, 2020, 12:13 p.m. | #3
On Mon, Jul 6, 2020 at 5:04 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 06.07.2020 13:57, H.J. Lu wrote:

> > On Mon, Jul 6, 2020 at 4:54 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>

> >> This parallels %LW and %XW.

> >>

> >> opcodes/

> >> 2020-07-XX  Jan Beulich  <jbeulich@suse.com>

> >>

> >>         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,

> >>         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,

> >>         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,

> >>         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):

> >>         Delete.

> >>         (putop): Handle "BW".

> >>         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,

> >>         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,

> >>         and 0F3A3F ...

> >>         * i386-dis-evex-prefix.h: ... here.

> >>

> >

> > OK.

>

> Thanks. Any thoughts on the post-commit-message question, either way?

>


Yes, convert "LW" to "DQ" looks nice.

Thanks.

-- 
H.J.

Patch

--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -474,8 +474,8 @@ 
   /* PREFIX_EVEX_0F3826 */
   {
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F3826_P_1) },
-    { VEX_W_TABLE (EVEX_W_0F3826_P_2) },
+    { "vptestnm%BW",	{ XMask, Vex, EXx }, 0 },
+    { "vptestm%BW",	{ XMask, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F3827 */
   {
@@ -486,13 +486,13 @@ 
   /* PREFIX_EVEX_0F3828 */
   {
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F3828_P_1) },
+    { "vpmovm2%BW",	{ XM, MaskR }, 0 },
     { VEX_W_TABLE (EVEX_W_0F3828_P_2) },
   },
   /* PREFIX_EVEX_0F3829 */
   {
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F3829_P_1) },
+    { "vpmov%BW2m",	{ XMask, EXx }, 0 },
     { VEX_W_TABLE (EVEX_W_0F3829_P_2) },
   },
   /* PREFIX_EVEX_0F382A */
@@ -693,7 +693,7 @@ 
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F3854_P_2) },
+    { "vpopcnt%BW",	{ XM, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F3855 */
   {
@@ -747,7 +747,7 @@ 
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F3866_P_2) },
+    { "vpblendm%BW",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F3868 */
   {
@@ -785,7 +785,7 @@ 
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F3875_P_2) },
+    { "vpermi2%BW",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F3876 */
   {
@@ -821,7 +821,7 @@ 
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F387D_P_2) },
+    { "vpermt2%BW",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F387E */
   {
@@ -869,7 +869,7 @@ 
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F388D_P_2) },
+    { "vperm%BW",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F388F */
   {
@@ -1227,13 +1227,13 @@ 
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F3A3E_P_2) },
+    { "vpcmpu%BW",	{ XMask, Vex, EXx, VPCMP }, 0 },
   },
   /* PREFIX_EVEX_0F3A3F */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F3A3F_P_2) },
+    { "vpcmp%BW",	{ XMask, Vex, EXx, VPCMP }, 0 },
   },
   /* PREFIX_EVEX_0F3A42 */
   {
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -442,31 +442,11 @@ 
   {
     { "vpmovsxdq",	{ XM, EXxmmq }, 0 },
   },
-  /* EVEX_W_0F3826_P_1 */
-  {
-    { "vptestnmb",	{ XMask, Vex, EXx }, 0 },
-    { "vptestnmw",	{ XMask, Vex, EXx }, 0 },
-  },
-  /* EVEX_W_0F3826_P_2 */
-  {
-    { "vptestmb",	{ XMask, Vex, EXx }, 0 },
-    { "vptestmw",	{ XMask, Vex, EXx }, 0 },
-  },
-  /* EVEX_W_0F3828_P_1 */
-  {
-    { "vpmovm2b",	{ XM, MaskR }, 0 },
-    { "vpmovm2w",	{ XM, MaskR }, 0 },
-  },
   /* EVEX_W_0F3828_P_2 */
   {
     { Bad_Opcode },
     { "vpmuldq",	{ XM, Vex, EXx }, 0 },
   },
-  /* EVEX_W_0F3829_P_1 */
-  {
-    { "vpmovb2m",	{ XMask, EXx }, 0 },
-    { "vpmovw2m",	{ XMask, EXx }, 0 },
-  },
   /* EVEX_W_0F3829_P_2 */
   {
     { Bad_Opcode },
@@ -527,11 +507,6 @@ 
     { "vdpbf16ps",	{ XM, Vex, EXx }, 0 },
     { Bad_Opcode },
   },
-  /* EVEX_W_0F3854_P_2 */
-  {
-    { "vpopcntb",	{ XM, EXx }, 0 },
-    { "vpopcntw",	{ XM, EXx }, 0 },
-  },
   /* EVEX_W_0F3859_P_2 */
   {
     { "vbroadcasti32x2",	{ XM, EXxmm_mq }, 0 },
@@ -557,11 +532,6 @@ 
     { "vpcompressb",   { EXbScalar, XM }, 0 },
     { "vpcompressw",   { EXwScalar, XM }, 0 },
   },
-  /* EVEX_W_0F3866_P_2 */
-  {
-    { "vpblendmb",	{ XM, Vex, EXx }, 0 },
-    { "vpblendmw",	{ XM, Vex, EXx }, 0 },
-  },
   /* EVEX_W_0F3870_P_2 */
   {
     { Bad_Opcode },
@@ -582,11 +552,6 @@ 
     { "vcvtne2ps2bf16", { XM, Vex, EXx}, 0 },
     { Bad_Opcode },
   },
-  /* EVEX_W_0F3875_P_2 */
-  {
-    { "vpermi2b",	{ XM, Vex, EXx }, 0 },
-    { "vpermi2w",	{ XM, Vex, EXx }, 0 },
-  },
   /* EVEX_W_0F387A_P_2 */
   {
     { "vpbroadcastb",	{ XM, Rd }, 0 },
@@ -595,21 +560,11 @@ 
   {
     { "vpbroadcastw",	{ XM, Rd }, 0 },
   },
-  /* EVEX_W_0F387D_P_2 */
-  {
-    { "vpermt2b",	{ XM, Vex, EXx }, 0 },
-    { "vpermt2w",	{ XM, Vex, EXx }, 0 },
-  },
   /* EVEX_W_0F3883_P_2 */
   {
     { Bad_Opcode },
     { "vpmultishiftqb",	{ XM, Vex, EXx }, 0 },
   },
-  /* EVEX_W_0F388D_P_2 */
-  {
-    { "vpermb",	{ XM, Vex, EXx }, 0 },
-    { "vpermw",	{ XM, Vex, EXx }, 0 },
-  },
   /* EVEX_W_0F3891_P_2 */
   {
     { "vpgatherqd",	{ XMxmmq, MVexVSIBQDWpX }, 0 },
@@ -732,16 +687,6 @@ 
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A3B_P_2_W_0) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A3B_P_2_W_1) },
   },
-  /* EVEX_W_0F3A3E_P_2 */
-  {
-    { "vpcmpub",	{ XMask, Vex, EXx, VPCMP }, 0 },
-    { "vpcmpuw",	{ XMask, Vex, EXx, VPCMP }, 0 },
-  },
-  /* EVEX_W_0F3A3F_P_2 */
-  {
-    { "vpcmpb",	{ XMask, Vex, EXx, VPCMP }, 0 },
-    { "vpcmpw",	{ XMask, Vex, EXx, VPCMP }, 0 },
-  },
   /* EVEX_W_0F3A42_P_2 */
   {
     { "vdbpsadbw",	{ XM, Vex, EXx, Ib }, 0 },
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2041,11 +2041,7 @@  enum
   EVEX_W_0F3824_P_1,
   EVEX_W_0F3825_P_1,
   EVEX_W_0F3825_P_2,
-  EVEX_W_0F3826_P_1,
-  EVEX_W_0F3826_P_2,
-  EVEX_W_0F3828_P_1,
   EVEX_W_0F3828_P_2,
-  EVEX_W_0F3829_P_1,
   EVEX_W_0F3829_P_2,
   EVEX_W_0F382A_P_1,
   EVEX_W_0F382A_P_2,
@@ -2060,23 +2056,18 @@  enum
   EVEX_W_0F3837_P_2,
   EVEX_W_0F383A_P_1,
   EVEX_W_0F3852_P_1,
-  EVEX_W_0F3854_P_2,
   EVEX_W_0F3859_P_2,
   EVEX_W_0F385A_P_2,
   EVEX_W_0F385B_P_2,
   EVEX_W_0F3862_P_2,
   EVEX_W_0F3863_P_2,
-  EVEX_W_0F3866_P_2,
   EVEX_W_0F3870_P_2,
   EVEX_W_0F3872_P_1,
   EVEX_W_0F3872_P_2,
   EVEX_W_0F3872_P_3,
-  EVEX_W_0F3875_P_2,
   EVEX_W_0F387A_P_2,
   EVEX_W_0F387B_P_2,
-  EVEX_W_0F387D_P_2,
   EVEX_W_0F3883_P_2,
-  EVEX_W_0F388D_P_2,
   EVEX_W_0F3891_P_2,
   EVEX_W_0F3893_P_2,
   EVEX_W_0F38A1_P_2,
@@ -2103,8 +2094,6 @@  enum
   EVEX_W_0F3A39_P_2,
   EVEX_W_0F3A3A_P_2,
   EVEX_W_0F3A3B_P_2,
-  EVEX_W_0F3A3E_P_2,
-  EVEX_W_0F3A3F_P_2,
   EVEX_W_0F3A42_P_2,
   EVEX_W_0F3A43_P_2,
   EVEX_W_0F3A70_P_2,
@@ -2180,6 +2169,7 @@  struct dis386 {
    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
    "LW" => print 'd', 'q' depending on the VEX.W bit
+   "BW" => print 'b' or 'w' depending on the EVEX.W bit
    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
 	   an operand size prefix, or suffix_always is true.  print
 	   'q' if rex prefix is present.
@@ -13087,6 +13077,8 @@  putop (const char *in_template, int size
 		*obufp++ = vex.w ? 'd': 's';
 	      else if (last[0] == 'L')
 		*obufp++ = vex.w ? 'q': 'd';
+	      else if (last[0] == 'B')
+		*obufp++ = vex.w ? 'w': 'b';
 	      else
 		abort ();
 	    }