arm: Add DFB instruction for ARMv8-R

Message ID 20200608110542.u7ije4vjsc7wvcuv@arm.com
State New
Headers show
Series
  • arm: Add DFB instruction for ARMv8-R
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Commit Message

Alex Coplan June 8, 2020, 11:05 a.m.
Hello,

This adds support for the DFB alias introduced in ARMv8-R AArch32.
Please see the Arm ARM supplement [0] for details.

Testing:
  * New unit test.
  * Regtested on arm-none-eabi.

OK for master? If so, I'll need a maintainer to commit on my behalf
since I don't have write access.

Thanks,
Alex

[0] : https://developer.arm.com/docs/ddi0568/latest

---

gas/ChangeLog:

2020-06-08  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-arm.c (insns): Add dfb.
	* testsuite/gas/arm/dfb.d: New test.
	* testsuite/gas/arm/dfb.s: Input for test.

opcodes/ChangeLog:

2020-06-08  Alex Coplan  <alex.coplan@arm.com>

	* arm-dis.c (arm_opcodes): Add dfb.
	(thumb32_opcodes): Add dfb.

Comments

David Faust via Binutils June 8, 2020, 2:18 p.m. | #1
Hi Alex,

> gas/ChangeLog:

> 

> 2020-06-08  Alex Coplan  <alex.coplan@arm.com>

> 

> 	* config/tc-arm.c (insns): Add dfb.

> 	* testsuite/gas/arm/dfb.d: New test.

> 	* testsuite/gas/arm/dfb.s: Input for test.

> 

> opcodes/ChangeLog:

> 

> 2020-06-08  Alex Coplan  <alex.coplan@arm.com>

> 

> 	* arm-dis.c (arm_opcodes): Add dfb.

> 	(thumb32_opcodes): Add dfb.

> 


Approved and applied.

Cheers
  Nick

Patch

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index a69300697f0..00fa2c76c83 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -24950,6 +24950,13 @@  static const struct asm_opcode insns[] =
 							ldrexd, t_ldrexd),
  TCE("stlexd",	1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
 							strexd, t_strexd),
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8r
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_v8r
+
+/* ARMv8-R instructions.  */
+ TUF("dfb",	57ff04c, f3bf8f4c, 0, (), noargs, noargs),
 
 /* Defined in V8 but is in undefined encoding space for earlier
    architectures.  However earlier architectures are required to treat
diff --git a/gas/testsuite/gas/arm/dfb.d b/gas/testsuite/gas/arm/dfb.d
new file mode 100644
index 00000000000..3cc434cfca0
--- /dev/null
+++ b/gas/testsuite/gas/arm/dfb.d
@@ -0,0 +1,15 @@ 
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <f_a32>:
+.*:	f57ff04c 	dfb
+
+[0-9a-f]+ <f_t32>:
+.*:	f3bf 8f4c 	dfb
+.*:	bf18      	it	ne
+.*:	f3bf 8f4c 	dfbne
+.*:	bf08      	it	eq
+.*:	f3bf 8f4c 	dfbeq
diff --git a/gas/testsuite/gas/arm/dfb.s b/gas/testsuite/gas/arm/dfb.s
new file mode 100644
index 00000000000..22e89b09568
--- /dev/null
+++ b/gas/testsuite/gas/arm/dfb.s
@@ -0,0 +1,14 @@ 
+// Test file for ARMv8-R dfb.
+.arch armv8-r
+.syntax unified
+
+f_a32:
+  dfb
+
+.thumb
+f_t32:
+  dfb
+  it ne
+  dfbne
+  it eq
+  dfbeq
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 79a3dc656a9..de62328ec9b 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -3685,6 +3685,10 @@  static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
     0xe320f010, 0xffffffff, "esb"},
 
+  /* V8-R instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
+    0xf57ff04c, 0xffffffff, "dfb"},
+
   /* V8 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0x0320f005, 0x0fffffff, "sevl"},
@@ -4735,6 +4739,10 @@  static const struct opcode32 thumb32_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
 
+  /* V8-R instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
+    0xf3bf8f4c, 0xffffffff, "dfb%c"},
+
   /* CRC32 instructions.  */
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},