Power10 VSX Mask Manipulation Operations

Message ID 20200511113142.GC27573@bubble.grove.modra.org
State New
Headers show
Series
  • Power10 VSX Mask Manipulation Operations
Related show

Commit Message

opcodes/
	* ppc-opc.c (MP, VXVAM_MASK): Define.
	(VXVAPS_MASK): Use VXVA_MASK.
	(powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
	vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
	vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
	vcntmbb, vcntmbh, vcntmbw, vcntmbd.
gas/
	* testsuite/gas/ppc/maskmanip.d,
	* testsuite/gas/ppc/maskmanip.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.


-- 
Alan Modra
Australia Development Lab, IBM

Patch

diff --git a/gas/testsuite/gas/ppc/maskmanip.d b/gas/testsuite/gas/ppc/maskmanip.d
new file mode 100644
index 0000000000..3cd2c4db56
--- /dev/null
+++ b/gas/testsuite/gas/ppc/maskmanip.d
@@ -0,0 +1,30 @@ 
+#as: -mpower10
+#objdump: -dr -Mpower10
+#name: mask manipulation operations
+
+.*
+
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+.*:	(10 10 0e 42|42 0e 10 10) 	mtvsrbm v0,r1
+.*:	(10 51 1e 42|42 1e 51 10) 	mtvsrhm v2,r3
+.*:	(10 92 2e 42|42 2e 92 10) 	mtvsrwm v4,r5
+.*:	(10 d3 3e 42|42 3e d3 10) 	mtvsrdm v6,r7
+.*:	(11 14 4e 42|42 4e 14 11) 	mtvsrqm v8,r9
+.*:	(11 5a 12 14|14 12 5a 11) 	mtvsrbmi v10,4660
+.*:	(11 60 66 42|42 66 60 11) 	vexpandbm v11,v12
+.*:	(11 a1 76 42|42 76 a1 11) 	vexpandhm v13,v14
+.*:	(11 e2 86 42|42 86 e2 11) 	vexpandwm v15,v16
+.*:	(12 23 96 42|42 96 23 12) 	vexpanddm v17,v18
+.*:	(12 64 a6 42|42 a6 64 12) 	vexpandqm v19,v20
+.*:	(12 a8 b6 42|42 b6 a8 12) 	vextractbm r21,v22
+.*:	(12 e9 c6 42|42 c6 e9 12) 	vextracthm r23,v24
+.*:	(13 2a d6 42|42 d6 2a 13) 	vextractwm r25,v26
+.*:	(13 6b e6 42|42 e6 6b 13) 	vextractdm r27,v28
+.*:	(13 ac f6 42|42 f6 ac 13) 	vextractqm r29,v30
+.*:	(13 f8 06 42|42 06 f8 13) 	vcntmbb r31,v0,0
+.*:	(13 db 0e 42|42 0e db 13) 	vcntmbh r30,v1,1
+.*:	(13 bd 16 42|42 16 bd 13) 	vcntmbw r29,v2,1
+.*:	(13 9e 1e 42|42 1e 9e 13) 	vcntmbd r28,v3,0
diff --git a/gas/testsuite/gas/ppc/maskmanip.s b/gas/testsuite/gas/ppc/maskmanip.s
new file mode 100644
index 0000000000..6e3688b387
--- /dev/null
+++ b/gas/testsuite/gas/ppc/maskmanip.s
@@ -0,0 +1,22 @@ 
+	.text
+_start:
+	mtvsrbm 0,1
+	mtvsrhm 2,3
+	mtvsrwm 4,5
+	mtvsrdm 6,7
+	mtvsrqm 8,9
+	mtvsrbmi 10,0x1234
+	vexpandbm 11,12
+	vexpandhm 13,14
+	vexpandwm 15,16
+	vexpanddm 17,18
+	vexpandqm 19,20
+	vextractbm 21,22
+	vextracthm 23,24
+	vextractwm 25,26
+	vextractdm 27,28
+	vextractqm 29,30
+	vcntmbb 31,0,0
+	vcntmbh 30,1,1
+	vcntmbw 29,2,1
+	vcntmbd 28,3,0
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 34cc82c9f3..c250acfd3e 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -138,3 +138,4 @@  run_dump_test "vsx_32byte"
 run_dump_test "int128"
 run_dump_test "simd_perm"
 run_dump_test "outerprod"
+run_dump_test "maskmanip"
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 5e122ef2e9..4e207b488f 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2886,6 +2886,7 @@  const struct powerpc_operand powerpc_operands[] =
   { 0x3, 9, NULL, NULL, 0 },
 
 #define R RMC + 1
+#define MP R
   { 0x1, 16, NULL, NULL, 0 },
 
 #define RIC R + 1
@@ -3492,7 +3493,10 @@  const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
 
 /* A VX_MASK with the VA field fixed with a PS field.  */
-#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
+#define VXVAPS_MASK (VXVA_MASK & ~(0x1 << 9))
+
+/* A VX_MASK with the VA field fixed with a MP field.  */
+#define VXVAM_MASK (VXVA_MASK & ~(0x1 << 16))
 
 /* A VX_MASK for instructions using a BF field.  */
 #define VXBF_MASK (VX_MASK | (3 << 21))
@@ -4114,6 +4118,7 @@  const struct powerpc_opcode powerpc_opcodes[] = {
 {"vinsbvlx",	VX (4,  15),	VX_MASK,     POWER10,	0,		{VD, RA, VB}},
 {"mulhhwu",	XRC(4,	 8,0),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
 {"mulhhwu.",	XRC(4,	 8,1),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
+{"mtvsrbmi",	DX (4,10),	DX_MASK,     POWER10,	0,		{VD, DXD}},
 {"ps_sum0",	A  (4,	10,0),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
 {"ps_sum0.",	A  (4,	10,1),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
 {"vsldbi",	VX (4,  22),	VXSH_MASK,   POWER10,	0,		{VD, VA, VB, SH3}},
@@ -4898,6 +4903,27 @@  const struct powerpc_opcode powerpc_opcodes[] = {
 {"vmoduq",	VX (4,1547),	VX_MASK,     POWER10,	0,		{VD, VA, VB}},
 {"vextublx",	VX (4,1549),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
 {"vsubuhs",	VX (4,1600),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},
+
+{"vexpandbm",	VXVA(4,1602,0),  VXVA_MASK,  POWER10,	0,		{VD, VB}},
+{"vexpandhm",	VXVA(4,1602,1),  VXVA_MASK,  POWER10,	0,		{VD, VB}},
+{"vexpandwm",	VXVA(4,1602,2),  VXVA_MASK,  POWER10,	0,		{VD, VB}},
+{"vexpanddm",	VXVA(4,1602,3),  VXVA_MASK,  POWER10,	0,		{VD, VB}},
+{"vexpandqm",	VXVA(4,1602,4),  VXVA_MASK,  POWER10,	0,		{VD, VB}},
+{"vextractbm",	VXVA(4,1602,8),  VXVA_MASK,  POWER10,	0,		{RT, VB}},
+{"vextracthm",	VXVA(4,1602,9),  VXVA_MASK,  POWER10,	0,		{RT, VB}},
+{"vextractwm",	VXVA(4,1602,10), VXVA_MASK,  POWER10,	0,		{RT, VB}},
+{"vextractdm",	VXVA(4,1602,11), VXVA_MASK,  POWER10,	0,		{RT, VB}},
+{"vextractqm",	VXVA(4,1602,12), VXVA_MASK,  POWER10,	0,		{RT, VB}},
+{"mtvsrbm",	VXVA(4,1602,16), VXVA_MASK,  POWER10,	0,		{VD, RB}},
+{"mtvsrhm",	VXVA(4,1602,17), VXVA_MASK,  POWER10,	0,		{VD, RB}},
+{"mtvsrwm",	VXVA(4,1602,18), VXVA_MASK,  POWER10,	0,		{VD, RB}},
+{"mtvsrdm",	VXVA(4,1602,19), VXVA_MASK,  POWER10,	0,		{VD, RB}},
+{"mtvsrqm",	VXVA(4,1602,20), VXVA_MASK,  POWER10,	0,		{VD, RB}},
+{"vcntmbb",	VXVA(4,1602,24), VXVAM_MASK, POWER10,	0,		{RT, VB, MP}},
+{"vcntmbh",	VXVA(4,1602,26), VXVAM_MASK, POWER10,	0,		{RT, VB, MP}},
+{"vcntmbw",	VXVA(4,1602,28), VXVAM_MASK, POWER10,	0,		{RT, VB, MP}},
+{"vcntmbd",	VXVA(4,1602,30), VXVAM_MASK, POWER10,	0,		{RT, VB, MP}},
+
 {"mtvscr",	VX (4,1604),	VXVDVA_MASK, PPCVEC,	0,		{VB}},
 {"vcmpgtuh.",	VXR(4, 582,1),	VXR_MASK,    PPCVEC,	0,		{VD, VA, VB}},
 {"vsum4shs",	VX (4,1608),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},