[v4,07/12] aarch64: Rename CC_ADCmode to CC_NOTCmode

Message ID 20200410034853.4322-8-richard.henderson@linaro.org
State New
Headers show
Series
  • aarch64: Implement TImode comparisons
Related show

Commit Message

Jakub Jelinek via Gcc-patches April 10, 2020, 3:48 a.m.
We are about to use !C in more contexts than add-with-carry.
Choose a more generic name.

	* config/aarch64/aarch64-modes.def (CC_NOTC): Rename CC_ADC.
	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Update.
	(aarch64_get_condition_code_1): Likewise.
	* config/aarch64/aarch64.md (addvti4): Likewise.
	(add<GPI>3_carryinC): Likewise.
	(*add<GPI>3_carryinC_zero): Likewise.
	(*add<GPI>3_carryinC): Likewise.
---
 gcc/config/aarch64/aarch64.c         |  4 ++--
 gcc/config/aarch64/aarch64-modes.def |  5 +++--
 gcc/config/aarch64/aarch64.md        | 14 +++++++-------
 gcc/config/aarch64/predicates.md     |  4 ++--
 4 files changed, 14 insertions(+), 13 deletions(-)

-- 
2.20.1

Patch

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index cd4dc1ef6f9..c09b7bcb7f0 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -9530,7 +9530,7 @@  aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
       && code_x == PLUS
       && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
       && const_dword_umaxp1 (y, mode_x))
-    return CC_ADCmode;
+    return CC_NOTCmode;
 
   /* A test for signed overflow.  */
   if ((mode_x == DImode || mode_x == TImode)
@@ -9663,7 +9663,7 @@  aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
 	}
       break;
 
-    case E_CC_ADCmode:
+    case E_CC_NOTCmode:
       switch (comp_code)
 	{
 	case GEU: return AARCH64_CS;
diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def
index af972e8f72b..181b7b30dcd 100644
--- a/gcc/config/aarch64/aarch64-modes.def
+++ b/gcc/config/aarch64/aarch64-modes.def
@@ -29,7 +29,7 @@ 
    CCmode is used for 'normal' compare (subtraction) operations.  For
    ADC, the representation becomes more complex still, since we cannot
    use the normal idiom of comparing the result to one of the input
-   operands; instead we use CC_ADCmode to represent this case.  */
+   operands; instead we use CC_NOTCmode to represent this case.  */
 CC_MODE (CCFP);
 CC_MODE (CCFPE);
 CC_MODE (CC_SWP);
@@ -38,7 +38,8 @@  CC_MODE (CC_NZC);   /* Only N, Z and C bits of condition flags are valid.
 CC_MODE (CC_NZ);    /* Only N and Z bits of condition flags are valid.  */
 CC_MODE (CC_Z);     /* Only Z bit of condition flags is valid.  */
 CC_MODE (CC_C);     /* C represents unsigned overflow of a simple addition.  */
-CC_MODE (CC_ADC);   /* Unsigned overflow from an ADC (add with carry).  */
+CC_MODE (CC_NOTC);  /* !C represents unsigned overflow of subtraction,
+                       as well as our representation of add-with-carry.  */
 CC_MODE (CC_V);     /* Only V bit of condition flags is valid.  */
 
 /* Half-precision floating point for __fp16.  */
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d51f6146c43..7d4a63f9a2a 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2077,7 +2077,7 @@ 
 			   CODE_FOR_adddi3_compareC,
 			   CODE_FOR_adddi3_compareC,
 			   CODE_FOR_adddi3_carryinC);
-  aarch64_gen_unlikely_cbranch (GEU, CC_ADCmode, operands[3]);
+  aarch64_gen_unlikely_cbranch (GEU, CC_NOTCmode, operands[3]);
   DONE;
 })
 
@@ -2580,7 +2580,7 @@ 
 (define_expand "add<mode>3_carryinC"
   [(parallel
      [(set (match_dup 3)
-	   (compare:CC_ADC
+	   (compare:CC_NOTC
 	     (plus:<DWI>
 	       (plus:<DWI>
 		 (match_dup 4)
@@ -2595,7 +2595,7 @@ 
 	     (match_dup 2)))])]
    ""
 {
-  operands[3] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
+  operands[3] = gen_rtx_REG (CC_NOTCmode, CC_REGNUM);
   rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
   operands[4] = gen_rtx_LTU (<DWI>mode, ccin, const0_rtx);
   operands[5] = gen_rtx_LTU (<MODE>mode, ccin, const0_rtx);
@@ -2605,8 +2605,8 @@ 
 })
 
 (define_insn "*add<mode>3_carryinC_zero"
-  [(set (reg:CC_ADC CC_REGNUM)
-	(compare:CC_ADC
+  [(set (reg:CC_NOTC CC_REGNUM)
+	(compare:CC_NOTC
 	  (plus:<DWI>
 	    (match_operand:<DWI> 2 "aarch64_carry_operation" "")
 	    (zero_extend:<DWI> (match_operand:GPI 1 "register_operand" "r")))
@@ -2620,8 +2620,8 @@ 
 )
 
 (define_insn "*add<mode>3_carryinC"
-  [(set (reg:CC_ADC CC_REGNUM)
-	(compare:CC_ADC
+  [(set (reg:CC_NOTC CC_REGNUM)
+	(compare:CC_NOTC
 	  (plus:<DWI>
 	    (plus:<DWI>
 	      (match_operand:<DWI> 3 "aarch64_carry_operation" "")
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 99c3bfbace4..e3572d2f60d 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -390,7 +390,7 @@ 
   machine_mode ccmode = GET_MODE (op0);
   if (ccmode == CC_Cmode)
     return GET_CODE (op) == LTU;
-  if (ccmode == CC_ADCmode || ccmode == CCmode)
+  if (ccmode == CC_NOTCmode || ccmode == CCmode)
     return GET_CODE (op) == GEU;
   return false;
 })
@@ -408,7 +408,7 @@ 
   machine_mode ccmode = GET_MODE (op0);
   if (ccmode == CC_Cmode)
     return GET_CODE (op) == GEU;
-  if (ccmode == CC_ADCmode || ccmode == CCmode)
+  if (ccmode == CC_NOTCmode || ccmode == CCmode)
     return GET_CODE (op) == LTU;
   return false;
 })