[PATH] Enable GCC support for SERIALIZE

Message ID CAMZc-byqb-2WP2H5XjUcLumpNR5hV-Hpb7h-ikAbyd1b2NHFjw@mail.gmail.com
State New
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  • [PATH] Enable GCC support for SERIALIZE
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Commit Message

Iain Buclaw via Gcc-patches April 1, 2020, 7:29 a.m.
Hi:
  This patch is about to enable GCC support for SERIALIZE which would
be in GLC. There's only 1 instruction: SERIALIZE, more details please
refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
  I know it's stage4 right now, and patches are approved only for bug
fixed, but since many users prefer to use release version other than
build from trunk, i'd like to see this patch landed on GCC10, after
all it's only 1 instruction, without any significant changes.

  Bootstrap ok, regression test on i386/x86 backend is ok.

gcc/Changelog:
        * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
        OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
        (ix86_handle_option): Handle -mserialize.
        * gcc/config.gcc (serializeintrin.h): New header file.
        * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.
        * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect
        -mserialize.
        * gcc/config/i386/i386-builtin.def: Add new builtin.
        * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.
        * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):
          Add -mserialize.
        * (ix86_valid_target_attribute_inner_p): Add target attribute
        * for serialize.
        * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
          New macros.
        * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
          (serialize): New define_insn.
        * gcc/config/i386/i386.opt (mserialize): New option
        * gcc/config/i386/immintrin.h: Include serailizeintrin.h.
        * gcc/config/i386/serializeintrin.h: New header file.
        * gcc/doc/invoke.texi: Add documents for -mserialize.

gcc/testsuite/Changelog
        * gcc/testsuite/gcc.target/i386/serialize-1.c: New test.
        * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.
        * gcc/testsuite/g++.dg/other/i386-3.C: Ditto.
        * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.
        * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.
        * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.
        * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.
        * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.



-- 
BR,
Hongtao

Comments

Iain Buclaw via Gcc-patches April 1, 2020, 7:36 a.m. | #1
On Wed, Apr 1, 2020 at 9:23 AM Hongtao Liu <crazylht@gmail.com> wrote:
>

> Hi:

>   This patch is about to enable GCC support for SERIALIZE which would

> be in GLC. There's only 1 instruction: SERIALIZE, more details please

> refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

>   I know it's stage4 right now, and patches are approved only for bug

> fixed, but since many users prefer to use release version other than

> build from trunk, i'd like to see this patch landed on GCC10, after

> all it's only 1 instruction, without any significant changes.

>

>   Bootstrap ok, regression test on i386/x86 backend is ok.


No, this should wait for gcc-11.

Uros.

> gcc/Changelog:

>         * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,

>         OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.

>         (ix86_handle_option): Handle -mserialize.

>         * gcc/config.gcc (serializeintrin.h): New header file.

>         * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.

>         * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect

>         -mserialize.

>         * gcc/config/i386/i386-builtin.def: Add new builtin.

>         * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.

>         * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):

>           Add -mserialize.

>         * (ix86_valid_target_attribute_inner_p): Add target attribute

>         * for serialize.

>         * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):

>           New macros.

>         * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.

>           (serialize): New define_insn.

>         * gcc/config/i386/i386.opt (mserialize): New option

>         * gcc/config/i386/immintrin.h: Include serailizeintrin.h.

>         * gcc/config/i386/serializeintrin.h: New header file.

>         * gcc/doc/invoke.texi: Add documents for -mserialize.

>

> gcc/testsuite/Changelog

>         * gcc/testsuite/gcc.target/i386/serialize-1.c: New test.

>         * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.

>         * gcc/testsuite/g++.dg/other/i386-3.C: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.

>

>

>

> --

> BR,

> Hongtao
Iain Buclaw via Gcc-patches May 2, 2020, 2:35 a.m. | #2
ping.

> On Wed, Apr 1, 2020 at 9:23 AM Hongtao Liu <crazylht@gmail.com> wrote:

>>

>> Hi:

>>   This patch is about to enable GCC support for SERIALIZE which would

>> be in GLC. There's only 1 instruction: SERIALIZE, more details please

>> refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

>>   I know it's stage4 right now, and patches are approved only for bug

>> fixed, but since many users prefer to use release version other than

>> build from trunk, i'd like to see this patch landed on GCC10, after

>> all it's only 1 instruction, without any significant changes.

>>

>>   Bootstrap ok, regression test on i386/x86 backend is ok.

>

> No, this should wait for gcc-11.

>

> Uros.

>

>> gcc/Changelog:

>>         * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,

>>         OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.

>>         (ix86_handle_option): Handle -mserialize.

>>         * gcc/config.gcc (serializeintrin.h): New header file.

>>         * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.

>>         * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect

>>         -mserialize.

>>         * gcc/config/i386/i386-builtin.def: Add new builtin.

>>         * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.

>>         * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):

>>           Add -mserialize.

>>         * (ix86_valid_target_attribute_inner_p): Add target attribute

>>         * for serialize.

>>         * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):

>>           New macros.

>>         * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.

>>           (serialize): New define_insn.

>>         * gcc/config/i386/i386.opt (mserialize): New option

>>         * gcc/config/i386/immintrin.h: Include serailizeintrin.h.

>>         * gcc/config/i386/serializeintrin.h: New header file.

>>         * gcc/doc/invoke.texi: Add documents for -mserialize.

>>

>> gcc/testsuite/Changelog

>>         * gcc/testsuite/gcc.target/i386/serialize-1.c: New test.

>>         * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.

>>         * gcc/testsuite/g++.dg/other/i386-3.C: Ditto.

>>         * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.

>>         * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.

>>         * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.

>>         * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.

>>         * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.

>>

>>

>>

>> --

>> BR,

>> Hongtao
Iain Buclaw via Gcc-patches May 3, 2020, 5:17 p.m. | #3
On Wed, Apr 1, 2020 at 9:23 AM Hongtao Liu <crazylht@gmail.com> wrote:
>

> Hi:

>   This patch is about to enable GCC support for SERIALIZE which would

> be in GLC. There's only 1 instruction: SERIALIZE, more details please

> refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

>   I know it's stage4 right now, and patches are approved only for bug

> fixed, but since many users prefer to use release version other than

> build from trunk, i'd like to see this patch landed on GCC10, after

> all it's only 1 instruction, without any significant changes.

>

>   Bootstrap ok, regression test on i386/x86 backend is ok.

>

> gcc/Changelog:

>         * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,

>         OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.

>         (ix86_handle_option): Handle -mserialize.

>         * gcc/config.gcc (serializeintrin.h): New header file.

>         * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.

>         * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect

>         -mserialize.

>         * gcc/config/i386/i386-builtin.def: Add new builtin.

>         * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.

>         * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):

>           Add -mserialize.

>         * (ix86_valid_target_attribute_inner_p): Add target attribute

>         * for serialize.

>         * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):

>           New macros.

>         * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.

>           (serialize): New define_insn.

>         * gcc/config/i386/i386.opt (mserialize): New option

>         * gcc/config/i386/immintrin.h: Include serailizeintrin.h.

>         * gcc/config/i386/serializeintrin.h: New header file.

>         * gcc/doc/invoke.texi: Add documents for -mserialize.

>

> gcc/testsuite/Changelog

>         * gcc/testsuite/gcc.target/i386/serialize-1.c: New test.

>         * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.

>         * gcc/testsuite/g++.dg/other/i386-3.C: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.

>         * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.

>


Please add new option to gcc.target/i386/funcspec-56.h test file.

Just a couple of nits:

+/* { dg-final { scan-assembler-times "serialize\[^-]"  1 } } */

Simply scan for "\tserialize", we are sure that file name won't
interfere, because it is always quoted.

/* { dg-final { scan-assembler "\tserialize" } } */

+void
+foo (void)
+{
+   _serialize ();
+   return;
+}

No need for explicit return.

OK with the above fixes.

Thanks,
Uros.


>

> --

> BR,

> Hongtao
Iain Buclaw via Gcc-patches May 6, 2020, 3:17 a.m. | #4
On Mon, May 4, 2020 at 1:17 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>

> On Wed, Apr 1, 2020 at 9:23 AM Hongtao Liu <crazylht@gmail.com> wrote:

> >

> > Hi:

> >   This patch is about to enable GCC support for SERIALIZE which would

> > be in GLC. There's only 1 instruction: SERIALIZE, more details please

> > refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

> >   I know it's stage4 right now, and patches are approved only for bug

> > fixed, but since many users prefer to use release version other than

> > build from trunk, i'd like to see this patch landed on GCC10, after

> > all it's only 1 instruction, without any significant changes.

> >

> >   Bootstrap ok, regression test on i386/x86 backend is ok.

> >

> > gcc/Changelog:

> >         * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,

> >         OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.

> >         (ix86_handle_option): Handle -mserialize.

> >         * gcc/config.gcc (serializeintrin.h): New header file.

> >         * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.

> >         * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect

> >         -mserialize.

> >         * gcc/config/i386/i386-builtin.def: Add new builtin.

> >         * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.

> >         * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):

> >           Add -mserialize.

> >         * (ix86_valid_target_attribute_inner_p): Add target attribute

> >         * for serialize.

> >         * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):

> >           New macros.

> >         * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.

> >           (serialize): New define_insn.

> >         * gcc/config/i386/i386.opt (mserialize): New option

> >         * gcc/config/i386/immintrin.h: Include serailizeintrin.h.

> >         * gcc/config/i386/serializeintrin.h: New header file.

> >         * gcc/doc/invoke.texi: Add documents for -mserialize.

> >

> > gcc/testsuite/Changelog

> >         * gcc/testsuite/gcc.target/i386/serialize-1.c: New test.

> >         * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.

> >         * gcc/testsuite/g++.dg/other/i386-3.C: Ditto.

> >         * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.

> >         * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.

> >         * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.

> >         * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.

> >         * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.

> >

>

> Please add new option to gcc.target/i386/funcspec-56.h test file.

>


Done.

> Just a couple of nits:

>

> +/* { dg-final { scan-assembler-times "serialize\[^-]"  1 } } */

>

> Simply scan for "\tserialize", we are sure that file name won't

> interfere, because it is always quoted.

>

> /* { dg-final { scan-assembler "\tserialize" } } */

>

> +void

> +foo (void)

> +{

> +   _serialize ();

> +   return;

> +}

>

> No need for explicit return.

>

> OK with the above fixes.

>


Changed.

> Thanks,

> Uros.

>

>

> >

> > --

> > BR,

> > Hongtao


Update patch.

-- 
BR,
Hongtao
From cc08d7292bba7d6aec942c160a8e562597de7d95 Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Wed, 4 Mar 2020 14:08:40 +0800
Subject: [PATCH] Enable GCC support for SERIALIZE

2020-03-04  Hongtao Liu  <hongtao.liu@intel.com>
2020-03-04  Wei Xiao  <wei3.xiao@intel.com>

gcc/Changelog:
	* gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
	OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
	(ix86_handle_option): Handle -mserialize.
	* gcc/config.gcc (serializeintrin.h): New header file.
	* gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.
	* gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect
	-mserialize.
	* gcc/config/i386/i386-builtin.def: Add new builtin.
	* gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.
	* gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):
	  Add -mserialize.
	* (ix86_valid_target_attribute_inner_p): Add target attribute
	* for serialize.
	* gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
	  New macros.
	* gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
	  (serialize): New define_insn.
	* gcc/config/i386/i386.opt (mserialize): New option
	* gcc/config/i386/immintrin.h: Include serailizeintrin.h.
	* gcc/config/i386/serializeintrin.h: New header file.
	* gcc/doc/invoke.texi: Add documents for -mserialize.

gcc/testsuite/Changelog
	* gcc/testsuite/gcc.target/i386/serialize-1.c: New test.
	* gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.
	* gcc/testsuite/g++.dg/other/i386-3.C: Ditto.
	* gcc/testsuite/gcc.target/i386/funcspec-56.inc: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.
---
 gcc/common/config/i386/i386-common.c          | 15 ++++++
 gcc/config.gcc                                | 10 ++--
 gcc/config/i386/cpuid.h                       |  1 +
 gcc/config/i386/driver-i386.c                 |  5 +-
 gcc/config/i386/i386-builtin.def              |  3 ++
 gcc/config/i386/i386-c.c                      |  2 +
 gcc/config/i386/i386-options.c                |  4 +-
 gcc/config/i386/i386.h                        |  2 +
 gcc/config/i386/i386.md                       | 10 ++++
 gcc/config/i386/i386.opt                      |  4 ++
 gcc/config/i386/immintrin.h                   |  2 +
 gcc/config/i386/serializeintrin.h             | 49 +++++++++++++++++++
 gcc/doc/invoke.texi                           | 11 +++--
 gcc/testsuite/g++.dg/other/i386-2.C           |  2 +-
 gcc/testsuite/g++.dg/other/i386-3.C           |  2 +-
 gcc/testsuite/gcc.target/i386/funcspec-56.inc |  2 +
 gcc/testsuite/gcc.target/i386/serialize-1.c   | 11 +++++
 gcc/testsuite/gcc.target/i386/sse-12.c        |  2 +-
 gcc/testsuite/gcc.target/i386/sse-13.c        |  2 +-
 gcc/testsuite/gcc.target/i386/sse-14.c        |  2 +-
 gcc/testsuite/gcc.target/i386/sse-22.c        |  4 +-
 gcc/testsuite/gcc.target/i386/sse-23.c        |  2 +-
 22 files changed, 129 insertions(+), 18 deletions(-)
 create mode 100644 gcc/config/i386/serializeintrin.h
 create mode 100644 gcc/testsuite/gcc.target/i386/serialize-1.c

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 02b19f1bb54..0a164e2c6b8 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -158,6 +158,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
+#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
 
 /* Define a set of ISAs which aren't available when a given ISA is
    disabled.  MMX and SSE ISAs are handled separately.  */
@@ -241,6 +242,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
+#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
@@ -677,6 +679,19 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       return true;
 
+    case OPT_mserialize:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
+	}
+      return true;
+
     case OPT_mavx5124fmaps:
       if (value)
 	{
diff --git a/gcc/config.gcc b/gcc/config.gcc
index cf1a87e2efd..d48b6c773d2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -412,8 +412,9 @@ i[34567]86-*-*)
 		       avx512vnnivlintrin.h vaesintrin.h vpclmulqdqintrin.h
 		       avx512vpopcntdqvlintrin.h avx512bitalgintrin.h
 		       pconfigintrin.h wbnoinvdintrin.h movdirintrin.h
-		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h
-		       enqcmdintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h"
+		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h
+		       avx512bf16intrin.h enqcmdintrin.h serializeintrin.h
+		       avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h"
 	;;
 x86_64-*-*)
 	cpu_type=i386
@@ -445,8 +446,9 @@ x86_64-*-*)
 		       avx512vnnivlintrin.h vaesintrin.h vpclmulqdqintrin.h
 		       avx512vpopcntdqvlintrin.h avx512bitalgintrin.h
 		       pconfigintrin.h wbnoinvdintrin.h movdirintrin.h
-		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h
-		       enqcmdintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h"
+		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h
+		       avx512bf16intrin.h enqcmdintrin.h serializeintrin.h
+		       avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h"
 	;;
 ia64-*-*)
 	extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 34a7956d36a..d3fbde93400 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -122,6 +122,7 @@
 #define bit_AVX512VP2INTERSECT	(1 << 8)
 #define bit_IBT	(1 << 20)
 #define bit_PCONFIG	(1 << 18)
+#define bit_SERIALIZE	(1 << 14)
 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
 #define bit_BNDREGS     (1 << 3)
 #define bit_BNDCSR      (1 << 4)
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 130e12c8868..2ef44acb9b4 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -429,6 +429,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
   unsigned int has_waitpkg = 0;
   unsigned int has_cldemote = 0;
   unsigned int has_avx512bf16 = 0;
+  unsigned int has_serialize = 0;
 
   unsigned int has_ptwrite = 0;
 
@@ -534,6 +535,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       has_avx5124vnniw = edx & bit_AVX5124VNNIW;
       has_avx5124fmaps = edx & bit_AVX5124FMAPS;
       has_avx512vp2intersect = edx & bit_AVX512VP2INTERSECT;
+      has_serialize = edx & bit_SERIALIZE;
 
       has_shstk = ecx & bit_SHSTK;
       has_pconfig = edx & bit_PCONFIG;
@@ -1161,6 +1163,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       const char *enqcmd = has_enqcmd ? " -menqcmd" : " -mno-enqcmd";
       const char *waitpkg = has_waitpkg ? " -mwaitpkg" : " -mno-waitpkg";
       const char *cldemote = has_cldemote ? " -mcldemote" : " -mno-cldemote";
+      const char *serialize = has_serialize ? " -mserialize" : " -mno-serialize";
       const char *ptwrite = has_ptwrite ? " -mptwrite" : " -mno-ptwrite";
       const char *avx512bf16 = has_avx512bf16 ? " -mavx512bf16" : " -mno-avx512bf16";
 
@@ -1178,7 +1181,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 			avx512vbmi2, avx512vnni, vaes, vpclmulqdq,
 			avx512bitalg, movdiri, movdir64b, waitpkg, cldemote,
 			ptwrite, avx512bf16, enqcmd, avx512vp2intersect,
-			NULL);
+			serialize, NULL);
     }
 
 done:
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 4d5863ce0aa..48c04d4f0e9 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -446,6 +446,9 @@ BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_PTWRITE, CODE_FOR_ptwritedi, "__b
 BDESC (0, OPTION_MASK_ISA2_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmd", IX86_BUILTIN_ENQCMD, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID)
 BDESC (0, OPTION_MASK_ISA2_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmds", IX86_BUILTIN_ENQCMDS, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID)
 
+/* SERIALIZE */
+BDESC (0, OPTION_MASK_ISA2_SERIALIZE, CODE_FOR_serialize, "__builtin_ia32_serialize", IX86_BUILTIN_SERIALIZE, UNKNOWN, (int) VOID_FTYPE_VOID)
+
 BDESC_END (SPECIAL_ARGS, ARGS)
 
 /* Builtins with variable number of arguments.  */
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 21ed7f4e99f..2ab5a813770 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -561,6 +561,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__WAITPKG__");
   if (isa_flag2 & OPTION_MASK_ISA2_CLDEMOTE)
     def_or_undef (parse_in, "__CLDEMOTE__");
+  if (isa_flag2 & OPTION_MASK_ISA2_SERIALIZE)
+    def_or_undef (parse_in, "__SERIALIZE__");
   if (isa_flag2 & OPTION_MASK_ISA2_PTWRITE)
     def_or_undef (parse_in, "__PTWRITE__");
   if (isa_flag2 & OPTION_MASK_ISA2_AVX512BF16)
diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
index 5c21fce06a4..8ad9f150286 100644
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@@ -205,7 +205,8 @@ static struct ix86_target_opts isa2_opts[] =
   { "-mcldemote",	OPTION_MASK_ISA2_CLDEMOTE },
   { "-mptwrite",	OPTION_MASK_ISA2_PTWRITE },
   { "-mavx512bf16",	OPTION_MASK_ISA2_AVX512BF16 },
-  { "-menqcmd",		OPTION_MASK_ISA2_ENQCMD }
+  { "-menqcmd",		OPTION_MASK_ISA2_ENQCMD },
+  { "-mserialize",	OPTION_MASK_ISA2_SERIALIZE }
 };
 static struct ix86_target_opts isa_opts[] =
 {
@@ -1017,6 +1018,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
     IX86_ATTR_ISA ("ptwrite",   OPT_mptwrite),
     IX86_ATTR_ISA ("avx512bf16",   OPT_mavx512bf16),
     IX86_ATTR_ISA ("enqcmd", OPT_menqcmd),
+    IX86_ATTR_ISA ("serialize", OPT_mserialize),
 
     /* enum options */
     IX86_ATTR_ENUM ("fpmath=",	OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 08245f64322..e907dfdfccb 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -199,6 +199,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_AVX512BF16_P(x)	TARGET_ISA2_AVX512BF16_P(x)
 #define TARGET_ENQCMD	TARGET_ISA2_ENQCMD
 #define TARGET_ENQCMD_P(x) TARGET_ISA2_ENQCMD_P(x)
+#define TARGET_SERIALIZE	TARGET_ISA2_SERIALIZE
+#define TARGET_SERIALIZE_P(x) TARGET_ISA2_SERIALIZE_P(x)
 
 #define TARGET_LP64	TARGET_ABI_64
 #define TARGET_LP64_P(x)	TARGET_ABI_64_P(x)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 898bb946a2d..8838ffec1a0 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -300,6 +300,9 @@
   ;; For ENQCMD and ENQCMDS support
   UNSPECV_ENQCMD
   UNSPECV_ENQCMDS
+
+  ;; For SERIALIZE support
+  UNSPECV_SERIALIZE
 ])
 
 ;; Constants to represent rounding modes in the ROUND instruction
@@ -21232,6 +21235,13 @@
   [(set_attr "type" "other")
    (set_attr "length" "3")])
 
+(define_insn "serialize"
+  [(unspec_volatile [(const_int 0)] UNSPECV_SERIALIZE)]
+  "TARGET_SERIALIZE"
+  "serialize"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
 (include "mmx.md")
 (include "sse.md")
 (include "sync.md")
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 185a1d0686b..9af05995b9d 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1107,3 +1107,7 @@ AVX512BF16 built-in functions and code generation.
 menqcmd
 Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save
 Support ENQCMD built-in functions and code generation.
+
+mserialize
+Target Report Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save
+Support SERIALIZE built-in functions and code generation.
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 12b118b0861..380e7f184f8 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -140,6 +140,8 @@
 
 #include <enqcmdintrin.h>
 
+#include <serializeintrin.h>
+
 #include <rdseedintrin.h>
 
 #include <prfchwintrin.h>
diff --git a/gcc/config/i386/serializeintrin.h b/gcc/config/i386/serializeintrin.h
new file mode 100644
index 00000000000..0c35b9ed1fa
--- /dev/null
+++ b/gcc/config/i386/serializeintrin.h
@@ -0,0 +1,49 @@
+/* Copyright (C) 2018 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+# error "Never use <serializeintrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _SERIALIZE_H_INCLUDED
+#define _SERIALIZE_H_INCLUDED
+
+#ifndef __SERIALIZE__
+#pragma GCC push_options
+#pragma GCC target("serialize")
+#define __DISABLE_SERIALIZE__
+#endif /* __SERIALIZE__ */
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_serialize (void)
+{
+  __builtin_ia32_serialize ();
+}
+
+#ifdef __DISABLE_SERIALIZE__
+#undef __DISABLE_SERIALIZE__
+#pragma GCC pop_options
+#endif /* __DISABLE_SERIALIZE__ */
+
+#endif /* _SERIALIZE_H_INCLUDED.  */
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 767d1f07801..09bc3dfcc32 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1344,7 +1344,7 @@ See RS/6000 and PowerPC Options.
 -mshstk -mmanual-endbr -mforce-indirect-call  -mavx512vbmi2 -mavx512bf16 -menqcmd @gol
 -mvpclmulqdq  -mavx512bitalg  -mmovdiri  -mmovdir64b  -mavx512vpopcntdq @gol
 -mavx5124fmaps  -mavx512vnni  -mavx5124vnniw  -mprfchw  -mrdpid @gol
--mrdseed  -msgx -mavx512vp2intersect@gol
+-mrdseed  -msgx -mavx512vp2intersect -mserialize @gol
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops @gol
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg} @gol
 -mmemcpy-strategy=@var{strategy}  -mmemset-strategy=@var{strategy} @gol
@@ -29485,6 +29485,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @itemx -mcldemote
 @opindex mcldemote
+@need 200
+@itemx -mserialize
+@opindex mserialize
 These switches enable the use of instructions in the MMX, SSE,
 SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,
 AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
@@ -29493,9 +29496,9 @@ WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,
 3DNow!@:, enhanced 3DNow!@:, POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE,
 XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,
 GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
-ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, or CLDEMOTE
-extended instruction sets.  Each has a corresponding @option{-mno-} option to
-disable use of these instructions.
+ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE
+or CLDEMOTE extended instruction sets.  Each has a corresponding
+@option{-mno-} option to disable use of these instructions.
 
 These extensions are also available as built-in functions: see
 @ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C
index 95314157170..dd9e6849cf2 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt  -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt  -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize" } */
 
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
    xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C
index 4912e7f40d1..1fdea53ae7a 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize" } */
 
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
    xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 200d27220df..84f8e31eb63 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -66,6 +66,7 @@ extern void test_clwb (void)			__attribute__((__target__("clwb")));
 
 extern void test_cld (void)			__attribute__((__target__("cld")));
 extern void test_recip (void)			__attribute__((__target__("recip")));
+extern void test_serialize (void)		__attribute__((__target__("serialize")));
 
 extern void test_no_sgx (void)			__attribute__((__target__("no-sgx")));
 extern void test_no_avx5124fmaps(void)		__attribute__((__target__("no-avx5124fmaps")));
@@ -133,6 +134,7 @@ extern void test_no_clwb (void)			__attribute__((__target__("no-clwb")));
 
 extern void test_no_cld (void)			__attribute__((__target__("no-cld")));
 extern void test_no_recip (void)		__attribute__((__target__("no-recip")));
+extern void test_no_serialize (void)		__attribute__((__target__("no-serialize")));
 
 extern void test_arch_nocona (void)		__attribute__((__target__("arch=nocona")));
 extern void test_arch_core2 (void)		__attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/serialize-1.c b/gcc/testsuite/gcc.target/i386/serialize-1.c
new file mode 100644
index 00000000000..29512b85d34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/serialize-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mserialize" } */
+/* { dg-final { scan-assembler-times "\tserialize"  1 } } */
+
+#include <x86intrin.h>
+
+void
+foo (void)
+{
+   _serialize ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c
index 6be531d88bf..0ab94b2692c 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@
    popcntintrin.h gfniintrin.h and mm_malloc.h are usable
    with -O -std=c89 -pedantic-errors.  */
 /* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize" } */
 
 #include <x86intrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index c2b192d72f6..472f7528a43 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize" } */
 /* { dg-add-options bind_pic_locally } */
 
 #include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 0d2b8b3cba0..396a4646e01 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize" } */
 /* { dg-add-options bind_pic_locally } */
 
 #include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index 9be7f2d5a58..581e16ba1d4 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -102,7 +102,7 @@
 
 
 #ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize")
 #endif
 
 /* Following intrinsics require immediate arguments.  They
@@ -219,7 +219,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
 
 /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
 #ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect")
+#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize")
 #endif
 #include <immintrin.h>
 test_1 (_cvtss_sh, unsigned short, float, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index e98c7693ef7..80891393336 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -697,6 +697,6 @@
 #define __builtin_ia32_vpclmulqdq_v2di(A, B, C)  __builtin_ia32_vpclmulqdq_v2di(A, B, 1) 
 #define __builtin_ia32_vpclmulqdq_v8di(A, B, C)  __builtin_ia32_vpclmulqdq_v8di(A, B, 1) 
 
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize")
 
 #include <x86intrin.h>
Iain Buclaw via Gcc-patches May 6, 2020, 6:39 a.m. | #5
On Wed, May 6, 2020 at 5:11 AM Hongtao Liu <crazylht@gmail.com> wrote:
>

> On Mon, May 4, 2020 at 1:17 AM Uros Bizjak <ubizjak@gmail.com> wrote:

> >

> > On Wed, Apr 1, 2020 at 9:23 AM Hongtao Liu <crazylht@gmail.com> wrote:

> > >

> > > Hi:

> > >   This patch is about to enable GCC support for SERIALIZE which would

> > > be in GLC. There's only 1 instruction: SERIALIZE, more details please

> > > refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

> > >   I know it's stage4 right now, and patches are approved only for bug

> > > fixed, but since many users prefer to use release version other than

> > > build from trunk, i'd like to see this patch landed on GCC10, after

> > > all it's only 1 instruction, without any significant changes.

> > >

> > >   Bootstrap ok, regression test on i386/x86 backend is ok.

> > >

> > > gcc/Changelog:

> > >         * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,

> > >         OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.

> > >         (ix86_handle_option): Handle -mserialize.

> > >         * gcc/config.gcc (serializeintrin.h): New header file.

> > >         * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.

> > >         * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect

> > >         -mserialize.

> > >         * gcc/config/i386/i386-builtin.def: Add new builtin.

> > >         * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.

> > >         * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):

> > >           Add -mserialize.

> > >         * (ix86_valid_target_attribute_inner_p): Add target attribute

> > >         * for serialize.

> > >         * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):

> > >           New macros.

> > >         * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.

> > >           (serialize): New define_insn.

> > >         * gcc/config/i386/i386.opt (mserialize): New option

> > >         * gcc/config/i386/immintrin.h: Include serailizeintrin.h.

> > >         * gcc/config/i386/serializeintrin.h: New header file.

> > >         * gcc/doc/invoke.texi: Add documents for -mserialize.

> > >

> > > gcc/testsuite/Changelog

> > >         * gcc/testsuite/gcc.target/i386/serialize-1.c: New test.

> > >         * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.

> > >         * gcc/testsuite/g++.dg/other/i386-3.C: Ditto.

> > >         * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.

> > >         * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.

> > >         * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.

> > >         * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.

> > >         * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.


OK.

Thanks,
Uros.

Patch

From b61dd0f3a503acb73b17e999991cd55d3ef7d477 Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Wed, 4 Mar 2020 14:08:40 +0800
Subject: [PATCH] Enable GCC support for SERIALIZE

2020-03-04  Hongtao Liu  <hongtao.liu@intel.com>
2020-03-04  Wei Xiao  <wei3.xiao@intel.com>

gcc/Changelog:
	* gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
	OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
	(ix86_handle_option): Handle -mserialize.
	* gcc/config.gcc (serializeintrin.h): New header file.
	* gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.
	* gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect
	-mserialize.
	* gcc/config/i386/i386-builtin.def: Add new builtin.
	* gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.
	* gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):
	  Add -mserialize.
	* (ix86_valid_target_attribute_inner_p): Add target attribute
	* for serialize.
	* gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
	  New macros.
	* gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
	  (serialize): New define_insn.
	* gcc/config/i386/i386.opt (mserialize): New option
	* gcc/config/i386/immintrin.h: Include serailizeintrin.h.
	* gcc/config/i386/serializeintrin.h: New header file.
	* gcc/doc/invoke.texi: Add documents for -mserialize.

gcc/testsuite/Changelog
	* gcc/testsuite/gcc.target/i386/serialize-1.c: New test.
	* gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.
	* gcc/testsuite/g++.dg/other/i386-3.C: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.
	* gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.
---
 gcc/common/config/i386/i386-common.c        | 15 +++++++
 gcc/config.gcc                              | 10 +++--
 gcc/config/i386/cpuid.h                     |  1 +
 gcc/config/i386/driver-i386.c               |  5 ++-
 gcc/config/i386/i386-builtin.def            |  3 ++
 gcc/config/i386/i386-c.c                    |  2 +
 gcc/config/i386/i386-options.c              |  4 +-
 gcc/config/i386/i386.h                      |  2 +
 gcc/config/i386/i386.md                     | 10 +++++
 gcc/config/i386/i386.opt                    |  4 ++
 gcc/config/i386/immintrin.h                 |  2 +
 gcc/config/i386/serializeintrin.h           | 49 +++++++++++++++++++++
 gcc/doc/invoke.texi                         | 11 +++--
 gcc/testsuite/g++.dg/other/i386-2.C         |  2 +-
 gcc/testsuite/g++.dg/other/i386-3.C         |  2 +-
 gcc/testsuite/gcc.target/i386/serialize-1.c | 12 +++++
 gcc/testsuite/gcc.target/i386/sse-12.c      |  2 +-
 gcc/testsuite/gcc.target/i386/sse-13.c      |  2 +-
 gcc/testsuite/gcc.target/i386/sse-14.c      |  2 +-
 gcc/testsuite/gcc.target/i386/sse-22.c      |  4 +-
 gcc/testsuite/gcc.target/i386/sse-23.c      |  2 +-
 21 files changed, 128 insertions(+), 18 deletions(-)
 create mode 100644 gcc/config/i386/serializeintrin.h
 create mode 100644 gcc/testsuite/gcc.target/i386/serialize-1.c

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 02b19f1bb54..0a164e2c6b8 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -158,6 +158,7 @@  along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
+#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
 
 /* Define a set of ISAs which aren't available when a given ISA is
    disabled.  MMX and SSE ISAs are handled separately.  */
@@ -241,6 +242,7 @@  along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
+#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
@@ -677,6 +679,19 @@  ix86_handle_option (struct gcc_options *opts,
 	}
       return true;
 
+    case OPT_mserialize:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
+	}
+      return true;
+
     case OPT_mavx5124fmaps:
       if (value)
 	{
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 13e3cb753e2..bfc8531f5d3 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -412,8 +412,9 @@  i[34567]86-*-*)
 		       avx512vnnivlintrin.h vaesintrin.h vpclmulqdqintrin.h
 		       avx512vpopcntdqvlintrin.h avx512bitalgintrin.h
 		       pconfigintrin.h wbnoinvdintrin.h movdirintrin.h
-		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h
-		       enqcmdintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h"
+		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h
+		       avx512bf16intrin.h enqcmdintrin.h serializeintrin.h
+		       avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h"
 	;;
 x86_64-*-*)
 	cpu_type=i386
@@ -445,8 +446,9 @@  x86_64-*-*)
 		       avx512vnnivlintrin.h vaesintrin.h vpclmulqdqintrin.h
 		       avx512vpopcntdqvlintrin.h avx512bitalgintrin.h
 		       pconfigintrin.h wbnoinvdintrin.h movdirintrin.h
-		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h
-		       enqcmdintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h"
+		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h
+		       avx512bf16intrin.h enqcmdintrin.h serializeintrin.h
+		       avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h"
 	;;
 ia64-*-*)
 	extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 34a7956d36a..d3fbde93400 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -122,6 +122,7 @@ 
 #define bit_AVX512VP2INTERSECT	(1 << 8)
 #define bit_IBT	(1 << 20)
 #define bit_PCONFIG	(1 << 18)
+#define bit_SERIALIZE	(1 << 14)
 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
 #define bit_BNDREGS     (1 << 3)
 #define bit_BNDCSR      (1 << 4)
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 130e12c8868..2ef44acb9b4 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -429,6 +429,7 @@  const char *host_detect_local_cpu (int argc, const char **argv)
   unsigned int has_waitpkg = 0;
   unsigned int has_cldemote = 0;
   unsigned int has_avx512bf16 = 0;
+  unsigned int has_serialize = 0;
 
   unsigned int has_ptwrite = 0;
 
@@ -534,6 +535,7 @@  const char *host_detect_local_cpu (int argc, const char **argv)
       has_avx5124vnniw = edx & bit_AVX5124VNNIW;
       has_avx5124fmaps = edx & bit_AVX5124FMAPS;
       has_avx512vp2intersect = edx & bit_AVX512VP2INTERSECT;
+      has_serialize = edx & bit_SERIALIZE;
 
       has_shstk = ecx & bit_SHSTK;
       has_pconfig = edx & bit_PCONFIG;
@@ -1161,6 +1163,7 @@  const char *host_detect_local_cpu (int argc, const char **argv)
       const char *enqcmd = has_enqcmd ? " -menqcmd" : " -mno-enqcmd";
       const char *waitpkg = has_waitpkg ? " -mwaitpkg" : " -mno-waitpkg";
       const char *cldemote = has_cldemote ? " -mcldemote" : " -mno-cldemote";
+      const char *serialize = has_serialize ? " -mserialize" : " -mno-serialize";
       const char *ptwrite = has_ptwrite ? " -mptwrite" : " -mno-ptwrite";
       const char *avx512bf16 = has_avx512bf16 ? " -mavx512bf16" : " -mno-avx512bf16";
 
@@ -1178,7 +1181,7 @@  const char *host_detect_local_cpu (int argc, const char **argv)
 			avx512vbmi2, avx512vnni, vaes, vpclmulqdq,
 			avx512bitalg, movdiri, movdir64b, waitpkg, cldemote,
 			ptwrite, avx512bf16, enqcmd, avx512vp2intersect,
-			NULL);
+			serialize, NULL);
     }
 
 done:
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 02e19539cca..197ac68944a 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -446,6 +446,9 @@  BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_PTWRITE, CODE_FOR_ptwritedi, "__b
 BDESC (0, OPTION_MASK_ISA2_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmd", IX86_BUILTIN_ENQCMD, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID)
 BDESC (0, OPTION_MASK_ISA2_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmds", IX86_BUILTIN_ENQCMDS, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID)
 
+/* SERIALIZE */
+BDESC (0, OPTION_MASK_ISA2_SERIALIZE, CODE_FOR_serialize, "__builtin_ia32_serialize", IX86_BUILTIN_SERIALIZE, UNKNOWN, (int) VOID_FTYPE_VOID)
+
 BDESC_END (SPECIAL_ARGS, ARGS)
 
 /* Builtins with variable number of arguments.  */
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 21ed7f4e99f..2ab5a813770 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -561,6 +561,8 @@  ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__WAITPKG__");
   if (isa_flag2 & OPTION_MASK_ISA2_CLDEMOTE)
     def_or_undef (parse_in, "__CLDEMOTE__");
+  if (isa_flag2 & OPTION_MASK_ISA2_SERIALIZE)
+    def_or_undef (parse_in, "__SERIALIZE__");
   if (isa_flag2 & OPTION_MASK_ISA2_PTWRITE)
     def_or_undef (parse_in, "__PTWRITE__");
   if (isa_flag2 & OPTION_MASK_ISA2_AVX512BF16)
diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
index e0be4932534..26a2ab72e37 100644
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@@ -205,7 +205,8 @@  static struct ix86_target_opts isa2_opts[] =
   { "-mcldemote",	OPTION_MASK_ISA2_CLDEMOTE },
   { "-mptwrite",	OPTION_MASK_ISA2_PTWRITE },
   { "-mavx512bf16",	OPTION_MASK_ISA2_AVX512BF16 },
-  { "-menqcmd",		OPTION_MASK_ISA2_ENQCMD }
+  { "-menqcmd",		OPTION_MASK_ISA2_ENQCMD },
+  { "-mserialize",	OPTION_MASK_ISA2_SERIALIZE }
 };
 static struct ix86_target_opts isa_opts[] =
 {
@@ -1017,6 +1018,7 @@  ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
     IX86_ATTR_ISA ("ptwrite",   OPT_mptwrite),
     IX86_ATTR_ISA ("avx512bf16",   OPT_mavx512bf16),
     IX86_ATTR_ISA ("enqcmd", OPT_menqcmd),
+    IX86_ATTR_ISA ("serialize", OPT_mserialize),
 
     /* enum options */
     IX86_ATTR_ENUM ("fpmath=",	OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index b8dddfc1594..997449c7efd 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -199,6 +199,8 @@  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_AVX512BF16_P(x)	TARGET_ISA2_AVX512BF16_P(x)
 #define TARGET_ENQCMD	TARGET_ISA2_ENQCMD
 #define TARGET_ENQCMD_P(x) TARGET_ISA2_ENQCMD_P(x)
+#define TARGET_SERIALIZE	TARGET_ISA2_SERIALIZE
+#define TARGET_SERIALIZE_P(x) TARGET_ISA2_SERIALIZE_P(x)
 
 #define TARGET_LP64	TARGET_ABI_64
 #define TARGET_LP64_P(x)	TARGET_ABI_64_P(x)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3051624d89f..44015b5b190 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -300,6 +300,9 @@ 
   ;; For ENQCMD and ENQCMDS support
   UNSPECV_ENQCMD
   UNSPECV_ENQCMDS
+
+  ;; For SERIALIZE support
+  UNSPECV_SERIALIZE
 ])
 
 ;; Constants to represent rounding modes in the ROUND instruction
@@ -21086,6 +21089,13 @@ 
   [(set_attr "type" "other")
    (set_attr "length" "3")])
 
+(define_insn "serialize"
+  [(unspec_volatile [(const_int 0)] UNSPECV_SERIALIZE)]
+  "TARGET_SERIALIZE"
+  "serialize"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
 (include "mmx.md")
 (include "sse.md")
 (include "sync.md")
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 185a1d0686b..9af05995b9d 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1107,3 +1107,7 @@  AVX512BF16 built-in functions and code generation.
 menqcmd
 Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save
 Support ENQCMD built-in functions and code generation.
+
+mserialize
+Target Report Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save
+Support SERIALIZE built-in functions and code generation.
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 12b118b0861..380e7f184f8 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -140,6 +140,8 @@ 
 
 #include <enqcmdintrin.h>
 
+#include <serializeintrin.h>
+
 #include <rdseedintrin.h>
 
 #include <prfchwintrin.h>
diff --git a/gcc/config/i386/serializeintrin.h b/gcc/config/i386/serializeintrin.h
new file mode 100644
index 00000000000..0c35b9ed1fa
--- /dev/null
+++ b/gcc/config/i386/serializeintrin.h
@@ -0,0 +1,49 @@ 
+/* Copyright (C) 2018 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+# error "Never use <serializeintrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _SERIALIZE_H_INCLUDED
+#define _SERIALIZE_H_INCLUDED
+
+#ifndef __SERIALIZE__
+#pragma GCC push_options
+#pragma GCC target("serialize")
+#define __DISABLE_SERIALIZE__
+#endif /* __SERIALIZE__ */
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_serialize (void)
+{
+  __builtin_ia32_serialize ();
+}
+
+#ifdef __DISABLE_SERIALIZE__
+#undef __DISABLE_SERIALIZE__
+#pragma GCC pop_options
+#endif /* __DISABLE_SERIALIZE__ */
+
+#endif /* _SERIALIZE_H_INCLUDED.  */
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 412750c1fc9..52105194e2d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1343,7 +1343,7 @@  See RS/6000 and PowerPC Options.
 -mshstk -mmanual-endbr -mforce-indirect-call  -mavx512vbmi2 -mavx512bf16 -menqcmd @gol
 -mvpclmulqdq  -mavx512bitalg  -mmovdiri  -mmovdir64b  -mavx512vpopcntdq @gol
 -mavx5124fmaps  -mavx512vnni  -mavx5124vnniw  -mprfchw  -mrdpid @gol
--mrdseed  -msgx -mavx512vp2intersect@gol
+-mrdseed  -msgx -mavx512vp2intersect -mserialize @gol
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops @gol
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg} @gol
 -mmemcpy-strategy=@var{strategy}  -mmemset-strategy=@var{strategy} @gol
@@ -29459,6 +29459,9 @@  preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @itemx -mcldemote
 @opindex mcldemote
+@need 200
+@itemx -mserialize
+@opindex mserialize
 These switches enable the use of instructions in the MMX, SSE,
 SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,
 AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
@@ -29467,9 +29470,9 @@  WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,
 3DNow!@:, enhanced 3DNow!@:, POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE,
 XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,
 GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
-ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, or CLDEMOTE
-extended instruction sets.  Each has a corresponding @option{-mno-} option to
-disable use of these instructions.
+ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE
+or CLDEMOTE extended instruction sets.  Each has a corresponding
+@option{-mno-} option to disable use of these instructions.
 
 These extensions are also available as built-in functions: see
 @ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C
index 95314157170..dd9e6849cf2 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@ 
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt  -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt  -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize" } */
 
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
    xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C
index 4912e7f40d1..1fdea53ae7a 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@ 
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize" } */
 
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
    xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/serialize-1.c b/gcc/testsuite/gcc.target/i386/serialize-1.c
new file mode 100644
index 00000000000..4fefb03d709
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/serialize-1.c
@@ -0,0 +1,12 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -mserialize" } */
+/* { dg-final { scan-assembler-times "serialize\[^-]"  1 } } */
+
+#include <x86intrin.h>
+
+void
+foo (void)
+{
+   _serialize ();
+   return;
+}
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c
index 6be531d88bf..0ab94b2692c 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@ 
    popcntintrin.h gfniintrin.h and mm_malloc.h are usable
    with -O -std=c89 -pedantic-errors.  */
 /* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize" } */
 
 #include <x86intrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index c2b192d72f6..472f7528a43 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize" } */
 /* { dg-add-options bind_pic_locally } */
 
 #include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 0d2b8b3cba0..396a4646e01 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize" } */
 /* { dg-add-options bind_pic_locally } */
 
 #include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index 9be7f2d5a58..581e16ba1d4 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -102,7 +102,7 @@ 
 
 
 #ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize")
 #endif
 
 /* Following intrinsics require immediate arguments.  They
@@ -219,7 +219,7 @@  test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
 
 /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
 #ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect")
+#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize")
 #endif
 #include <immintrin.h>
 test_1 (_cvtss_sh, unsigned short, float, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index e98c7693ef7..80891393336 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -697,6 +697,6 @@ 
 #define __builtin_ia32_vpclmulqdq_v2di(A, B, C)  __builtin_ia32_vpclmulqdq_v2di(A, B, 1) 
 #define __builtin_ia32_vpclmulqdq_v8di(A, B, C)  __builtin_ia32_vpclmulqdq_v8di(A, B, 1) 
 
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize")
 
 #include <x86intrin.h>
-- 
2.18.1