[v2,ARM,5/5x] : MVE ACLE load intrinsics which load a byte, halfword, or word from memory.

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  • [v2,ARM,5/5x] : MVE ACLE load intrinsics which load a byte, halfword, or word from memory.
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Commit Message

Srinath Parvathaneni March 18, 2020, 5:17 p.m.
Hello Kyrill,

Following patch is the rebased version of v1.
(version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-November/534352.html

####

Hello,

This patch supports the following MVE ACLE load intrinsics which load a byte, halfword,
or word from memory.
vld1q_s8, vld1q_s32, vld1q_s16, vld1q_u8, vld1q_u32, vld1q_u16, vldrhq_gather_offset_s32,
vldrhq_gather_offset_s16, vldrhq_gather_offset_u32, vldrhq_gather_offset_u16,
vldrhq_gather_offset_z_s32, vldrhq_gather_offset_z_s16, vldrhq_gather_offset_z_u32,
vldrhq_gather_offset_z_u16, vldrhq_gather_shifted_offset_s32,vldrwq_f32, vldrwq_z_f32,
vldrhq_gather_shifted_offset_s16, vldrhq_gather_shifted_offset_u32,
vldrhq_gather_shifted_offset_u16, vldrhq_gather_shifted_offset_z_s32,
vldrhq_gather_shifted_offset_z_s16, vldrhq_gather_shifted_offset_z_u32,
vldrhq_gather_shifted_offset_z_u16, vldrhq_s32, vldrhq_s16, vldrhq_u32, vldrhq_u16,
vldrhq_z_s32, vldrhq_z_s16, vldrhq_z_u32, vldrhq_z_u16, vldrwq_s32, vldrwq_u32,
vldrwq_z_s32, vldrwq_z_u32, vld1q_f32, vld1q_f16, vldrhq_f16, vldrhq_z_f16.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1]  https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

Regression tested on arm-none-eabi and found no regressions.

Ok for trunk?

Thanks,
Srinath.

gcc/ChangeLog:

2019-11-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Mihail Ionescu  <mihail.ionescu@arm.com>
	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vld1q_s8): Define macro.
	(vld1q_s32): Likewise.
	(vld1q_s16): Likewise.
	(vld1q_u8): Likewise.
	(vld1q_u32): Likewise.
	(vld1q_u16): Likewise.
	(vldrhq_gather_offset_s32): Likewise.
	(vldrhq_gather_offset_s16): Likewise.
	(vldrhq_gather_offset_u32): Likewise.
	(vldrhq_gather_offset_u16): Likewise.
	(vldrhq_gather_offset_z_s32): Likewise.
	(vldrhq_gather_offset_z_s16): Likewise.
	(vldrhq_gather_offset_z_u32): Likewise.
	(vldrhq_gather_offset_z_u16): Likewise.
	(vldrhq_gather_shifted_offset_s32): Likewise.
	(vldrhq_gather_shifted_offset_s16): Likewise.
	(vldrhq_gather_shifted_offset_u32): Likewise.
	(vldrhq_gather_shifted_offset_u16): Likewise.
	(vldrhq_gather_shifted_offset_z_s32): Likewise.
	(vldrhq_gather_shifted_offset_z_s16): Likewise.
	(vldrhq_gather_shifted_offset_z_u32): Likewise.
	(vldrhq_gather_shifted_offset_z_u16): Likewise.
	(vldrhq_s32): Likewise.
	(vldrhq_s16): Likewise.
	(vldrhq_u32): Likewise.
	(vldrhq_u16): Likewise.
	(vldrhq_z_s32): Likewise.
	(vldrhq_z_s16): Likewise.
	(vldrhq_z_u32): Likewise.
	(vldrhq_z_u16): Likewise.
	(vldrwq_s32): Likewise.
	(vldrwq_u32): Likewise.
	(vldrwq_z_s32): Likewise.
	(vldrwq_z_u32): Likewise.
	(vld1q_f32): Likewise.
	(vld1q_f16): Likewise.
	(vldrhq_f16): Likewise.
	(vldrhq_z_f16): Likewise.
	(vldrwq_f32): Likewise.
	(vldrwq_z_f32): Likewise.
	(__arm_vld1q_s8): Define intrinsic.
	(__arm_vld1q_s32): Likewise.
	(__arm_vld1q_s16): Likewise.
	(__arm_vld1q_u8): Likewise.
	(__arm_vld1q_u32): Likewise.
	(__arm_vld1q_u16): Likewise.
	(__arm_vldrhq_gather_offset_s32): Likewise.
	(__arm_vldrhq_gather_offset_s16): Likewise.
	(__arm_vldrhq_gather_offset_u32): Likewise.
	(__arm_vldrhq_gather_offset_u16): Likewise.
	(__arm_vldrhq_gather_offset_z_s32): Likewise.
	(__arm_vldrhq_gather_offset_z_s16): Likewise.
	(__arm_vldrhq_gather_offset_z_u32): Likewise.
	(__arm_vldrhq_gather_offset_z_u16): Likewise.
	(__arm_vldrhq_gather_shifted_offset_s32): Likewise.
	(__arm_vldrhq_gather_shifted_offset_s16): Likewise.
	(__arm_vldrhq_gather_shifted_offset_u32): Likewise.
	(__arm_vldrhq_gather_shifted_offset_u16): Likewise.
	(__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
	(__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
	(__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
	(__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
	(__arm_vldrhq_s32): Likewise.
	(__arm_vldrhq_s16): Likewise.
	(__arm_vldrhq_u32): Likewise.
	(__arm_vldrhq_u16): Likewise.
	(__arm_vldrhq_z_s32): Likewise.
	(__arm_vldrhq_z_s16): Likewise.
	(__arm_vldrhq_z_u32): Likewise.
	(__arm_vldrhq_z_u16): Likewise.
	(__arm_vldrwq_s32): Likewise.
	(__arm_vldrwq_u32): Likewise.
	(__arm_vldrwq_z_s32): Likewise.
	(__arm_vldrwq_z_u32): Likewise.
	(__arm_vld1q_f32): Likewise.
	(__arm_vld1q_f16): Likewise.
	(__arm_vldrwq_f32): Likewise.
	(__arm_vldrwq_z_f32): Likewise.
	(__arm_vldrhq_z_f16): Likewise.
	(__arm_vldrhq_f16): Likewise.
	(vld1q): Define polymorphic variant.
	(vldrhq_gather_offset): Likewise.
	(vldrhq_gather_offset_z): Likewise.
	(vldrhq_gather_shifted_offset): Likewise.
	(vldrhq_gather_shifted_offset_z): Likewise.
	* config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
	(LDRS): Likewise.
	(LDRU_Z): Likewise.
	(LDRS_Z): Likewise.
	(LDRGU_Z): Likewise.
	(LDRGU): Likewise.
	(LDRGS_Z): Likewise.
	(LDRGS): Likewise.
	* config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
	(V_sz_elem1): Likewise.
	(VLD1Q): Define iterator.
	(VLDRHGOQ): Likewise.
	(VLDRHGSOQ): Likewise.
	(VLDRHQ): Likewise.
	(VLDRWQ): Likewise.
	(mve_vldrhq_fv8hf): Define RTL pattern.
	(mve_vldrhq_gather_offset_<supf><mode>): Likewise
	(mve_vldrhq_gather_offset_z_<supf><mode>): Likewise
	(mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise
	(mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise
	(mve_vldrhq_<supf><mode>): Likewise
	(mve_vldrhq_z_fv8hf): Likewise
	(mve_vldrhq_z_<supf><mode>): Likewise
	(mve_vldrwq_fv4sf): Likewise
	(mve_vldrwq_<supf>v4si): Likewise
	(mve_vldrwq_z_fv4sf): Likewise
	(mve_vldrwq_z_<supf>v4si): Likewise
	(mve_vld1q_f<mode>): Define RTL expand pattern.
	(mve_vld1q_<supf><mode>): Likewise

gcc/testsuite/ChangeLog:

2019-11-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Mihail Ionescu  <mihail.ionescu@arm.com>
	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.


###############     Attachment also inlined for ease of reply    ###############

Comments

Kyrylo Tkachov March 18, 2020, 6:49 p.m. | #1
Hi Srinath,

> -----Original Message-----

> From: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>

> Sent: 18 March 2020 17:18

> To: gcc-patches@gcc.gnu.org

> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>

> Subject: [PATCH v2][ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a

> byte, halfword, or word from memory.

> 

> Hello Kyrill,

> 

> Following patch is the rebased version of v1.

> (version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-

> November/534352.html

> 

> ####

> 

> Hello,

> 

> This patch supports the following MVE ACLE load intrinsics which load a byte,

> halfword,

> or word from memory.

> vld1q_s8, vld1q_s32, vld1q_s16, vld1q_u8, vld1q_u32, vld1q_u16,

> vldrhq_gather_offset_s32,

> vldrhq_gather_offset_s16, vldrhq_gather_offset_u32,

> vldrhq_gather_offset_u16,

> vldrhq_gather_offset_z_s32, vldrhq_gather_offset_z_s16,

> vldrhq_gather_offset_z_u32,

> vldrhq_gather_offset_z_u16, vldrhq_gather_shifted_offset_s32,vldrwq_f32,

> vldrwq_z_f32,

> vldrhq_gather_shifted_offset_s16, vldrhq_gather_shifted_offset_u32,

> vldrhq_gather_shifted_offset_u16, vldrhq_gather_shifted_offset_z_s32,

> vldrhq_gather_shifted_offset_z_s16, vldrhq_gather_shifted_offset_z_u32,

> vldrhq_gather_shifted_offset_z_u16, vldrhq_s32, vldrhq_s16, vldrhq_u32,

> vldrhq_u16,

> vldrhq_z_s32, vldrhq_z_s16, vldrhq_z_u32, vldrhq_z_u16, vldrwq_s32,

> vldrwq_u32,

> vldrwq_z_s32, vldrwq_z_u32, vld1q_f32, vld1q_f16, vldrhq_f16,

> vldrhq_z_f16.

> 

> Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more

> details.

> [1]  https://developer.arm.com/architectures/instruction-sets/simd-

> isas/helium/mve-intrinsics

> 

> Regression tested on arm-none-eabi and found no regressions.

> 

> Ok for trunk?


Thanks, I've pushed this patch to master.
Kyrill

> 

> Thanks,

> Srinath.

> 

> gcc/ChangeLog:

> 

> 2019-11-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 	    Mihail Ionescu  <mihail.ionescu@arm.com>

> 	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

> 

> 	* config/arm/arm_mve.h (vld1q_s8): Define macro.

> 	(vld1q_s32): Likewise.

> 	(vld1q_s16): Likewise.

> 	(vld1q_u8): Likewise.

> 	(vld1q_u32): Likewise.

> 	(vld1q_u16): Likewise.

> 	(vldrhq_gather_offset_s32): Likewise.

> 	(vldrhq_gather_offset_s16): Likewise.

> 	(vldrhq_gather_offset_u32): Likewise.

> 	(vldrhq_gather_offset_u16): Likewise.

> 	(vldrhq_gather_offset_z_s32): Likewise.

> 	(vldrhq_gather_offset_z_s16): Likewise.

> 	(vldrhq_gather_offset_z_u32): Likewise.

> 	(vldrhq_gather_offset_z_u16): Likewise.

> 	(vldrhq_gather_shifted_offset_s32): Likewise.

> 	(vldrhq_gather_shifted_offset_s16): Likewise.

> 	(vldrhq_gather_shifted_offset_u32): Likewise.

> 	(vldrhq_gather_shifted_offset_u16): Likewise.

> 	(vldrhq_gather_shifted_offset_z_s32): Likewise.

> 	(vldrhq_gather_shifted_offset_z_s16): Likewise.

> 	(vldrhq_gather_shifted_offset_z_u32): Likewise.

> 	(vldrhq_gather_shifted_offset_z_u16): Likewise.

> 	(vldrhq_s32): Likewise.

> 	(vldrhq_s16): Likewise.

> 	(vldrhq_u32): Likewise.

> 	(vldrhq_u16): Likewise.

> 	(vldrhq_z_s32): Likewise.

> 	(vldrhq_z_s16): Likewise.

> 	(vldrhq_z_u32): Likewise.

> 	(vldrhq_z_u16): Likewise.

> 	(vldrwq_s32): Likewise.

> 	(vldrwq_u32): Likewise.

> 	(vldrwq_z_s32): Likewise.

> 	(vldrwq_z_u32): Likewise.

> 	(vld1q_f32): Likewise.

> 	(vld1q_f16): Likewise.

> 	(vldrhq_f16): Likewise.

> 	(vldrhq_z_f16): Likewise.

> 	(vldrwq_f32): Likewise.

> 	(vldrwq_z_f32): Likewise.

> 	(__arm_vld1q_s8): Define intrinsic.

> 	(__arm_vld1q_s32): Likewise.

> 	(__arm_vld1q_s16): Likewise.

> 	(__arm_vld1q_u8): Likewise.

> 	(__arm_vld1q_u32): Likewise.

> 	(__arm_vld1q_u16): Likewise.

> 	(__arm_vldrhq_gather_offset_s32): Likewise.

> 	(__arm_vldrhq_gather_offset_s16): Likewise.

> 	(__arm_vldrhq_gather_offset_u32): Likewise.

> 	(__arm_vldrhq_gather_offset_u16): Likewise.

> 	(__arm_vldrhq_gather_offset_z_s32): Likewise.

> 	(__arm_vldrhq_gather_offset_z_s16): Likewise.

> 	(__arm_vldrhq_gather_offset_z_u32): Likewise.

> 	(__arm_vldrhq_gather_offset_z_u16): Likewise.

> 	(__arm_vldrhq_gather_shifted_offset_s32): Likewise.

> 	(__arm_vldrhq_gather_shifted_offset_s16): Likewise.

> 	(__arm_vldrhq_gather_shifted_offset_u32): Likewise.

> 	(__arm_vldrhq_gather_shifted_offset_u16): Likewise.

> 	(__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.

> 	(__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.

> 	(__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.

> 	(__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.

> 	(__arm_vldrhq_s32): Likewise.

> 	(__arm_vldrhq_s16): Likewise.

> 	(__arm_vldrhq_u32): Likewise.

> 	(__arm_vldrhq_u16): Likewise.

> 	(__arm_vldrhq_z_s32): Likewise.

> 	(__arm_vldrhq_z_s16): Likewise.

> 	(__arm_vldrhq_z_u32): Likewise.

> 	(__arm_vldrhq_z_u16): Likewise.

> 	(__arm_vldrwq_s32): Likewise.

> 	(__arm_vldrwq_u32): Likewise.

> 	(__arm_vldrwq_z_s32): Likewise.

> 	(__arm_vldrwq_z_u32): Likewise.

> 	(__arm_vld1q_f32): Likewise.

> 	(__arm_vld1q_f16): Likewise.

> 	(__arm_vldrwq_f32): Likewise.

> 	(__arm_vldrwq_z_f32): Likewise.

> 	(__arm_vldrhq_z_f16): Likewise.

> 	(__arm_vldrhq_f16): Likewise.

> 	(vld1q): Define polymorphic variant.

> 	(vldrhq_gather_offset): Likewise.

> 	(vldrhq_gather_offset_z): Likewise.

> 	(vldrhq_gather_shifted_offset): Likewise.

> 	(vldrhq_gather_shifted_offset_z): Likewise.

> 	* config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.

> 	(LDRS): Likewise.

> 	(LDRU_Z): Likewise.

> 	(LDRS_Z): Likewise.

> 	(LDRGU_Z): Likewise.

> 	(LDRGU): Likewise.

> 	(LDRGS_Z): Likewise.

> 	(LDRGS): Likewise.

> 	* config/arm/mve.md (MVE_H_ELEM): Define mode iterator.

> 	(V_sz_elem1): Likewise.

> 	(VLD1Q): Define iterator.

> 	(VLDRHGOQ): Likewise.

> 	(VLDRHGSOQ): Likewise.

> 	(VLDRHQ): Likewise.

> 	(VLDRWQ): Likewise.

> 	(mve_vldrhq_fv8hf): Define RTL pattern.

> 	(mve_vldrhq_gather_offset_<supf><mode>): Likewise

> 	(mve_vldrhq_gather_offset_z_<supf><mode>): Likewise

> 	(mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise

> 	(mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise

> 	(mve_vldrhq_<supf><mode>): Likewise

> 	(mve_vldrhq_z_fv8hf): Likewise

> 	(mve_vldrhq_z_<supf><mode>): Likewise

> 	(mve_vldrwq_fv4sf): Likewise

> 	(mve_vldrwq_<supf>v4si): Likewise

> 	(mve_vldrwq_z_fv4sf): Likewise

> 	(mve_vldrwq_z_<supf>v4si): Likewise

> 	(mve_vld1q_f<mode>): Define RTL expand pattern.

> 	(mve_vld1q_<supf><mode>): Likewise

> 

> gcc/testsuite/ChangeLog:

> 

> 2019-11-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 	    Mihail Ionescu  <mihail.ionescu@arm.com>

> 	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

> 

> 	* gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test.

> 	* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c:

> Likewise.

> 	*

> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c:

> Likewise.

> 	*

> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c:

> Likewise.

> 	*

> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c:

> Likewise.

> 	*

> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.

> 

> 

> ###############     Attachment also inlined for ease of reply

> ###############

> 

> 

> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h

> index

> 4570a0b16c37b11471a61f4b53686945063b4a55..9991e25c8d642c8109ab9ce

> 9f48a818508d7801c 100644

> --- a/gcc/config/arm/arm_mve.h

> +++ b/gcc/config/arm/arm_mve.h

> @@ -1758,6 +1758,46 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;

>  #define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p)

>  #define vldrwq_gather_base_z_u32(__addr,  __offset, __p)

> __arm_vldrwq_gather_base_z_u32(__addr,  __offset, __p)

>  #define vldrwq_gather_base_z_s32(__addr,  __offset, __p)

> __arm_vldrwq_gather_base_z_s32(__addr,  __offset, __p)

> +#define vld1q_s8(__base) __arm_vld1q_s8(__base)

> +#define vld1q_s32(__base) __arm_vld1q_s32(__base)

> +#define vld1q_s16(__base) __arm_vld1q_s16(__base)

> +#define vld1q_u8(__base) __arm_vld1q_u8(__base)

> +#define vld1q_u32(__base) __arm_vld1q_u32(__base)

> +#define vld1q_u16(__base) __arm_vld1q_u16(__base)

> +#define vldrhq_gather_offset_s32(__base, __offset)

> __arm_vldrhq_gather_offset_s32(__base, __offset)

> +#define vldrhq_gather_offset_s16(__base, __offset)

> __arm_vldrhq_gather_offset_s16(__base, __offset)

> +#define vldrhq_gather_offset_u32(__base, __offset)

> __arm_vldrhq_gather_offset_u32(__base, __offset)

> +#define vldrhq_gather_offset_u16(__base, __offset)

> __arm_vldrhq_gather_offset_u16(__base, __offset)

> +#define vldrhq_gather_offset_z_s32(__base, __offset, __p)

> __arm_vldrhq_gather_offset_z_s32(__base, __offset, __p)

> +#define vldrhq_gather_offset_z_s16(__base, __offset, __p)

> __arm_vldrhq_gather_offset_z_s16(__base, __offset, __p)

> +#define vldrhq_gather_offset_z_u32(__base, __offset, __p)

> __arm_vldrhq_gather_offset_z_u32(__base, __offset, __p)

> +#define vldrhq_gather_offset_z_u16(__base, __offset, __p)

> __arm_vldrhq_gather_offset_z_u16(__base, __offset, __p)

> +#define vldrhq_gather_shifted_offset_s32(__base, __offset)

> __arm_vldrhq_gather_shifted_offset_s32(__base, __offset)

> +#define vldrhq_gather_shifted_offset_s16(__base, __offset)

> __arm_vldrhq_gather_shifted_offset_s16(__base, __offset)

> +#define vldrhq_gather_shifted_offset_u32(__base, __offset)

> __arm_vldrhq_gather_shifted_offset_u32(__base, __offset)

> +#define vldrhq_gather_shifted_offset_u16(__base, __offset)

> __arm_vldrhq_gather_shifted_offset_u16(__base, __offset)

> +#define vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p)

> __arm_vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p)

> +#define vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p)

> __arm_vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p)

> +#define vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p)

> __arm_vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p)

> +#define vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p)

> __arm_vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p)

> +#define vldrhq_s32(__base) __arm_vldrhq_s32(__base)

> +#define vldrhq_s16(__base) __arm_vldrhq_s16(__base)

> +#define vldrhq_u32(__base) __arm_vldrhq_u32(__base)

> +#define vldrhq_u16(__base) __arm_vldrhq_u16(__base)

> +#define vldrhq_z_s32(__base, __p) __arm_vldrhq_z_s32(__base, __p)

> +#define vldrhq_z_s16(__base, __p) __arm_vldrhq_z_s16(__base, __p)

> +#define vldrhq_z_u32(__base, __p) __arm_vldrhq_z_u32(__base, __p)

> +#define vldrhq_z_u16(__base, __p) __arm_vldrhq_z_u16(__base, __p)

> +#define vldrwq_s32(__base) __arm_vldrwq_s32(__base)

> +#define vldrwq_u32(__base) __arm_vldrwq_u32(__base)

> +#define vldrwq_z_s32(__base, __p) __arm_vldrwq_z_s32(__base, __p)

> +#define vldrwq_z_u32(__base, __p) __arm_vldrwq_z_u32(__base, __p)

> +#define vld1q_f32(__base) __arm_vld1q_f32(__base)

> +#define vld1q_f16(__base) __arm_vld1q_f16(__base)

> +#define vldrhq_f16(__base) __arm_vldrhq_f16(__base)

> +#define vldrhq_z_f16(__base, __p) __arm_vldrhq_z_f16(__base, __p)

> +#define vldrwq_f32(__base) __arm_vldrwq_f32(__base)

> +#define vldrwq_z_f32(__base, __p) __arm_vldrwq_z_f32(__base, __p)

>  #endif

> 

>  __extension__ extern __inline void

> @@ -11443,6 +11483,245 @@ __arm_vldrwq_gather_base_z_u32

> (uint32x4_t __addr, const int __offset, mve_pred1

>    return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p);

>  }

> 

> +__extension__ extern __inline int8x16_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vld1q_s8 (int8_t const * __base)

> +{

> +  return __builtin_mve_vld1q_sv16qi ((__builtin_neon_qi *) __base);

> +}

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vld1q_s32 (int32_t const * __base)

> +{

> +  return __builtin_mve_vld1q_sv4si ((__builtin_neon_si *) __base);

> +}

> +

> +__extension__ extern __inline int16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vld1q_s16 (int16_t const * __base)

> +{

> +  return __builtin_mve_vld1q_sv8hi ((__builtin_neon_hi *) __base);

> +}

> +

> +__extension__ extern __inline uint8x16_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vld1q_u8 (uint8_t const * __base)

> +{

> +  return __builtin_mve_vld1q_uv16qi ((__builtin_neon_qi *) __base);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vld1q_u32 (uint32_t const * __base)

> +{

> +  return __builtin_mve_vld1q_uv4si ((__builtin_neon_si *) __base);

> +}

> +

> +__extension__ extern __inline uint16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vld1q_u16 (uint16_t const * __base)

> +{

> +  return __builtin_mve_vld1q_uv8hi ((__builtin_neon_hi *) __base);

> +}

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_offset_s32 (int16_t const * __base, uint32x4_t

> __offset)

> +{

> +  return __builtin_mve_vldrhq_gather_offset_sv4si ((__builtin_neon_hi *)

> __base, __offset);

> +}

> +

> +__extension__ extern __inline int16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_offset_s16 (int16_t const * __base, uint16x8_t

> __offset)

> +{

> +  return __builtin_mve_vldrhq_gather_offset_sv8hi ((__builtin_neon_hi *)

> __base, __offset);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_offset_u32 (uint16_t const * __base, uint32x4_t

> __offset)

> +{

> +  return __builtin_mve_vldrhq_gather_offset_uv4si ((__builtin_neon_hi *)

> __base, __offset);

> +}

> +

> +__extension__ extern __inline uint16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_offset_u16 (uint16_t const * __base, uint16x8_t

> __offset)

> +{

> +  return __builtin_mve_vldrhq_gather_offset_uv8hi ((__builtin_neon_hi *)

> __base, __offset);

> +}

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_offset_z_s32 (int16_t const * __base, uint32x4_t

> __offset, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_gather_offset_z_sv4si ((__builtin_neon_hi *)

> __base, __offset, __p);

> +}

> +

> +__extension__ extern __inline int16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_offset_z_s16 (int16_t const * __base, uint16x8_t

> __offset, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_gather_offset_z_sv8hi ((__builtin_neon_hi *)

> __base, __offset, __p);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_offset_z_u32 (uint16_t const * __base, uint32x4_t

> __offset, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_gather_offset_z_uv4si ((__builtin_neon_hi *)

> __base, __offset, __p);

> +}

> +

> +__extension__ extern __inline uint16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_offset_z_u16 (uint16_t const * __base, uint16x8_t

> __offset, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_gather_offset_z_uv8hi ((__builtin_neon_hi *)

> __base, __offset, __p);

> +}

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_shifted_offset_s32 (int16_t const * __base,

> uint32x4_t __offset)

> +{

> +  return __builtin_mve_vldrhq_gather_shifted_offset_sv4si

> ((__builtin_neon_hi *) __base, __offset);

> +}

> +

> +__extension__ extern __inline int16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_shifted_offset_s16 (int16_t const * __base,

> uint16x8_t __offset)

> +{

> +  return __builtin_mve_vldrhq_gather_shifted_offset_sv8hi

> ((__builtin_neon_hi *) __base, __offset);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_shifted_offset_u32 (uint16_t const * __base,

> uint32x4_t __offset)

> +{

> +  return __builtin_mve_vldrhq_gather_shifted_offset_uv4si

> ((__builtin_neon_hi *) __base, __offset);

> +}

> +

> +__extension__ extern __inline uint16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_shifted_offset_u16 (uint16_t const * __base,

> uint16x8_t __offset)

> +{

> +  return __builtin_mve_vldrhq_gather_shifted_offset_uv8hi

> ((__builtin_neon_hi *) __base, __offset);

> +}

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_shifted_offset_z_s32 (int16_t const * __base,

> uint32x4_t __offset, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_gather_shifted_offset_z_sv4si

> ((__builtin_neon_hi *) __base, __offset, __p);

> +}

> +

> +__extension__ extern __inline int16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_shifted_offset_z_s16 (int16_t const * __base,

> uint16x8_t __offset, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_gather_shifted_offset_z_sv8hi

> ((__builtin_neon_hi *) __base, __offset, __p);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_shifted_offset_z_u32 (uint16_t const * __base,

> uint32x4_t __offset, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_gather_shifted_offset_z_uv4si

> ((__builtin_neon_hi *) __base, __offset, __p);

> +}

> +

> +__extension__ extern __inline uint16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_gather_shifted_offset_z_u16 (uint16_t const * __base,

> uint16x8_t __offset, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_gather_shifted_offset_z_uv8hi

> ((__builtin_neon_hi *) __base, __offset, __p);

> +}

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_s32 (int16_t const * __base)

> +{

> +  return __builtin_mve_vldrhq_sv4si ((__builtin_neon_hi *) __base);

> +}

> +

> +__extension__ extern __inline int16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_s16 (int16_t const * __base)

> +{

> +  return __builtin_mve_vldrhq_sv8hi ((__builtin_neon_hi *) __base);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_u32 (uint16_t const * __base)

> +{

> +  return __builtin_mve_vldrhq_uv4si ((__builtin_neon_hi *) __base);

> +}

> +

> +__extension__ extern __inline uint16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_u16 (uint16_t const * __base)

> +{

> +  return __builtin_mve_vldrhq_uv8hi ((__builtin_neon_hi *) __base);

> +}

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_z_s32 (int16_t const * __base, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_z_sv4si ((__builtin_neon_hi *) __base, __p);

> +}

> +

> +__extension__ extern __inline int16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_z_s16 (int16_t const * __base, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_z_sv8hi ((__builtin_neon_hi *) __base, __p);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_z_u32 (uint16_t const * __base, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_z_uv4si ((__builtin_neon_hi *) __base, __p);

> +}

> +

> +__extension__ extern __inline uint16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_z_u16 (uint16_t const * __base, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_z_uv8hi ((__builtin_neon_hi *) __base, __p);

> +}

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrwq_s32 (int32_t const * __base)

> +{

> +  return __builtin_mve_vldrwq_sv4si ((__builtin_neon_si *) __base);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrwq_u32 (uint32_t const * __base)

> +{

> +  return __builtin_mve_vldrwq_uv4si ((__builtin_neon_si *) __base);

> +}

> +

> +

> +__extension__ extern __inline int32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrwq_z_s32 (int32_t const * __base, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrwq_z_sv4si ((__builtin_neon_si *) __base, __p);

> +}

> +

> +__extension__ extern __inline uint32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrwq_z_u32 (uint32_t const * __base, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrwq_z_uv4si ((__builtin_neon_si *) __base, __p);

> +}

> +

>  #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */

> 

>  __extension__ extern __inline void

> @@ -13585,6 +13864,47 @@ __arm_vsubq_m_n_f16 (float16x8_t __inactive,

> float16x8_t __a, float16_t __b, mve

>    return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p);

>  }

> 

> +__extension__ extern __inline float32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vld1q_f32 (float32_t const * __base)

> +{

> +  return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base);

> +}

> +

> +__extension__ extern __inline float16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vld1q_f16 (float16_t const * __base)

> +{

> +  return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base);

> +}

> +

> +__extension__ extern __inline float32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrwq_f32 (float32_t const * __base)

> +{

> +  return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base);

> +}

> +

> +__extension__ extern __inline float32x4_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p);

> +}

> +

> +__extension__ extern __inline float16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p)

> +{

> +  return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p);

> +}

> +

> +__extension__ extern __inline float16x8_t

> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrhq_f16 (float16_t const * __base)

> +{

> +  return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base);

> +}

>  #endif

> 

>  enum {

> @@ -16052,6 +16372,18 @@ extern void *__ARM_undef;

>    int

> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_

> mve_type_float16x8_t]: __arm_vorrq_m_f16 (__ARM_mve_coerce(__p0,

> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),

> __ARM_mve_coerce(__p2, float16x8_t), p3), \

>    int

> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_

> mve_type_float32x4_t]: __arm_vorrq_m_f32 (__ARM_mve_coerce(__p0,

> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),

> __ARM_mve_coerce(__p2, float32x4_t), p3));})

> 

> +#define vld1q(p0) __arm_vld1q(p0)

> +#define __arm_vld1q(p0) ({ __typeof(p0) __p0 = (p0); \

> +  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \

> +  int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8

> (__ARM_mve_coerce(__p0, int8_t const *)), \

> +  int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16

> (__ARM_mve_coerce(__p0, int16_t const *)), \

> +  int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32

> (__ARM_mve_coerce(__p0, int32_t const *)), \

> +  int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8

> (__ARM_mve_coerce(__p0, uint8_t const *)), \

> +  int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16

> (__ARM_mve_coerce(__p0, uint16_t const *)), \

> +  int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32

> (__ARM_mve_coerce(__p0, uint32_t const *)), \

> +  int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_f16

> (__ARM_mve_coerce(__p0, float16_t const *)), \

> +  int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_f32

> (__ARM_mve_coerce(__p0, float32_t const *)));})

> +

>  #else /* MVE Integer.  */

> 

>  #define vst4q(p0,p1) __arm_vst4q(p0,p1)

> @@ -18148,6 +18480,52 @@ extern void *__ARM_undef;

>    int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32

> (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \

>    int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32

> (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})

> 

> +#define vld1q(p0) __arm_vld1q(p0)

> +#define __arm_vld1q(p0) ({ __typeof(p0) __p0 = (p0); \

> +  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \

> +  int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8

> (__ARM_mve_coerce(__p0, int8_t const *)), \

> +  int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16

> (__ARM_mve_coerce(__p0, int16_t const *)), \

> +  int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32

> (__ARM_mve_coerce(__p0, int32_t const *)), \

> +  int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8

> (__ARM_mve_coerce(__p0, uint8_t const *)), \

> +  int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16

> (__ARM_mve_coerce(__p0, uint16_t const *)), \

> +  int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32

> (__ARM_mve_coerce(__p0, uint32_t const *)));})

> +

> +#define vldrhq_gather_offset(p0,p1) __arm_vldrhq_gather_offset(p0,p1)

> +#define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \

> +  __typeof(p1) __p1 = (p1); \

> +  _Generic( (int

> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \

> +  int

> (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce(__p0, int16_t const

> *), __ARM_mve_coerce(__p1, uint16x8_t)), \

> +  int

> (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce(__p0, int16_t const

> *), __ARM_mve_coerce(__p1, uint32x4_t)), \

> +  int

> (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const

> *), __ARM_mve_coerce(__p1, uint16x8_t)), \

> +  int

> (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const

> *), __ARM_mve_coerce(__p1, uint32x4_t)));})

> +

> +#define vldrhq_gather_offset_z(p0,p1,p2)

> __arm_vldrhq_gather_offset_z(p0,p1,p2)

> +#define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 =

> (p0); \

> +  __typeof(p1) __p1 = (p1); \

> +  _Generic( (int

> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \

> +  int

> (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const

> *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \

> +  int

> (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const

> *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \

> +  int

> (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t

> const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \

> +  int

> (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t

> const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})

> +

> +#define vldrhq_gather_shifted_offset(p0,p1)

> __arm_vldrhq_gather_shifted_offset(p0,p1)

> +#define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 =

> (p0); \

> +  __typeof(p1) __p1 = (p1); \

> +  _Generic( (int

> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \

> +  int

> (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t

> const *), __ARM_mve_coerce(__p1, uint16x8_t)), \

> +  int

> (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t

> const *), __ARM_mve_coerce(__p1, uint32x4_t)), \

> +  int

> (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce(__p0,

> uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \

> +  int

> (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce(__p0,

> uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));})

> +

> +#define vldrhq_gather_shifted_offset_z(p0,p1,p2)

> __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2)

> +#define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0)

> __p0 = (p0); \

> +  __typeof(p1) __p1 = (p1); \

> +  _Generic( (int

> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \

> +  int

> (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce(__p0,

> int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \

> +  int

> (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0,

> int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \

> +  int

> (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce(__p0,

> uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \

> +  int

> (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0,

> uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})

> +

>  #endif /* MVE Integer.  */

> 

>  #define vldrbq_gather_offset_z(p0,p1,p2)

> __arm_vldrbq_gather_offset_z(p0,p1,p2)

> diff --git a/gcc/config/arm/arm_mve_builtins.def

> b/gcc/config/arm/arm_mve_builtins.def

> index

> 0f466e4cec295c1d791d675b52ff15e364d7016e..bafc953a5e5108caa9595ea9

> 189ed1182da2c692 100644

> --- a/gcc/config/arm/arm_mve_builtins.def

> +++ b/gcc/config/arm/arm_mve_builtins.def

> @@ -709,3 +709,26 @@ VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi,

> v8hi, v4si)

>  VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si)

>  VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si)

>  VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si)

> +VAR3 (LDRU, vld1q_u, v16qi, v8hi, v4si)

> +VAR3 (LDRS, vld1q_s, v16qi, v8hi, v4si)

> +VAR2 (LDRU_Z, vldrhq_z_u, v8hi, v4si)

> +VAR2 (LDRU, vldrhq_u, v8hi, v4si)

> +VAR2 (LDRS_Z, vldrhq_z_s, v8hi, v4si)

> +VAR2 (LDRS, vldrhq_s, v8hi, v4si)

> +VAR2 (LDRS, vld1q_f, v8hf, v4sf)

> +VAR2 (LDRGU_Z, vldrhq_gather_shifted_offset_z_u, v8hi, v4si)

> +VAR2 (LDRGU_Z, vldrhq_gather_offset_z_u, v8hi, v4si)

> +VAR2 (LDRGU, vldrhq_gather_shifted_offset_u, v8hi, v4si)

> +VAR2 (LDRGU, vldrhq_gather_offset_u, v8hi, v4si)

> +VAR2 (LDRGS_Z, vldrhq_gather_shifted_offset_z_s, v8hi, v4si)

> +VAR2 (LDRGS_Z, vldrhq_gather_offset_z_s, v8hi, v4si)

> +VAR2 (LDRGS, vldrhq_gather_shifted_offset_s, v8hi, v4si)

> +VAR2 (LDRGS, vldrhq_gather_offset_s, v8hi, v4si)

> +VAR1 (LDRS, vldrhq_f, v8hf)

> +VAR1 (LDRS_Z, vldrhq_z_f, v8hf)

> +VAR1 (LDRS, vldrwq_f, v4sf)

> +VAR1 (LDRS, vldrwq_s, v4si)

> +VAR1 (LDRU, vldrwq_u, v4si)

> +VAR1 (LDRS_Z, vldrwq_z_f, v4sf)

> +VAR1 (LDRS_Z, vldrwq_z_s, v4si)

> +VAR1 (LDRU_Z, vldrwq_z_u, v4si)

> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md

> index

> 03a90ab3212954ea881c52e1b80bc69feed59a5d..89ff2e269e5ff0c42954cdd1f

> 773b5456cb6251a 100644

> --- a/gcc/config/arm/mve.md

> +++ b/gcc/config/arm/mve.md

> @@ -26,6 +26,7 @@

>  (define_mode_iterator MVE_3 [V16QI V8HI])

>  (define_mode_iterator MVE_2 [V16QI V8HI V4SI])

>  (define_mode_iterator MVE_5 [V8HI V4SI])

> +(define_mode_iterator MVE_6 [V8HI V4SI])

> 

>  (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F

> VRNDNQ_F VRNDMQ_F

>  			 VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F

> VABSQ_F VREV32Q_F

> @@ -193,10 +194,13 @@

>  			 VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F

> VMAXNMQ_M_F

>  			 VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S

> VSTRWQSB_U

>  			 VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U

> VLDRBQGO_S

> -			 VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S

> VLDRWQGB_U])

> +			 VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S

> VLDRWQGB_U

> +			 VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F

> VLDRHQGO_S

> +			 VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U

> VLDRHQ_S VLDRHQ_U

> +			 VLDRWQ_F VLDRWQ_S VLDRWQ_U])

> 

> -(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")

> -			    (V8HF "V8HI") (V4SF "V4SI")])

> +(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")

> +			    (V4SF "V4SI")])

> 

>  (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")

> (VREV16Q_S "s")

>  		       (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")

> @@ -348,7 +352,11 @@

>  		       (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")

>  		       (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")

>  		       (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")

> -		       (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")])

> +		       (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")

> +		       (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")

> +		       (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U

> "u")

> +		       (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")

> +		       (VLDRWQ_U "u")])

> 

>  (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")

>  			(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")

> @@ -362,10 +370,12 @@

>  				   (V4SI "mve_imm_31")])

>  (define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])

>  (define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI

> "mve_imm_16")])

> -

>  (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])

>  (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI

> "mve_imm_15")])

>  (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI

> "V4QI")])

> +(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])

> +(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI  "h") (V4SI "w") (V8HF

> "h")

> +			      (V4SF "w")])

> 

>  (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])

>  (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])

> @@ -575,6 +585,11 @@

>  (define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])

>  (define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])

>  (define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])

> +(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])

> +(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])

> +(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])

> +(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])

> +(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])

> 

>  (define_insn "*mve_mov<mode>"

>    [(set (match_operand:MVE_types 0 "nonimmediate_operand"

> "=w,w,r,w,w,r,w,Us")

> @@ -8208,3 +8223,276 @@

>     return "";

>  }

>    [(set_attr "length" "8")])

> +

> +;;

> +;; [vldrhq_f]

> +;;

> +(define_insn "mve_vldrhq_fv8hf"

> +  [(set (match_operand:V8HF 0 "s_register_operand" "=w")

> +	(unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")]

> +	 VLDRHQ_F))

> +  ]

> +  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vldrh.f16\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "4")])

> +

> +;;

> +;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]

> +;;

> +(define_insn "mve_vldrhq_gather_offset_<supf><mode>"

> +  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")

> +	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1

> "memory_operand" "Us")

> +		       (match_operand:MVE_6 2 "s_register_operand" "w")]

> +	VLDRHGOQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[3];

> +   ops[0] = operands[0];

> +   ops[1] = operands[1];

> +   ops[2] = operands[2];

> +   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)

> +     output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops);

> +   else

> +     output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);

> +   return "";

> +}

> +  [(set_attr "length" "4")])

> +

> +;;

> +;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]

> +;;

> +(define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"

> +  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")

> +	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1

> "memory_operand" "Us")

> +		       (match_operand:MVE_6 2 "s_register_operand" "w")

> +		       (match_operand:HI 3 "vpr_register_operand" "Up")

> +	]VLDRHGOQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[4];

> +   ops[0] = operands[0];

> +   ops[1] = operands[1];

> +   ops[2] = operands[2];

> +   ops[3] = operands[3];

> +   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)

> +     output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops);

> +   else

> +     output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0,

> [%m1, %q2]",ops);

> +   return "";

> +}

> + [(set_attr "length" "8")])

> +

> +;;

> +;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]

> +;;

> +(define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"

> +  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")

> +	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1

> "memory_operand" "Us")

> +		       (match_operand:MVE_6 2 "s_register_operand" "w")]

> +	VLDRHGSOQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[3];

> +   ops[0] = operands[0];

> +   ops[1] = operands[1];

> +   ops[2] = operands[2];

> +      if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)

> +     output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops);

> +   else

> +     output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw

> #1]",ops);

> +   return "";

> +}

> +  [(set_attr "length" "4")])

> +

> +;;

> +;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]

> +;;

> +(define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"

> +  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")

> +	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1

> "memory_operand" "Us")

> +		       (match_operand:MVE_6 2 "s_register_operand" "w")

> +		       (match_operand:HI 3 "vpr_register_operand" "Up")

> +	]VLDRHGSOQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[4];

> +   ops[0] = operands[0];

> +   ops[1] = operands[1];

> +   ops[2] = operands[2];

> +   ops[3] = operands[3];

> +   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)

> +     output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops);

> +   else

> +     output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2,

> uxtw #1]",ops);

> +   return "";

> +}

> +  [(set_attr "length" "8")])

> +

> +;;

> +;;

> +;; [vldrhq_s, vldrhq_u]

> +;;

> +(define_insn "mve_vldrhq_<supf><mode>"

> +  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")

> +	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1

> "memory_operand" "Us")]

> +	 VLDRHQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "4")])

> +

> +;;

> +;; [vldrhq_z_f]

> +;;

> +(define_insn "mve_vldrhq_z_fv8hf"

> +  [(set (match_operand:V8HF 0 "s_register_operand" "=w")

> +	(unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")

> +	(match_operand:HI 2 "vpr_register_operand" "Up")]

> +	 VLDRHQ_F))

> +  ]

> +  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vpst\n\tvldrht.f16\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "8")])

> +

> +;;

> +;; [vldrhq_z_s vldrhq_z_u]

> +;;

> +(define_insn "mve_vldrhq_z_<supf><mode>"

> +  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")

> +	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1

> "memory_operand" "Us")

> +	(match_operand:HI 2 "vpr_register_operand" "Up")]

> +	 VLDRHQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "8")])

> +

> +;;

> +;; [vldrwq_f]

> +;;

> +(define_insn "mve_vldrwq_fv4sf"

> +  [(set (match_operand:V4SF 0 "s_register_operand" "=w")

> +	(unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")]

> +	 VLDRWQ_F))

> +  ]

> +  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vldrw.f32\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "4")])

> +

> +;;

> +;; [vldrwq_s vldrwq_u]

> +;;

> +(define_insn "mve_vldrwq_<supf>v4si"

> +  [(set (match_operand:V4SI 0 "s_register_operand" "=w")

> +	(unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")]

> +	 VLDRWQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vldrw.<supf>32\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "4")])

> +

> +;;

> +;; [vldrwq_z_f]

> +;;

> +(define_insn "mve_vldrwq_z_fv4sf"

> +  [(set (match_operand:V4SF 0 "s_register_operand" "=w")

> +	(unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")

> +	(match_operand:HI 2 "vpr_register_operand" "Up")]

> +	 VLDRWQ_F))

> +  ]

> +  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vpst\n\tvldrwt.f32\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "8")])

> +

> +;;

> +;; [vldrwq_z_s vldrwq_z_u]

> +;;

> +(define_insn "mve_vldrwq_z_<supf>v4si"

> +  [(set (match_operand:V4SI 0 "s_register_operand" "=w")

> +	(unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")

> +	(match_operand:HI 2 "vpr_register_operand" "Up")]

> +	 VLDRWQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vpst\n\tvldrwt.<supf>32\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "8")])

> +

> +(define_expand "mve_vld1q_f<mode>"

> +  [(match_operand:MVE_0 0 "s_register_operand")

> +   (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "memory_operand")]

> VLD1Q_F)

> +  ]

> +  "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"

> +{

> +  emit_insn

> (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));

> +  DONE;

> +})

> +

> +(define_expand "mve_vld1q_<supf><mode>"

> +  [(match_operand:MVE_2 0 "s_register_operand")

> +   (unspec:MVE_2 [(match_operand:MVE_2 1 "memory_operand")] VLD1Q)

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +  emit_insn

> (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));

> +  DONE;

> +})

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..91e39f52c0fe63dc13aeaba

> 78469ccbfc1795239

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */

> +/* { dg-add-options arm_v8_1m_mve_fp } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +float16x8_t

> +foo (float16_t const * base)

> +{

> +  return vld1q_f16 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.f16"  }  } */

> +

> +float16x8_t

> +foo1 (float16_t const * base)

> +{

> +  return vld1q (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.f16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..0ef33ad2e0d3fae181eec59

> 378d797f744ecf564

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */

> +/* { dg-add-options arm_v8_1m_mve_fp } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +float32x4_t

> +foo (float32_t const * base)

> +{

> +  return vld1q_f32 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.f32"  }  } */

> +

> +float32x4_t

> +foo1 (float32_t const * base)

> +{

> +  return vld1q (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.f32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..adf2f5b2f7fef4e3c2740305f

> da40ff88d5e9138

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int16_t const * base)

> +{

> +  return vld1q_s16 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.s16"  }  } */

> +

> +int16x8_t

> +foo1 (int16_t const * base)

> +{

> +  return vld1q (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.s16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..94df0b4a0e49b32157c59cd

> ba73edb7af8821d25

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int32_t const * base)

> +{

> +  return vld1q_s32 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.s32"  }  } */

> +

> +int32x4_t

> +foo1 (int32_t const * base)

> +{

> +  return vld1q (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.s32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..9a8b3040af849ac3e0815b3

> 081aec4cc67d7a63d

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int8x16_t

> +foo (int8_t const * base)

> +{

> +  return vld1q_s8 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrb.s8"  }  } */

> +

> +int8x16_t

> +foo1 (int8_t const * base)

> +{

> +  return vld1q (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrb.s8"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..4c5916bd9a3c24f40ccacf6e

> caedd70a6de4447e

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint16_t const * base)

> +{

> +  return vld1q_u16 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> +

> +uint16x8_t

> +foo1 (uint16_t const * base)

> +{

> +  return vld1q (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..8f4d521890b81a7716d22b

> d94513e042e246794d

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint32_t const * base)

> +{

> +  return vld1q_u32 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.u32"  }  } */

> +

> +uint32x4_t

> +foo1 (uint32_t const * base)

> +{

> +  return vld1q (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.u32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..3804394ad4932c016271bc7

> b5a20e5e686dad3d1

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint8x16_t

> +foo (uint8_t const * base)

> +{

> +  return vld1q_u8 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrb.u8"  }  } */

> +

> +uint8x16_t

> +foo1 (uint8_t const * base)

> +{

> +  return vld1q (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrb.u8"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..ef7b5d4b90e9175d85c791c

> d606bb0da5633c05c

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */

> +/* { dg-add-options arm_v8_1m_mve_fp } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +float16x8_t

> +foo (float16_t const * base)

> +{

> +  return vldrhq_f16 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.f16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..72e5ae2a36c8d7c7b3d58cd

> daf26b24a2c809c96

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int16_t const * base, uint16x8_t offset)

> +{

> +  return vldrhq_gather_offset_s16 (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> +

> +int16x8_t

> +foo1 (int16_t const * base, uint16x8_t offset)

> +{

> +  return vldrhq_gather_offset (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..14a850a7574212944bb374

> 30e9836d2205be5151

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int16_t const * base, uint32x4_t offset)

> +{

> +  return vldrhq_gather_offset_s32 (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.s32"  }  } */

> +

> +int32x4_t

> +foo1 (int16_t const * base, uint32x4_t offset)

> +{

> +  return vldrhq_gather_offset (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.s32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..6e8f881c102a6e7defae472

> 427f139cabe47e8be

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint16_t const * base, uint16x8_t offset)

> +{

> +  return vldrhq_gather_offset_u16 (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> +

> +uint16x8_t

> +foo1 (uint16_t const * base, uint16x8_t offset)

> +{

> +  return vldrhq_gather_offset (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..5e18f632931dd9cf720f55f8

> f0903ebc41490f30

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint16_t const * base, uint32x4_t offset)

> +{

> +  return vldrhq_gather_offset_u32 (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u32"  }  } */

> +

> +uint32x4_t

> +foo1 (uint16_t const * base, uint32x4_t offset)

> +{

> +  return vldrhq_gather_offset (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..625a8189f789e9759dfb420

> ace2ef2170c0b9281

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_offset_z_s16 (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> +

> +int16x8_t

> +foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_offset_z (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..bb104680877940fb03cf026

> 0630469577e42a66a

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_offset_z_s32 (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.s32"  }  } */

> +

> +int32x4_t

> +foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_offset_z (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.s32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..8a69d05d498f4b6c468b717

> e7bb6e489d4a15139

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_offset_z_u16 (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> +

> +uint16x8_t

> +foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_offset_z (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..f88dc5e2358496d8164b0e4

> 04cd5bd960fae2062

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_offset_z_u32 (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u32"  }  } */

> +

> +uint32x4_t

> +foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_offset_z (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..b82323f7bc4e0f2619c51bd

> 2e423b53d2fc5b1fe

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> s16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int16_t const * base, uint16x8_t offset)

> +{

> +  return vldrhq_gather_shifted_offset_s16 (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> +

> +int16x8_t

> +foo1 (int16_t const * base, uint16x8_t offset)

> +{

> +  return vldrhq_gather_shifted_offset (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..15f496cd7c419dff795e546f

> 43038b7280b5ab42

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> s32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int16_t const * base, uint32x4_t offset)

> +{

> +  return vldrhq_gather_shifted_offset_s32 (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.s32"  }  } */

> +

> +int32x4_t

> +foo1 (int16_t const * base, uint32x4_t offset)

> +{

> +  return vldrhq_gather_shifted_offset (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.s32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..ccf93d4abcd793e25098e75

> dd4fbb774201995de

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> u16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint16_t const * base, uint16x8_t offset)

> +{

> +  return vldrhq_gather_shifted_offset_u16 (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> +

> +uint16x8_t

> +foo1 (uint16_t const * base, uint16x8_t offset)

> +{

> +  return vldrhq_gather_shifted_offset (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..558893cc01d6ca4a243237fc

> eff0622f02b15043

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> u32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint16_t const * base, uint32x4_t offset)

> +{

> +  return vldrhq_gather_shifted_offset_u32 (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u32"  }  } */

> +

> +uint32x4_t

> +foo1 (uint16_t const * base, uint32x4_t offset)

> +{

> +  return vldrhq_gather_shifted_offset (base, offset);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..c2f5429a1b2c43ae9ecd225

> 9523feab76d7ee951

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_s16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_shifted_offset_z_s16 (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> +

> +int16x8_t

> +foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_shifted_offset_z (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..25655929c0bc649e26db6f4

> c7ef7b94bd580e814

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_s32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_shifted_offset_z_s32 (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.s32"  }  } */

> +

> +int32x4_t

> +foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_shifted_offset_z (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.s32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..3ade33919592e633675014

> 3fd36dc3888e8ab551

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_u16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_shifted_offset_z_u16 (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> +

> +uint16x8_t

> +foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_shifted_offset_z (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..c37203bb6607a9e54bf8b10

> b999b5e91866ba2ce

> --- /dev/null

> +++

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_

> z_u32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_shifted_offset_z_u32 (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u32"  }  } */

> +

> +uint32x4_t

> +foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)

> +{

> +  return vldrhq_gather_shifted_offset_z (base, offset, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..dd5b7c0e6f3c85a9384b0b7

> 99662bbd3a0345dc7

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int16_t const * base)

> +{

> +  return vldrhq_s16 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.s16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..ee3613ca5202695f380f833

> 3536c07fd087794ce

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int16_t const * base)

> +{

> +  return vldrhq_s32 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.s32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..460931fb818585549ac8b81

> 77468a09e3f5d9096

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint16_t const * base)

> +{

> +  return vldrhq_u16 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..1cd04f5c9678845bedb4d2c

> eaa92f0eb28bccc81

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint16_t const * base)

> +{

> +  return vldrhq_u32 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrh.u32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..3ea1db7e0532fae867ee216

> 0babe926d3d47429f

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */

> +/* { dg-add-options arm_v8_1m_mve_fp } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +float16x8_t

> +foo (float16_t const * base, mve_pred16_t p)

> +{

> +  return vldrhq_z_f16 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.f16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..9a700ab3f72e882602a55cc

> 5f8293ef3b20f58e5

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int16_t const * base, mve_pred16_t p)

> +{

> +  return vldrhq_z_s16 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.s16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..729b6272d9e7ce0854819d

> d9f8268d81739bc3e6

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int16_t const * base, mve_pred16_t p)

> +{

> +  return vldrhq_z_s32 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.s32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..a511e3af9771eb0f7cbcc211

> 7050778c7c27ac53

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint16_t const * base, mve_pred16_t p)

> +{

> +  return vldrhq_z_u16 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..7b0a9a26d951e8fdea7eb6c

> 6844fed598a7cf6d7

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint16_t const * base, mve_pred16_t p)

> +{

> +  return vldrhq_z_u32 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrht.u32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..eea45715beae15fe37b426f

> a3c41b8aaf5031f36

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */

> +/* { dg-add-options arm_v8_1m_mve_fp } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +float32x4_t

> +foo (float32_t const * base)

> +{

> +  return vldrwq_f32 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.f32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..4f18dc675b120161792295c

> e64c111c3bd7d6d4c

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int32_t const * base)

> +{

> +  return vldrwq_s32 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.s32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..b3672e51e5901d7b15f028f

> 50b7e61178ebc2474

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint32_t const * base)

> +{

> +  return vldrwq_u32 (base);

> +}

> +

> +/* { dg-final { scan-assembler "vldrw.u32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..0af5f964d6be1ad89269eccc

> 47eda449e211582c

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */

> +/* { dg-add-options arm_v8_1m_mve_fp } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +float32x4_t

> +foo (float32_t const * base, mve_pred16_t p)

> +{

> +  return vldrwq_z_f32 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrwt.f32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..a8589cd596be840ff117729f

> d8386a9b600b7068

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int32_t const * base, mve_pred16_t p)

> +{

> +  return vldrwq_z_s32 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrwt.s32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..d5fa5cf2f21564f6b589168e

> f3bb41cb9615e2a2

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint32_t const * base, mve_pred16_t p)

> +{

> +  return vldrwq_z_u32 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrwt.u32"  }  } */

Patch

diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 4570a0b16c37b11471a61f4b53686945063b4a55..9991e25c8d642c8109ab9ce9f48a818508d7801c 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -1758,6 +1758,46 @@  typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
 #define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p)
 #define vldrwq_gather_base_z_u32(__addr,  __offset, __p) __arm_vldrwq_gather_base_z_u32(__addr,  __offset, __p)
 #define vldrwq_gather_base_z_s32(__addr,  __offset, __p) __arm_vldrwq_gather_base_z_s32(__addr,  __offset, __p)
+#define vld1q_s8(__base) __arm_vld1q_s8(__base)
+#define vld1q_s32(__base) __arm_vld1q_s32(__base)
+#define vld1q_s16(__base) __arm_vld1q_s16(__base)
+#define vld1q_u8(__base) __arm_vld1q_u8(__base)
+#define vld1q_u32(__base) __arm_vld1q_u32(__base)
+#define vld1q_u16(__base) __arm_vld1q_u16(__base)
+#define vldrhq_gather_offset_s32(__base, __offset) __arm_vldrhq_gather_offset_s32(__base, __offset)
+#define vldrhq_gather_offset_s16(__base, __offset) __arm_vldrhq_gather_offset_s16(__base, __offset)
+#define vldrhq_gather_offset_u32(__base, __offset) __arm_vldrhq_gather_offset_u32(__base, __offset)
+#define vldrhq_gather_offset_u16(__base, __offset) __arm_vldrhq_gather_offset_u16(__base, __offset)
+#define vldrhq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrhq_gather_offset_z_s32(__base, __offset, __p)
+#define vldrhq_gather_offset_z_s16(__base, __offset, __p) __arm_vldrhq_gather_offset_z_s16(__base, __offset, __p)
+#define vldrhq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrhq_gather_offset_z_u32(__base, __offset, __p)
+#define vldrhq_gather_offset_z_u16(__base, __offset, __p) __arm_vldrhq_gather_offset_z_u16(__base, __offset, __p)
+#define vldrhq_gather_shifted_offset_s32(__base, __offset) __arm_vldrhq_gather_shifted_offset_s32(__base, __offset)
+#define vldrhq_gather_shifted_offset_s16(__base, __offset) __arm_vldrhq_gather_shifted_offset_s16(__base, __offset)
+#define vldrhq_gather_shifted_offset_u32(__base, __offset) __arm_vldrhq_gather_shifted_offset_u32(__base, __offset)
+#define vldrhq_gather_shifted_offset_u16(__base, __offset) __arm_vldrhq_gather_shifted_offset_u16(__base, __offset)
+#define vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p)
+#define vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p)
+#define vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p)
+#define vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p)
+#define vldrhq_s32(__base) __arm_vldrhq_s32(__base)
+#define vldrhq_s16(__base) __arm_vldrhq_s16(__base)
+#define vldrhq_u32(__base) __arm_vldrhq_u32(__base)
+#define vldrhq_u16(__base) __arm_vldrhq_u16(__base)
+#define vldrhq_z_s32(__base, __p) __arm_vldrhq_z_s32(__base, __p)
+#define vldrhq_z_s16(__base, __p) __arm_vldrhq_z_s16(__base, __p)
+#define vldrhq_z_u32(__base, __p) __arm_vldrhq_z_u32(__base, __p)
+#define vldrhq_z_u16(__base, __p) __arm_vldrhq_z_u16(__base, __p)
+#define vldrwq_s32(__base) __arm_vldrwq_s32(__base)
+#define vldrwq_u32(__base) __arm_vldrwq_u32(__base)
+#define vldrwq_z_s32(__base, __p) __arm_vldrwq_z_s32(__base, __p)
+#define vldrwq_z_u32(__base, __p) __arm_vldrwq_z_u32(__base, __p)
+#define vld1q_f32(__base) __arm_vld1q_f32(__base)
+#define vld1q_f16(__base) __arm_vld1q_f16(__base)
+#define vldrhq_f16(__base) __arm_vldrhq_f16(__base)
+#define vldrhq_z_f16(__base, __p) __arm_vldrhq_z_f16(__base, __p)
+#define vldrwq_f32(__base) __arm_vldrwq_f32(__base)
+#define vldrwq_z_f32(__base, __p) __arm_vldrwq_z_f32(__base, __p)
 #endif
 
 __extension__ extern __inline void
@@ -11443,6 +11483,245 @@  __arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr, const int __offset, mve_pred1
   return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p);
 }
 
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_s8 (int8_t const * __base)
+{
+  return __builtin_mve_vld1q_sv16qi ((__builtin_neon_qi *) __base);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_s32 (int32_t const * __base)
+{
+  return __builtin_mve_vld1q_sv4si ((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_s16 (int16_t const * __base)
+{
+  return __builtin_mve_vld1q_sv8hi ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_u8 (uint8_t const * __base)
+{
+  return __builtin_mve_vld1q_uv16qi ((__builtin_neon_qi *) __base);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_u32 (uint32_t const * __base)
+{
+  return __builtin_mve_vld1q_uv4si ((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_u16 (uint16_t const * __base)
+{
+  return __builtin_mve_vld1q_uv8hi ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_s32 (int16_t const * __base, uint32x4_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_offset_sv4si ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_s16 (int16_t const * __base, uint16x8_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_offset_sv8hi ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_u32 (uint16_t const * __base, uint32x4_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_offset_uv4si ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_u16 (uint16_t const * __base, uint16x8_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_offset_uv8hi ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_s32 (int16_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_offset_z_sv4si ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_s16 (int16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_offset_z_sv8hi ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_u32 (uint16_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_offset_z_uv4si ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_u16 (uint16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_offset_z_uv8hi ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_s32 (int16_t const * __base, uint32x4_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_sv4si ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_s16 (int16_t const * __base, uint16x8_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_sv8hi ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_u32 (uint16_t const * __base, uint32x4_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_uv4si ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_u16 (uint16_t const * __base, uint16x8_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_uv8hi ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_s32 (int16_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_z_sv4si ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_s16 (int16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_z_sv8hi ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_u32 (uint16_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_z_uv4si ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_u16 (uint16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_z_uv8hi ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_s32 (int16_t const * __base)
+{
+  return __builtin_mve_vldrhq_sv4si ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_s16 (int16_t const * __base)
+{
+  return __builtin_mve_vldrhq_sv8hi ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_u32 (uint16_t const * __base)
+{
+  return __builtin_mve_vldrhq_uv4si ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_u16 (uint16_t const * __base)
+{
+  return __builtin_mve_vldrhq_uv8hi ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_s32 (int16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_sv4si ((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_s16 (int16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_sv8hi ((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_u32 (uint16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_uv4si ((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_u16 (uint16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_uv8hi ((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_s32 (int32_t const * __base)
+{
+  return __builtin_mve_vldrwq_sv4si ((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_u32 (uint32_t const * __base)
+{
+  return __builtin_mve_vldrwq_uv4si ((__builtin_neon_si *) __base);
+}
+
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_z_s32 (int32_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_z_sv4si ((__builtin_neon_si *) __base, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_z_u32 (uint32_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_z_uv4si ((__builtin_neon_si *) __base, __p);
+}
+
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
 __extension__ extern __inline void
@@ -13585,6 +13864,47 @@  __arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve
   return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p);
 }
 
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_f32 (float32_t const * __base)
+{
+  return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_f16 (float16_t const * __base)
+{
+  return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_f32 (float32_t const * __base)
+{
+  return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_f16 (float16_t const * __base)
+{
+  return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base);
+}
 #endif
 
 enum {
@@ -16052,6 +16372,18 @@  extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
 
+#define vld1q(p0) __arm_vld1q(p0)
+#define __arm_vld1q(p0) ({ __typeof(p0) __p0 = (p0); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+  int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \
+  int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \
+  int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \
+  int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)), \
+  int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce(__p0, float16_t const *)), \
+  int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce(__p0, float32_t const *)));})
+
 #else /* MVE Integer.  */
 
 #define vst4q(p0,p1) __arm_vst4q(p0,p1)
@@ -18148,6 +18480,52 @@  extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
+#define vld1q(p0) __arm_vld1q(p0)
+#define __arm_vld1q(p0) ({ __typeof(p0) __p0 = (p0); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+  int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \
+  int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \
+  int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \
+  int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)));})
+
+#define vldrhq_gather_offset(p0,p1) __arm_vldrhq_gather_offset(p0,p1)
+#define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+
+#define vldrhq_gather_offset_z(p0,p1,p2) __arm_vldrhq_gather_offset_z(p0,p1,p2)
+#define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
+#define vldrhq_gather_shifted_offset(p0,p1) __arm_vldrhq_gather_shifted_offset(p0,p1)
+#define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+
+#define vldrhq_gather_shifted_offset_z(p0,p1,p2) __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2)
+#define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
 #endif /* MVE Integer.  */
 
 #define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2)
diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index 0f466e4cec295c1d791d675b52ff15e364d7016e..bafc953a5e5108caa9595ea9189ed1182da2c692 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -709,3 +709,26 @@  VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, v4si)
 VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si)
 VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si)
 VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si)
+VAR3 (LDRU, vld1q_u, v16qi, v8hi, v4si)
+VAR3 (LDRS, vld1q_s, v16qi, v8hi, v4si)
+VAR2 (LDRU_Z, vldrhq_z_u, v8hi, v4si)
+VAR2 (LDRU, vldrhq_u, v8hi, v4si)
+VAR2 (LDRS_Z, vldrhq_z_s, v8hi, v4si)
+VAR2 (LDRS, vldrhq_s, v8hi, v4si)
+VAR2 (LDRS, vld1q_f, v8hf, v4sf)
+VAR2 (LDRGU_Z, vldrhq_gather_shifted_offset_z_u, v8hi, v4si)
+VAR2 (LDRGU_Z, vldrhq_gather_offset_z_u, v8hi, v4si)
+VAR2 (LDRGU, vldrhq_gather_shifted_offset_u, v8hi, v4si)
+VAR2 (LDRGU, vldrhq_gather_offset_u, v8hi, v4si)
+VAR2 (LDRGS_Z, vldrhq_gather_shifted_offset_z_s, v8hi, v4si)
+VAR2 (LDRGS_Z, vldrhq_gather_offset_z_s, v8hi, v4si)
+VAR2 (LDRGS, vldrhq_gather_shifted_offset_s, v8hi, v4si)
+VAR2 (LDRGS, vldrhq_gather_offset_s, v8hi, v4si)
+VAR1 (LDRS, vldrhq_f, v8hf)
+VAR1 (LDRS_Z, vldrhq_z_f, v8hf)
+VAR1 (LDRS, vldrwq_f, v4sf)
+VAR1 (LDRS, vldrwq_s, v4si)
+VAR1 (LDRU, vldrwq_u, v4si)
+VAR1 (LDRS_Z, vldrwq_z_f, v4sf)
+VAR1 (LDRS_Z, vldrwq_z_s, v4si)
+VAR1 (LDRU_Z, vldrwq_z_u, v4si)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 03a90ab3212954ea881c52e1b80bc69feed59a5d..89ff2e269e5ff0c42954cdd1f773b5456cb6251a 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -26,6 +26,7 @@ 
 (define_mode_iterator MVE_3 [V16QI V8HI])
 (define_mode_iterator MVE_2 [V16QI V8HI V4SI])
 (define_mode_iterator MVE_5 [V8HI V4SI])
+(define_mode_iterator MVE_6 [V8HI V4SI])
 
 (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
 			 VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
@@ -193,10 +194,13 @@ 
 			 VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F
 			 VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U
 			 VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S
-			 VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U])
+			 VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U
+			 VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S
+			 VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U
+			 VLDRWQ_F VLDRWQ_S VLDRWQ_U])
 
-(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
-			    (V8HF "V8HI") (V4SF "V4SI")])
+(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
+			    (V4SF "V4SI")])
 
 (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
 		       (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
@@ -348,7 +352,11 @@ 
 		       (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
 		       (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
 		       (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
-		       (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")])
+		       (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")
+		       (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")
+		       (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u")
+		       (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")
+		       (VLDRWQ_U "u")])
 
 (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
 			(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
@@ -362,10 +370,12 @@ 
 				   (V4SI "mve_imm_31")])
 (define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
 (define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
-
 (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
 (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
 (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
+(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
+(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI  "h") (V4SI "w") (V8HF "h")
+			      (V4SF "w")])
 
 (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
 (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
@@ -575,6 +585,11 @@ 
 (define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
 (define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
 (define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
+(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])
+(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])
+(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])
+(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])
+(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])
 
 (define_insn "*mve_mov<mode>"
   [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
@@ -8208,3 +8223,276 @@ 
    return "";
 }
   [(set_attr "length" "8")])
+
+;;
+;; [vldrhq_f]
+;;
+(define_insn "mve_vldrhq_fv8hf"
+  [(set (match_operand:V8HF 0 "s_register_operand" "=w")
+	(unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")]
+	 VLDRHQ_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vldrh.f16\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
+;;
+(define_insn "mve_vldrhq_gather_offset_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
+	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+		       (match_operand:MVE_6 2 "s_register_operand" "w")]
+	VLDRHGOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[3];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
+     output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops);
+   else
+     output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
+;;
+(define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
+	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+		       (match_operand:MVE_6 2 "s_register_operand" "w")
+		       (match_operand:HI 3 "vpr_register_operand" "Up")
+	]VLDRHGOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   ops[3] = operands[3];
+   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
+     output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops);
+   else
+     output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
+   return "";
+}
+ [(set_attr "length" "8")])
+
+;;
+;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
+;;
+(define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
+	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+		       (match_operand:MVE_6 2 "s_register_operand" "w")]
+	VLDRHGSOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[3];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+      if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
+     output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
+   else
+     output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
+;;
+(define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
+	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+		       (match_operand:MVE_6 2 "s_register_operand" "w")
+		       (match_operand:HI 3 "vpr_register_operand" "Up")
+	]VLDRHGSOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   ops[3] = operands[3];
+   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
+     output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
+   else
+     output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;;
+;; [vldrhq_s, vldrhq_u]
+;;
+(define_insn "mve_vldrhq_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
+	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")]
+	 VLDRHQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrhq_z_f]
+;;
+(define_insn "mve_vldrhq_z_fv8hf"
+  [(set (match_operand:V8HF 0 "s_register_operand" "=w")
+	(unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
+	(match_operand:HI 2 "vpr_register_operand" "Up")]
+	 VLDRHQ_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrht.f16\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrhq_z_s vldrhq_z_u]
+;;
+(define_insn "mve_vldrhq_z_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
+	(unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+	(match_operand:HI 2 "vpr_register_operand" "Up")]
+	 VLDRHQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrwq_f]
+;;
+(define_insn "mve_vldrwq_fv4sf"
+  [(set (match_operand:V4SF 0 "s_register_operand" "=w")
+	(unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")]
+	 VLDRWQ_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vldrw.f32\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrwq_s vldrwq_u]
+;;
+(define_insn "mve_vldrwq_<supf>v4si"
+  [(set (match_operand:V4SI 0 "s_register_operand" "=w")
+	(unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")]
+	 VLDRWQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vldrw.<supf>32\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrwq_z_f]
+;;
+(define_insn "mve_vldrwq_z_fv4sf"
+  [(set (match_operand:V4SF 0 "s_register_operand" "=w")
+	(unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
+	(match_operand:HI 2 "vpr_register_operand" "Up")]
+	 VLDRWQ_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrwt.f32\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrwq_z_s vldrwq_z_u]
+;;
+(define_insn "mve_vldrwq_z_<supf>v4si"
+  [(set (match_operand:V4SI 0 "s_register_operand" "=w")
+	(unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
+	(match_operand:HI 2 "vpr_register_operand" "Up")]
+	 VLDRWQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrwt.<supf>32\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+(define_expand "mve_vld1q_f<mode>"
+  [(match_operand:MVE_0 0 "s_register_operand")
+   (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "memory_operand")] VLD1Q_F)
+  ]
+  "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
+{
+  emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
+  DONE;
+})
+
+(define_expand "mve_vld1q_<supf><mode>"
+  [(match_operand:MVE_2 0 "s_register_operand")
+   (unspec:MVE_2 [(match_operand:MVE_2 1 "memory_operand")] VLD1Q)
+  ]
+  "TARGET_HAVE_MVE"
+{
+  emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
+  DONE;
+})
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..91e39f52c0fe63dc13aeaba78469ccbfc1795239
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16_t const * base)
+{
+  return vld1q_f16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.f16"  }  } */
+
+float16x8_t
+foo1 (float16_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..0ef33ad2e0d3fae181eec59378d797f744ecf564
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32_t const * base)
+{
+  return vld1q_f32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.f32"  }  } */
+
+float32x4_t
+foo1 (float32_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..adf2f5b2f7fef4e3c2740305fda40ff88d5e9138
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base)
+{
+  return vld1q_s16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.s16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..94df0b4a0e49b32157c59cdba73edb7af8821d25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32_t const * base)
+{
+  return vld1q_s32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.s32"  }  } */
+
+int32x4_t
+foo1 (int32_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a8b3040af849ac3e0815b3081aec4cc67d7a63d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8_t const * base)
+{
+  return vld1q_s8 (base);
+}
+
+/* { dg-final { scan-assembler "vldrb.s8"  }  } */
+
+int8x16_t
+foo1 (int8_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrb.s8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..4c5916bd9a3c24f40ccacf6ecaedd70a6de4447e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base)
+{
+  return vld1q_u16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..8f4d521890b81a7716d22bd94513e042e246794d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32_t const * base)
+{
+  return vld1q_u32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+
+uint32x4_t
+foo1 (uint32_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
new file mode 100644
index 0000000000000000000000000000000000000000..3804394ad4932c016271bc7b5a20e5e686dad3d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8_t const * base)
+{
+  return vld1q_u8 (base);
+}
+
+/* { dg-final { scan-assembler "vldrb.u8"  }  } */
+
+uint8x16_t
+foo1 (uint8_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrb.u8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..ef7b5d4b90e9175d85c791cd606bb0da5633c05c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16_t const * base)
+{
+  return vldrhq_f16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..72e5ae2a36c8d7c7b3d58cddaf26b24a2c809c96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_offset_s16 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..14a850a7574212944bb37430e9836d2205be5151
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_offset_s32 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
+
+int32x4_t
+foo1 (int16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e8f881c102a6e7defae472427f139cabe47e8be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_offset_u16 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..5e18f632931dd9cf720f55f8f0903ebc41490f30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_offset_u32 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
+
+uint32x4_t
+foo1 (uint16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..625a8189f789e9759dfb420ace2ef2170c0b9281
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z_s16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..bb104680877940fb03cf0260630469577e42a66a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z_s32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
+
+int32x4_t
+foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..8a69d05d498f4b6c468b717e7bb6e489d4a15139
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z_u16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..f88dc5e2358496d8164b0e404cd5bd960fae2062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z_u32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
+
+uint32x4_t
+foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..b82323f7bc4e0f2619c51bd2e423b53d2fc5b1fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_shifted_offset_s16 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_shifted_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..15f496cd7c419dff795e546f43038b7280b5ab42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_shifted_offset_s32 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
+
+int32x4_t
+foo1 (int16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_shifted_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..ccf93d4abcd793e25098e75dd4fbb774201995de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_shifted_offset_u16 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_shifted_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..558893cc01d6ca4a243237fceff0622f02b15043
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_shifted_offset_u32 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
+
+uint32x4_t
+foo1 (uint16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_shifted_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..c2f5429a1b2c43ae9ecd2259523feab76d7ee951
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z_s16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..25655929c0bc649e26db6f4c7ef7b94bd580e814
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z_s32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
+
+int32x4_t
+foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..3ade33919592e6336750143fd36dc3888e8ab551
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z_u16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..c37203bb6607a9e54bf8b10b999b5e91866ba2ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z_u32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
+
+uint32x4_t
+foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..dd5b7c0e6f3c85a9384b0b799662bbd3a0345dc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base)
+{
+  return vldrhq_s16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..ee3613ca5202695f380f8333536c07fd087794ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base)
+{
+  return vldrhq_s32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..460931fb818585549ac8b8177468a09e3f5d9096
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base)
+{
+  return vldrhq_u16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..1cd04f5c9678845bedb4d2ceaa92f0eb28bccc81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base)
+{
+  return vldrhq_u32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..3ea1db7e0532fae867ee2160babe926d3d47429f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_f16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a700ab3f72e882602a55cc5f8293ef3b20f58e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_s16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..729b6272d9e7ce0854819dd9f8268d81739bc3e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_s32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..a511e3af9771eb0f7cbcc2117050778c7c27ac53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_u16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b0a9a26d951e8fdea7eb6c6844fed598a7cf6d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_u32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..eea45715beae15fe37b426fa3c41b8aaf5031f36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32_t const * base)
+{
+  return vldrwq_f32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..4f18dc675b120161792295ce64c111c3bd7d6d4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32_t const * base)
+{
+  return vldrwq_s32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..b3672e51e5901d7b15f028f50b7e61178ebc2474
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32_t const * base)
+{
+  return vldrwq_u32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..0af5f964d6be1ad89269eccc47eda449e211582c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32_t const * base, mve_pred16_t p)
+{
+  return vldrwq_z_f32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..a8589cd596be840ff117729fd8386a9b600b7068
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32_t const * base, mve_pred16_t p)
+{
+  return vldrwq_z_s32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..d5fa5cf2f21564f6b589168ef3bb41cb9615e2a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32_t const * base, mve_pred16_t p)
+{
+  return vldrwq_z_u32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.u32"  }  } */