[v2,ARM,4/5x] : MVE load intrinsics with zero(_z) suffix.

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  • [v2,ARM,4/5x] : MVE load intrinsics with zero(_z) suffix.
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Commit Message

Srinath Parvathaneni March 18, 2020, 5:17 p.m.
Hello Kyrill,

Following patch is the rebased version of v1.
(version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-November/534333.html

####

Hello,

This patch supports the following MVE ACLE load intrinsics with zero(_z)
suffix.
* ``_z`` (zero) which indicates false-predicated lanes are filled with zeroes,
these are only used for load instructions.

vldrbq_gather_offset_z_s16, vldrbq_gather_offset_z_u8, vldrbq_gather_offset_z_s32,
vldrbq_gather_offset_z_u16, vldrbq_gather_offset_z_u32, vldrbq_gather_offset_z_s8,
vldrbq_z_s16, vldrbq_z_u8, vldrbq_z_s8, vldrbq_z_s32, vldrbq_z_u16, vldrbq_z_u32,
vldrwq_gather_base_z_u32, vldrwq_gather_base_z_s32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1]  https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

Regression tested on arm-none-eabi and found no regressions.

Ok for trunk?

Thanks,
Srinath.

gcc/ChangeLog:

2019-11-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Mihail Ionescu  <mihail.ionescu@arm.com>
	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
	qualifier.
	(LDRGBU_Z_QUALIFIERS): Likewise.
	(LDRGS_Z_QUALIFIERS): Likewise.
	(LDRGU_Z_QUALIFIERS): Likewise.
	(LDRS_Z_QUALIFIERS): Likewise.
	(LDRU_Z_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
	(vldrbq_gather_offset_z_u8): Likewise.
	(vldrbq_gather_offset_z_s32): Likewise.
	(vldrbq_gather_offset_z_u16): Likewise.
	(vldrbq_gather_offset_z_u32): Likewise.
	(vldrbq_gather_offset_z_s8): Likewise.
	(vldrbq_z_s16): Likewise.
	(vldrbq_z_u8): Likewise.
	(vldrbq_z_s8): Likewise.
	(vldrbq_z_s32): Likewise.
	(vldrbq_z_u16): Likewise.
	(vldrbq_z_u32): Likewise.
	(vldrwq_gather_base_z_u32): Likewise.
	(vldrwq_gather_base_z_s32): Likewise.
	(__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
	(__arm_vldrbq_gather_offset_z_s32): Likewise.
	(__arm_vldrbq_gather_offset_z_s16): Likewise.
	(__arm_vldrbq_gather_offset_z_u8): Likewise.
	(__arm_vldrbq_gather_offset_z_u32): Likewise.
	(__arm_vldrbq_gather_offset_z_u16): Likewise.
	(__arm_vldrbq_z_s8): Likewise.
	(__arm_vldrbq_z_s32): Likewise.
	(__arm_vldrbq_z_s16): Likewise.
	(__arm_vldrbq_z_u8): Likewise.
	(__arm_vldrbq_z_u32): Likewise.
	(__arm_vldrbq_z_u16): Likewise.
	(__arm_vldrwq_gather_base_z_s32): Likewise.
	(__arm_vldrwq_gather_base_z_u32): Likewise.
	(vldrbq_gather_offset_z): Define polymorphic variant.
	* config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
        qualifier.
        (LDRGBU_Z_QUALIFIERS): Likewise.
        (LDRGS_Z_QUALIFIERS): Likewise.
        (LDRGU_Z_QUALIFIERS): Likewise.
        (LDRS_Z_QUALIFIERS): Likewise.
        (LDRU_Z_QUALIFIERS): Likewise.
	* config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
	RTL pattern.
	(mve_vldrbq_z_<supf><mode>): Likewise.
	(mve_vldrwq_gather_base_z_<supf>v4si): Likewise.

gcc/testsuite/ChangeLog: Likewise.

2019-11-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Mihail Ionescu  <mihail.ionescu@arm.com>
	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise.


###############     Attachment also inlined for ease of reply    ###############
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index c87fa3118510e4de90ac9afe08608fb2315f4809..c3deb9efc8849019141b6430543e93605fda4af4 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -677,6 +677,40 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate};
 #define LDRGBU_QUALIFIERS (arm_ldrgbu_qualifiers)
 
+static enum arm_type_qualifiers
+arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_unsigned, qualifier_immediate,
+      qualifier_unsigned};
+#define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
+      qualifier_unsigned};
+#define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrgs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_pointer, qualifier_unsigned,
+      qualifier_unsigned};
+#define LDRGS_Z_QUALIFIERS (arm_ldrgs_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrgu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned,
+      qualifier_unsigned};
+#define LDRGU_Z_QUALIFIERS (arm_ldrgu_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_pointer, qualifier_unsigned};
+#define LDRS_Z_QUALIFIERS (arm_ldrs_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned};
+#define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers)
+
 /* End of Qualifier for MVE builtins.  */
 
    /* void ([T element type] *, T, immediate).  */
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index deed81cfb31b2cf8f830076c5e44098c1abf2310..4570a0b16c37b11471a61f4b53686945063b4a55 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -1744,6 +1744,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
 #define vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p)
 #define vstrwq_scatter_base_p_s32(__addr,  __offset, __value, __p) __arm_vstrwq_scatter_base_p_s32(__addr,  __offset, __value, __p)
 #define vstrwq_scatter_base_p_u32(__addr,  __offset, __value, __p) __arm_vstrwq_scatter_base_p_u32(__addr,  __offset, __value, __p)
+#define vldrbq_gather_offset_z_s16(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s16(__base, __offset, __p)
+#define vldrbq_gather_offset_z_u8(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u8(__base, __offset, __p)
+#define vldrbq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s32(__base, __offset, __p)
+#define vldrbq_gather_offset_z_u16(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u16(__base, __offset, __p)
+#define vldrbq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u32(__base, __offset, __p)
+#define vldrbq_gather_offset_z_s8(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s8(__base, __offset, __p)
+#define vldrbq_z_s16(__base, __p) __arm_vldrbq_z_s16(__base, __p)
+#define vldrbq_z_u8(__base, __p) __arm_vldrbq_z_u8(__base, __p)
+#define vldrbq_z_s8(__base, __p) __arm_vldrbq_z_s8(__base, __p)
+#define vldrbq_z_s32(__base, __p) __arm_vldrbq_z_s32(__base, __p)
+#define vldrbq_z_u16(__base, __p) __arm_vldrbq_z_u16(__base, __p)
+#define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p)
+#define vldrwq_gather_base_z_u32(__addr,  __offset, __p) __arm_vldrwq_gather_base_z_u32(__addr,  __offset, __p)
+#define vldrwq_gather_base_z_s32(__addr,  __offset, __p) __arm_vldrwq_gather_base_z_s32(__addr,  __offset, __p)
 #endif
 
 __extension__ extern __inline void
@@ -11330,6 +11344,105 @@ __arm_vstrwq_scatter_base_p_u32 (uint32x4_t __addr, const int __offset, uint32x4
 {
   __builtin_mve_vstrwq_scatter_base_p_uv4si (__addr, __offset, __value, __p);
 }
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_s8 (int8_t const * __base, uint8x16_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_sv16qi ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_s32 (int8_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_sv4si ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_s16 (int8_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_sv8hi ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_u8 (uint8_t const * __base, uint8x16_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_uv16qi ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_u32 (uint8_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_uv4si ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_u16 (uint8_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_uv8hi ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_s8 (int8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_sv16qi ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_s32 (int8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_sv4si ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_s16 (int8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_sv8hi ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_u8 (uint8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_uv16qi ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_u32 (uint8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_uv4si ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_u16 (uint8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_uv8hi ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_base_z_s32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_gather_base_z_sv4si (__addr, __offset, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p);
+}
+
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
 __extension__ extern __inline void
@@ -13471,6 +13584,7 @@ __arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve
 {
   return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p);
 }
+
 #endif
 
 enum {
@@ -18034,6 +18148,8 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
+#endif /* MVE Integer.  */
+
 #define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2)
 #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -18045,8 +18161,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
-#endif /* MVE Integer.  */
-
 #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3)
 #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index c6e065d52d00e5f6b618e37c0b2df42c94e18f60..0f466e4cec295c1d791d675b52ff15e364d7016e 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -703,3 +703,9 @@ VAR3 (STRSS_P, vstrbq_scatter_offset_p_s, v16qi, v8hi, v4si)
 VAR3 (STRSU_P, vstrbq_scatter_offset_p_u, v16qi, v8hi, v4si)
 VAR1 (STRSBS_P, vstrwq_scatter_base_p_s, v4si)
 VAR1 (STRSBU_P, vstrwq_scatter_base_p_u, v4si)
+VAR1 (LDRGBS_Z, vldrwq_gather_base_z_s, v4si)
+VAR1 (LDRGBU_Z, vldrwq_gather_base_z_u, v4si)
+VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, v4si)
+VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si)
+VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si)
+VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 0e8b04f531c679b87d972265ed21ea5ec796e3a2..03a90ab3212954ea881c52e1b80bc69feed59a5d 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -8142,3 +8142,69 @@
    return "";
 }
   [(set_attr "length" "8")])
+
+;;
+;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u]
+;;
+(define_insn "mve_vldrbq_gather_offset_z_<supf><mode>"
+  [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
+	(unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")
+		       (match_operand:HI 3 "vpr_register_operand" "Up")]
+	 VLDRBGOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   ops[3] = operands[3];
+   if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
+     output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);
+   else
+     output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrbq_z_s vldrbq_z_u]
+;;
+(define_insn "mve_vldrbq_z_<supf><mode>"
+  [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
+		       (match_operand:HI 2 "vpr_register_operand" "Up")]
+	 VLDRBQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u]
+;;
+(define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
+  [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
+	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
+		      (match_operand:SI 2 "immediate_operand" "i")
+		      (match_operand:HI 3 "vpr_register_operand" "Up")]
+	 VLDRWGBQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[3];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..a51689f7740cd31de08108389df398970321aef6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_s16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
+
+int16x8_t
+foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..4b3b8ba3249388706008f68b9535c50f9c1ba5f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_s32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
+
+int32x4_t
+foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
new file mode 100644
index 0000000000000000000000000000000000000000..14e0f301d725cf5057e4799bfe5cfe59615c6377
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_s8 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
+
+int8x16_t
+foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b075001c8118c226ec8d2f4e434fe582fb51831
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_u16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
+
+uint16x8_t
+foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..c81ef6d365a65c7b1908f00c200ec1418b9c1adb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_u32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
+
+uint32x4_t
+foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
new file mode 100644
index 0000000000000000000000000000000000000000..3c91278ddc9d58dc782f0b5207bb116c756e7ea3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_u8 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
+
+uint8x16_t
+foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..c709db6c3ea4afb1228cd28c81ab51b5bf1b4803
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_s16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..aa47e239c4b81c57009232c9a0953388c1f89722
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_s32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
new file mode 100644
index 0000000000000000000000000000000000000000..85d7ef436673be3d90a5a7e44e1e81f8946bb154
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_s8 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..054305797ebf40bf66d09f25bdbb10439b463c60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_u16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..73b9ea19a6e0474cab181d8b355d77521e9b95da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_u32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
new file mode 100644
index 0000000000000000000000000000000000000000..3925c9f17a2d2a5d7439178312df20c6eeee4ae1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_u8 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..2e61760ede715efa0776fba6523b974e2becc08c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (uint32x4_t addr, mve_pred16_t p)
+{
+  return vldrwq_gather_base_z_s32 (addr, 4, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..a71c562722db6b5f97299ab8b64d044126f1b3ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t addr, mve_pred16_t p)
+{
+  return vldrwq_gather_base_z_u32 (addr, 4, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.u32"  }  } */

Comments

Kyrylo Tkachov March 18, 2020, 6:36 p.m. | #1
Hi Srinath,

> -----Original Message-----

> From: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>

> Sent: 18 March 2020 17:18

> To: gcc-patches@gcc.gnu.org

> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>

> Subject: [PATCH v2][ARM][GCC][4/5x]: MVE load intrinsics with zero(_z)

> suffix.

> 

> Hello Kyrill,

> 

> Following patch is the rebased version of v1.

> (version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-

> November/534333.html

> 

> ####

> 

> Hello,

> 

> This patch supports the following MVE ACLE load intrinsics with zero(_z)

> suffix.

> * ``_z`` (zero) which indicates false-predicated lanes are filled with zeroes,

> these are only used for load instructions.

> 

> vldrbq_gather_offset_z_s16, vldrbq_gather_offset_z_u8,

> vldrbq_gather_offset_z_s32, vldrbq_gather_offset_z_u16,

> vldrbq_gather_offset_z_u32, vldrbq_gather_offset_z_s8, vldrbq_z_s16,

> vldrbq_z_u8, vldrbq_z_s8, vldrbq_z_s32, vldrbq_z_u16, vldrbq_z_u32,

> vldrwq_gather_base_z_u32, vldrwq_gather_base_z_s32.

> 

> Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more

> details.

> [1]  https://developer.arm.com/architectures/instruction-sets/simd-

> isas/helium/mve-intrinsics

> 

> Regression tested on arm-none-eabi and found no regressions.

> 

> Ok for trunk?


Thanks, I've pushed this patch to master.
Kyrill

> 

> Thanks,

> Srinath.

> 

> gcc/ChangeLog:

> 

> 2019-11-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 	    Mihail Ionescu  <mihail.ionescu@arm.com>

> 	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

> 

> 	* config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin

> 	qualifier.

> 	(LDRGBU_Z_QUALIFIERS): Likewise.

> 	(LDRGS_Z_QUALIFIERS): Likewise.

> 	(LDRGU_Z_QUALIFIERS): Likewise.

> 	(LDRS_Z_QUALIFIERS): Likewise.

> 	(LDRU_Z_QUALIFIERS): Likewise.

> 	* config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define

> macro.

> 	(vldrbq_gather_offset_z_u8): Likewise.

> 	(vldrbq_gather_offset_z_s32): Likewise.

> 	(vldrbq_gather_offset_z_u16): Likewise.

> 	(vldrbq_gather_offset_z_u32): Likewise.

> 	(vldrbq_gather_offset_z_s8): Likewise.

> 	(vldrbq_z_s16): Likewise.

> 	(vldrbq_z_u8): Likewise.

> 	(vldrbq_z_s8): Likewise.

> 	(vldrbq_z_s32): Likewise.

> 	(vldrbq_z_u16): Likewise.

> 	(vldrbq_z_u32): Likewise.

> 	(vldrwq_gather_base_z_u32): Likewise.

> 	(vldrwq_gather_base_z_s32): Likewise.

> 	(__arm_vldrbq_gather_offset_z_s8): Define intrinsic.

> 	(__arm_vldrbq_gather_offset_z_s32): Likewise.

> 	(__arm_vldrbq_gather_offset_z_s16): Likewise.

> 	(__arm_vldrbq_gather_offset_z_u8): Likewise.

> 	(__arm_vldrbq_gather_offset_z_u32): Likewise.

> 	(__arm_vldrbq_gather_offset_z_u16): Likewise.

> 	(__arm_vldrbq_z_s8): Likewise.

> 	(__arm_vldrbq_z_s32): Likewise.

> 	(__arm_vldrbq_z_s16): Likewise.

> 	(__arm_vldrbq_z_u8): Likewise.

> 	(__arm_vldrbq_z_u32): Likewise.

> 	(__arm_vldrbq_z_u16): Likewise.

> 	(__arm_vldrwq_gather_base_z_s32): Likewise.

> 	(__arm_vldrwq_gather_base_z_u32): Likewise.

> 	(vldrbq_gather_offset_z): Define polymorphic variant.

> 	* config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use

> builtin

>         qualifier.

>         (LDRGBU_Z_QUALIFIERS): Likewise.

>         (LDRGS_Z_QUALIFIERS): Likewise.

>         (LDRGU_Z_QUALIFIERS): Likewise.

>         (LDRS_Z_QUALIFIERS): Likewise.

>         (LDRU_Z_QUALIFIERS): Likewise.

> 	* config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>):

> Define

> 	RTL pattern.

> 	(mve_vldrbq_z_<supf><mode>): Likewise.

> 	(mve_vldrwq_gather_base_z_<supf>v4si): Likewise.

> 

> gcc/testsuite/ChangeLog: Likewise.

> 

> 2019-11-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 	    Mihail Ionescu  <mihail.ionescu@arm.com>

> 	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

> 

> 	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New

> test.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c:

> Likewise.

> 	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c:

> Likewise.

> 

> 

> ###############     Attachment also inlined for ease of reply

> ###############

> 

> 

> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c

> index

> c87fa3118510e4de90ac9afe08608fb2315f4809..c3deb9efc8849019141b64305

> 43e93605fda4af4 100644

> --- a/gcc/config/arm/arm-builtins.c

> +++ b/gcc/config/arm/arm-builtins.c

> @@ -677,6 +677,40 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]

>    = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate};  #define

> LDRGBU_QUALIFIERS (arm_ldrgbu_qualifiers)

> 

> +static enum arm_type_qualifiers

> +arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]

> +  = { qualifier_none, qualifier_unsigned, qualifier_immediate,

> +      qualifier_unsigned};

> +#define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers)

> +

> +static enum arm_type_qualifiers

> +arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]

> +  = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,

> +      qualifier_unsigned};

> +#define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers)

> +

> +static enum arm_type_qualifiers

> +arm_ldrgs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]

> +  = { qualifier_none, qualifier_pointer, qualifier_unsigned,

> +      qualifier_unsigned};

> +#define LDRGS_Z_QUALIFIERS (arm_ldrgs_z_qualifiers)

> +

> +static enum arm_type_qualifiers

> +arm_ldrgu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]

> +  = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned,

> +      qualifier_unsigned};

> +#define LDRGU_Z_QUALIFIERS (arm_ldrgu_z_qualifiers)

> +

> +static enum arm_type_qualifiers

> +arm_ldrs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]

> +  = { qualifier_none, qualifier_pointer, qualifier_unsigned}; #define

> +LDRS_Z_QUALIFIERS (arm_ldrs_z_qualifiers)

> +

> +static enum arm_type_qualifiers

> +arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]

> +  = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned};

> +#define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers)

> +

>  /* End of Qualifier for MVE builtins.  */

> 

>     /* void ([T element type] *, T, immediate).  */ diff --git

> a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index

> deed81cfb31b2cf8f830076c5e44098c1abf2310..4570a0b16c37b11471a61f4b5

> 3686945063b4a55 100644

> --- a/gcc/config/arm/arm_mve.h

> +++ b/gcc/config/arm/arm_mve.h

> @@ -1744,6 +1744,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;

> #define vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p)

> __arm_vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p)

> #define vstrwq_scatter_base_p_s32(__addr,  __offset, __value, __p)

> __arm_vstrwq_scatter_base_p_s32(__addr,  __offset, __value, __p)  #define

> vstrwq_scatter_base_p_u32(__addr,  __offset, __value, __p)

> __arm_vstrwq_scatter_base_p_u32(__addr,  __offset, __value, __p)

> +#define vldrbq_gather_offset_z_s16(__base, __offset, __p)

> +__arm_vldrbq_gather_offset_z_s16(__base, __offset, __p) #define

> +vldrbq_gather_offset_z_u8(__base, __offset, __p)

> +__arm_vldrbq_gather_offset_z_u8(__base, __offset, __p) #define

> +vldrbq_gather_offset_z_s32(__base, __offset, __p)

> +__arm_vldrbq_gather_offset_z_s32(__base, __offset, __p) #define

> +vldrbq_gather_offset_z_u16(__base, __offset, __p)

> +__arm_vldrbq_gather_offset_z_u16(__base, __offset, __p) #define

> +vldrbq_gather_offset_z_u32(__base, __offset, __p)

> +__arm_vldrbq_gather_offset_z_u32(__base, __offset, __p) #define

> +vldrbq_gather_offset_z_s8(__base, __offset, __p)

> +__arm_vldrbq_gather_offset_z_s8(__base, __offset, __p) #define

> +vldrbq_z_s16(__base, __p) __arm_vldrbq_z_s16(__base, __p) #define

> +vldrbq_z_u8(__base, __p) __arm_vldrbq_z_u8(__base, __p) #define

> +vldrbq_z_s8(__base, __p) __arm_vldrbq_z_s8(__base, __p) #define

> +vldrbq_z_s32(__base, __p) __arm_vldrbq_z_s32(__base, __p) #define

> +vldrbq_z_u16(__base, __p) __arm_vldrbq_z_u16(__base, __p) #define

> +vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p) #define

> +vldrwq_gather_base_z_u32(__addr,  __offset, __p)

> +__arm_vldrwq_gather_base_z_u32(__addr,  __offset, __p) #define

> +vldrwq_gather_base_z_s32(__addr,  __offset, __p)

> +__arm_vldrwq_gather_base_z_s32(__addr,  __offset, __p)

>  #endif

> 

>  __extension__ extern __inline void

> @@ -11330,6 +11344,105 @@ __arm_vstrwq_scatter_base_p_u32

> (uint32x4_t __addr, const int __offset, uint32x4  {

>    __builtin_mve_vstrwq_scatter_base_p_uv4si (__addr, __offset, __value,

> __p);  }

> +

> +__extension__ extern __inline int8x16_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_gather_offset_z_s8 (int8_t const * __base, uint8x16_t

> +__offset, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_gather_offset_z_sv16qi

> +((__builtin_neon_qi *) __base, __offset, __p); }

> +

> +__extension__ extern __inline int32x4_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_gather_offset_z_s32 (int8_t const * __base, uint32x4_t

> +__offset, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_gather_offset_z_sv4si ((__builtin_neon_qi

> +*) __base, __offset, __p); }

> +

> +__extension__ extern __inline int16x8_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_gather_offset_z_s16 (int8_t const * __base, uint16x8_t

> +__offset, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_gather_offset_z_sv8hi ((__builtin_neon_qi

> +*) __base, __offset, __p); }

> +

> +__extension__ extern __inline uint8x16_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_gather_offset_z_u8 (uint8_t const * __base, uint8x16_t

> +__offset, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_gather_offset_z_uv16qi

> +((__builtin_neon_qi *) __base, __offset, __p); }

> +

> +__extension__ extern __inline uint32x4_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_gather_offset_z_u32 (uint8_t const * __base, uint32x4_t

> +__offset, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_gather_offset_z_uv4si ((__builtin_neon_qi

> +*) __base, __offset, __p); }

> +

> +__extension__ extern __inline uint16x8_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_gather_offset_z_u16 (uint8_t const * __base, uint16x8_t

> +__offset, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_gather_offset_z_uv8hi ((__builtin_neon_qi

> +*) __base, __offset, __p); }

> +

> +__extension__ extern __inline int8x16_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_z_s8 (int8_t const * __base, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_z_sv16qi ((__builtin_neon_qi *) __base,

> +__p); }

> +

> +__extension__ extern __inline int32x4_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_z_s32 (int8_t const * __base, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_z_sv4si ((__builtin_neon_qi *) __base,

> +__p); }

> +

> +__extension__ extern __inline int16x8_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_z_s16 (int8_t const * __base, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_z_sv8hi ((__builtin_neon_qi *) __base,

> +__p); }

> +

> +__extension__ extern __inline uint8x16_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_z_u8 (uint8_t const * __base, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_z_uv16qi ((__builtin_neon_qi *) __base,

> +__p); }

> +

> +__extension__ extern __inline uint32x4_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_z_u32 (uint8_t const * __base, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_z_uv4si ((__builtin_neon_qi *) __base,

> +__p); }

> +

> +__extension__ extern __inline uint16x8_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrbq_z_u16 (uint8_t const * __base, mve_pred16_t __p) {

> +  return __builtin_mve_vldrbq_z_uv8hi ((__builtin_neon_qi *) __base,

> +__p); }

> +

> +__extension__ extern __inline int32x4_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrwq_gather_base_z_s32 (uint32x4_t __addr, const int __offset,

> +mve_pred16_t __p) {

> +  return __builtin_mve_vldrwq_gather_base_z_sv4si (__addr, __offset,

> +__p); }

> +

> +__extension__ extern __inline uint32x4_t __attribute__

> +((__always_inline__, __gnu_inline__, __artificial__))

> +__arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr, const int __offset,

> +mve_pred16_t __p) {

> +  return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset,

> +__p); }

> +

>  #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */

> 

>  __extension__ extern __inline void

> @@ -13471,6 +13584,7 @@ __arm_vsubq_m_n_f16 (float16x8_t __inactive,

> float16x8_t __a, float16_t __b, mve  {

>    return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p);  }

> +

>  #endif

> 

>  enum {

> @@ -18034,6 +18148,8 @@ extern void *__ARM_undef;

>    int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32

> (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \

>    int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32

> (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})

> 

> +#endif /* MVE Integer.  */

> +

>  #define vldrbq_gather_offset_z(p0,p1,p2)

> __arm_vldrbq_gather_offset_z(p0,p1,p2)

>  #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 =

> (p0); \

>    __typeof(p1) __p1 = (p1); \

> @@ -18045,8 +18161,6 @@ extern void *__ARM_undef;

>    int

> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]:

> __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint8_t

> const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \

>    int

> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]:

> __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint8_t

> const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})

> 

> -#endif /* MVE Integer.  */

> -

>  #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3)

> #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \

>    __typeof(p1) __p1 = (p1); \

> diff --git a/gcc/config/arm/arm_mve_builtins.def

> b/gcc/config/arm/arm_mve_builtins.def

> index

> c6e065d52d00e5f6b618e37c0b2df42c94e18f60..0f466e4cec295c1d791d675b

> 52ff15e364d7016e 100644

> --- a/gcc/config/arm/arm_mve_builtins.def

> +++ b/gcc/config/arm/arm_mve_builtins.def

> @@ -703,3 +703,9 @@ VAR3 (STRSS_P, vstrbq_scatter_offset_p_s, v16qi,

> v8hi, v4si)

>  VAR3 (STRSU_P, vstrbq_scatter_offset_p_u, v16qi, v8hi, v4si)

>  VAR1 (STRSBS_P, vstrwq_scatter_base_p_s, v4si)

>  VAR1 (STRSBU_P, vstrwq_scatter_base_p_u, v4si)

> +VAR1 (LDRGBS_Z, vldrwq_gather_base_z_s, v4si)

> +VAR1 (LDRGBU_Z, vldrwq_gather_base_z_u, v4si)

> +VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, v4si)

> +VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si)

> +VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si)

> +VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si)

> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index

> 0e8b04f531c679b87d972265ed21ea5ec796e3a2..03a90ab3212954ea881c52e

> 1b80bc69feed59a5d 100644

> --- a/gcc/config/arm/mve.md

> +++ b/gcc/config/arm/mve.md

> @@ -8142,3 +8142,69 @@

>     return "";

>  }

>    [(set_attr "length" "8")])

> +

> +;;

> +;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u] ;; (define_insn

> +"mve_vldrbq_gather_offset_z_<supf><mode>"

> +  [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")

> +	(unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1

> "memory_operand" "Us")

> +		       (match_operand:MVE_2 2 "s_register_operand" "w")

> +		       (match_operand:HI 3 "vpr_register_operand" "Up")]

> +	 VLDRBGOQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[4];

> +   ops[0] = operands[0];

> +   ops[1] = operands[1];

> +   ops[2] = operands[2];

> +   ops[3] = operands[3];

> +   if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)

> +     output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);

> +   else

> +     output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0,

> [%m1, %q2]",ops);

> +   return "";

> +}

> +  [(set_attr "length" "8")])

> +

> +;;

> +;; [vldrbq_z_s vldrbq_z_u]

> +;;

> +(define_insn "mve_vldrbq_z_<supf><mode>"

> +  [(set (match_operand:MVE_2 0 "s_register_operand" "=w")

> +	(unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1

> "memory_operand" "Us")

> +		       (match_operand:HI 2 "vpr_register_operand" "Up")]

> +	 VLDRBQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[2];

> +   int regno = REGNO (operands[0]);

> +   ops[0] = gen_rtx_REG (TImode, regno);

> +   ops[1]  = operands[1];

> +   output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);

> +   return "";

> +}

> +  [(set_attr "length" "8")])

> +

> +;;

> +;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u] ;; (define_insn

> +"mve_vldrwq_gather_base_z_<supf>v4si"

> +  [(set (match_operand:V4SI 0 "s_register_operand" "=&w")

> +	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")

> +		      (match_operand:SI 2 "immediate_operand" "i")

> +		      (match_operand:HI 3 "vpr_register_operand" "Up")]

> +	 VLDRWGBQ))

> +  ]

> +  "TARGET_HAVE_MVE"

> +{

> +   rtx ops[3];

> +   ops[0] = operands[0];

> +   ops[1] = operands[1];

> +   ops[2] = operands[2];

> +   output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);

> +   return "";

> +}

> +  [(set_attr "length" "8")])

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..a51689f7740cd31de081083

> 89df398970321aef6

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z

> +++ _s16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z_s16 (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.s16"  }  } */

> +

> +int16x8_t

> +foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.s16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..4b3b8ba3249388706008f68

> b9535c50f9c1ba5f4

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z

> +++ _s32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z_s32 (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.s32"  }  } */

> +

> +int32x4_t

> +foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.s32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..14e0f301d725cf5057e4799

> bfe5cfe59615c6377

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z

> +++ _s8.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int8x16_t

> +foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z_s8 (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.u8"  }  } */

> +

> +int8x16_t

> +foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.u8"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..7b075001c8118c226ec8d2f

> 4e434fe582fb51831

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z

> +++ _u16.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z_u16 (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.u16"  }  } */

> +

> +uint16x8_t

> +foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.u16"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..c81ef6d365a65c7b1908f00c

> 200ec1418b9c1adb

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z

> +++ _u32.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z_u32 (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.u32"  }  } */

> +

> +uint32x4_t

> +foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.u32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..3c91278ddc9d58dc782f0b5

> 207bb116c756e7ea3

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z

> +++ _u8.c

> @@ -0,0 +1,22 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint8x16_t

> +foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z_u8 (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.u8"  }  } */

> +

> +uint8x16_t

> +foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) {

> +  return vldrbq_gather_offset_z (base, offset, p); }

> +

> +/* { dg-final { scan-assembler "vldrbt.u8"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..c709db6c3ea4afb1228cd28

> c81ab51b5bf1b4803

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int16x8_t

> +foo (int8_t const * base, mve_pred16_t p) {

> +  return vldrbq_z_s16 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrbt.s16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..aa47e239c4b81c57009232c

> 9a0953388c1f89722

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (int8_t const * base, mve_pred16_t p) {

> +  return vldrbq_z_s32 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrbt.s32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..85d7ef436673be3d90a5a7e

> 44e1e81f8946bb154

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int8x16_t

> +foo (int8_t const * base, mve_pred16_t p) {

> +  return vldrbq_z_s8 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrbt.s8"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..054305797ebf40bf66d09f2

> 5bdbb10439b463c60

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint16x8_t

> +foo (uint8_t const * base, mve_pred16_t p) {

> +  return vldrbq_z_u16 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrbt.u16"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..73b9ea19a6e0474cab181d

> 8b355d77521e9b95da

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint8_t const * base, mve_pred16_t p) {

> +  return vldrbq_z_u32 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrbt.u32"  }  } */

> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..3925c9f17a2d2a5d7439178

> 312df20c6eeee4ae1

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint8x16_t

> +foo (uint8_t const * base, mve_pred16_t p) {

> +  return vldrbq_z_u8 (base, p);

> +}

> +

> +/* { dg-final { scan-assembler "vldrbt.u8"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..2e61760ede715efa0776fba

> 6523b974e2becc08c

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s

> +++ 32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +int32x4_t

> +foo (uint32x4_t addr, mve_pred16_t p)

> +{

> +  return vldrwq_gather_base_z_s32 (addr, 4, p); }

> +

> +/* { dg-final { scan-assembler "vldrwt.u32"  }  } */

> diff --git

> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c

> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c

> new file mode 100644

> index

> 0000000000000000000000000000000000000000..a71c562722db6b5f97299ab

> 8b64d044126f1b3ef

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u

> +++ 32.c

> @@ -0,0 +1,14 @@

> +/* { dg-do compile  } */

> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */

> +/* { dg-add-options arm_v8_1m_mve } */

> +/* { dg-additional-options "-O2" } */

> +

> +#include "arm_mve.h"

> +

> +uint32x4_t

> +foo (uint32x4_t addr, mve_pred16_t p)

> +{

> +  return vldrwq_gather_base_z_u32 (addr, 4, p); }

> +

> +/* { dg-final { scan-assembler "vldrwt.u32"  }  } */

Patch

diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index c87fa3118510e4de90ac9afe08608fb2315f4809..c3deb9efc8849019141b6430543e93605fda4af4 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -677,6 +677,40 @@  arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate};
 #define LDRGBU_QUALIFIERS (arm_ldrgbu_qualifiers)
 
+static enum arm_type_qualifiers
+arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_unsigned, qualifier_immediate,
+      qualifier_unsigned};
+#define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
+      qualifier_unsigned};
+#define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrgs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_pointer, qualifier_unsigned,
+      qualifier_unsigned};
+#define LDRGS_Z_QUALIFIERS (arm_ldrgs_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrgu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned,
+      qualifier_unsigned};
+#define LDRGU_Z_QUALIFIERS (arm_ldrgu_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_pointer, qualifier_unsigned};
+#define LDRS_Z_QUALIFIERS (arm_ldrs_z_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned};
+#define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers)
+
 /* End of Qualifier for MVE builtins.  */
 
    /* void ([T element type] *, T, immediate).  */
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index deed81cfb31b2cf8f830076c5e44098c1abf2310..4570a0b16c37b11471a61f4b53686945063b4a55 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -1744,6 +1744,20 @@  typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
 #define vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p) __arm_vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p)
 #define vstrwq_scatter_base_p_s32(__addr,  __offset, __value, __p) __arm_vstrwq_scatter_base_p_s32(__addr,  __offset, __value, __p)
 #define vstrwq_scatter_base_p_u32(__addr,  __offset, __value, __p) __arm_vstrwq_scatter_base_p_u32(__addr,  __offset, __value, __p)
+#define vldrbq_gather_offset_z_s16(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s16(__base, __offset, __p)
+#define vldrbq_gather_offset_z_u8(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u8(__base, __offset, __p)
+#define vldrbq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s32(__base, __offset, __p)
+#define vldrbq_gather_offset_z_u16(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u16(__base, __offset, __p)
+#define vldrbq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrbq_gather_offset_z_u32(__base, __offset, __p)
+#define vldrbq_gather_offset_z_s8(__base, __offset, __p) __arm_vldrbq_gather_offset_z_s8(__base, __offset, __p)
+#define vldrbq_z_s16(__base, __p) __arm_vldrbq_z_s16(__base, __p)
+#define vldrbq_z_u8(__base, __p) __arm_vldrbq_z_u8(__base, __p)
+#define vldrbq_z_s8(__base, __p) __arm_vldrbq_z_s8(__base, __p)
+#define vldrbq_z_s32(__base, __p) __arm_vldrbq_z_s32(__base, __p)
+#define vldrbq_z_u16(__base, __p) __arm_vldrbq_z_u16(__base, __p)
+#define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p)
+#define vldrwq_gather_base_z_u32(__addr,  __offset, __p) __arm_vldrwq_gather_base_z_u32(__addr,  __offset, __p)
+#define vldrwq_gather_base_z_s32(__addr,  __offset, __p) __arm_vldrwq_gather_base_z_s32(__addr,  __offset, __p)
 #endif
 
 __extension__ extern __inline void
@@ -11330,6 +11344,105 @@  __arm_vstrwq_scatter_base_p_u32 (uint32x4_t __addr, const int __offset, uint32x4
 {
   __builtin_mve_vstrwq_scatter_base_p_uv4si (__addr, __offset, __value, __p);
 }
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_s8 (int8_t const * __base, uint8x16_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_sv16qi ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_s32 (int8_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_sv4si ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_s16 (int8_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_sv8hi ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_u8 (uint8_t const * __base, uint8x16_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_uv16qi ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_u32 (uint8_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_uv4si ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_gather_offset_z_u16 (uint8_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_gather_offset_z_uv8hi ((__builtin_neon_qi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_s8 (int8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_sv16qi ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_s32 (int8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_sv4si ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_s16 (int8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_sv8hi ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_u8 (uint8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_uv16qi ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_u32 (uint8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_uv4si ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrbq_z_u16 (uint8_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrbq_z_uv8hi ((__builtin_neon_qi *) __base, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_base_z_s32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_gather_base_z_sv4si (__addr, __offset, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p);
+}
+
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
 __extension__ extern __inline void
@@ -13471,6 +13584,7 @@  __arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve
 {
   return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p);
 }
+
 #endif
 
 enum {
@@ -18034,6 +18148,8 @@  extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
+#endif /* MVE Integer.  */
+
 #define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2)
 #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -18045,8 +18161,6 @@  extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
-#endif /* MVE Integer.  */
-
 #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3)
 #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index c6e065d52d00e5f6b618e37c0b2df42c94e18f60..0f466e4cec295c1d791d675b52ff15e364d7016e 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -703,3 +703,9 @@  VAR3 (STRSS_P, vstrbq_scatter_offset_p_s, v16qi, v8hi, v4si)
 VAR3 (STRSU_P, vstrbq_scatter_offset_p_u, v16qi, v8hi, v4si)
 VAR1 (STRSBS_P, vstrwq_scatter_base_p_s, v4si)
 VAR1 (STRSBU_P, vstrwq_scatter_base_p_u, v4si)
+VAR1 (LDRGBS_Z, vldrwq_gather_base_z_s, v4si)
+VAR1 (LDRGBU_Z, vldrwq_gather_base_z_u, v4si)
+VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, v4si)
+VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si)
+VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si)
+VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 0e8b04f531c679b87d972265ed21ea5ec796e3a2..03a90ab3212954ea881c52e1b80bc69feed59a5d 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -8142,3 +8142,69 @@ 
    return "";
 }
   [(set_attr "length" "8")])
+
+;;
+;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u]
+;;
+(define_insn "mve_vldrbq_gather_offset_z_<supf><mode>"
+  [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
+	(unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")
+		       (match_operand:HI 3 "vpr_register_operand" "Up")]
+	 VLDRBGOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   ops[3] = operands[3];
+   if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
+     output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);
+   else
+     output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrbq_z_s vldrbq_z_u]
+;;
+(define_insn "mve_vldrbq_z_<supf><mode>"
+  [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
+		       (match_operand:HI 2 "vpr_register_operand" "Up")]
+	 VLDRBQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u]
+;;
+(define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
+  [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
+	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
+		      (match_operand:SI 2 "immediate_operand" "i")
+		      (match_operand:HI 3 "vpr_register_operand" "Up")]
+	 VLDRWGBQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[3];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..a51689f7740cd31de08108389df398970321aef6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_s16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
+
+int16x8_t
+foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..4b3b8ba3249388706008f68b9535c50f9c1ba5f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_s32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
+
+int32x4_t
+foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
new file mode 100644
index 0000000000000000000000000000000000000000..14e0f301d725cf5057e4799bfe5cfe59615c6377
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_s8 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
+
+int8x16_t
+foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b075001c8118c226ec8d2f4e434fe582fb51831
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_u16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
+
+uint16x8_t
+foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..c81ef6d365a65c7b1908f00c200ec1418b9c1adb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_u32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
+
+uint32x4_t
+foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
new file mode 100644
index 0000000000000000000000000000000000000000..3c91278ddc9d58dc782f0b5207bb116c756e7ea3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z_u8 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
+
+uint8x16_t
+foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+{
+  return vldrbq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..c709db6c3ea4afb1228cd28c81ab51b5bf1b4803
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_s16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..aa47e239c4b81c57009232c9a0953388c1f89722
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_s32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
new file mode 100644
index 0000000000000000000000000000000000000000..85d7ef436673be3d90a5a7e44e1e81f8946bb154
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_s8 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.s8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..054305797ebf40bf66d09f25bdbb10439b463c60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_u16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..73b9ea19a6e0474cab181d8b355d77521e9b95da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_u32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
new file mode 100644
index 0000000000000000000000000000000000000000..3925c9f17a2d2a5d7439178312df20c6eeee4ae1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8_t const * base, mve_pred16_t p)
+{
+  return vldrbq_z_u8 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..2e61760ede715efa0776fba6523b974e2becc08c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (uint32x4_t addr, mve_pred16_t p)
+{
+  return vldrwq_gather_base_z_s32 (addr, 4, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..a71c562722db6b5f97299ab8b64d044126f1b3ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t addr, mve_pred16_t p)
+{
+  return vldrwq_gather_base_z_u32 (addr, 4, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.u32"  }  } */