[committed] amdgcn: Fix vector compare modes

Message ID 7383a62d-1b87-6e14-e2cd-69481b09896d@codesourcery.com
State New
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  • [committed] amdgcn: Fix vector compare modes
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Commit Message

Andrew Stubbs March 18, 2020, 1:04 p.m.
This patch fixes a problem which has existed for a long time, but showed 
itself again after my previous patch to add conditional vector operators.

The solution is to set STORE_FLAG_VALUE properly. (More details in the 
patch header.)

Andrew

Patch

amdgcn: Fix vector compare modes

The GCN VCC register has 64 CC values in one registers, one bit for each
vector lane.

Previously we avoided problems with invalid optimizations by not declaring
a mode for the comparison operators, but it turns out that causes other
problems (and build warnings).

Instead, the optimization issues can be avoided by setting
STORE_REGISTER_VALUE to -1, meaning that all the bits are significant.

(It would be better if we could set STORE_REGISTER_VALUE according to the
known mask or vector size, but we can't.)

2020-03-18  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
	(vec_cmp<mode>di_dup): Likewise.
	* config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 68d89fadc9e..d3620688a9c 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2549,7 +2549,7 @@ 
 
 (define_insn "vec_cmp<mode>di"
   [(set (match_operand:DI 0 "register_operand"	      "=cV,cV,  e, e,Sg,Sg")
-	(match_operator 1 "gcn_fp_compare_operator"
+	(match_operator:DI 1 "gcn_fp_compare_operator"
 	  [(match_operand:VCMP_MODE 2 "gcn_alu_operand"
 						      "vSv, B,vSv, B, v,vA")
 	   (match_operand:VCMP_MODE 3 "gcn_vop3_operand"
@@ -2658,7 +2658,7 @@ 
 
 (define_insn "vec_cmp<mode>di_dup"
   [(set (match_operand:DI 0 "register_operand"		   "=cV,cV, e,e,Sg")
-	(match_operator 1 "gcn_fp_compare_operator"
+	(match_operator:DI 1 "gcn_fp_compare_operator"
 	  [(vec_duplicate:VCMP_MODE
 	     (match_operand:<SCALAR_MODE> 2 "gcn_alu_operand"
 							   " Sv, B,Sv,B, A"))
diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h
index 0efa99f3bee..9993a995d05 100644
--- a/gcc/config/gcn/gcn.h
+++ b/gcc/config/gcn/gcn.h
@@ -607,6 +607,10 @@  enum gcn_builtin_codes
 #define SLOW_BYTE_ACCESS 0
 #define WORD_REGISTER_OPERATIONS 1
 
+/* Flag values are either BImode or DImode, but either way the compiler
+   should assume that all the bits are live.  */
+#define STORE_FLAG_VALUE -1
+
 /* Definitions for register eliminations.
 
    This is an array of structures.  Each structure initializes one pair