More 1 << 31 signed overflows

Message ID 20200310113511.GV5384@bubble.grove.modra.org
State New
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Series
  • More 1 << 31 signed overflows
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Commit Message

Alan Modra March 10, 2020, 11:35 a.m.
* config/tc-csky.c (get_operand_value): Rewrite 1 << 31 expressions
	to avoid signed overflow.
	* config/tc-mcore.c (md_assemble): Likewise.
	* config/tc-mips.c (gpr_read_mask, gpr_write_mask): Likewise.
	* config/tc-nds32.c (SET_ADDEND): Likewise.
	* config/tc-nios2.c (nios2_assemble_arg_R): Likewise.


-- 
Alan Modra
Australia Development Lab, IBM

Patch

diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index d03b817e62..83fca2af73 100644
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -3166,7 +3166,7 @@  get_operand_value (struct csky_opcode_info *op,
     case OPRND_TYPE_IMM5b_1_31:
       return is_imm_over_range (oper, 1, 31, -1);
     case OPRND_TYPE_IMM5b_POWER:
-      if (is_imm_over_range (oper, 1, ~(1 << 31), 1 << 31))
+      if (is_imm_over_range (oper, 1, (1u << 31) - 1, 1u << 31))
 	{
 	  int log;
 	  int val = csky_insn.val[csky_insn.idx - 1];
@@ -3179,7 +3179,7 @@  get_operand_value (struct csky_opcode_info *op,
 
       /* This type for "mgeni" in csky v1 ISA.  */
       case OPRND_TYPE_IMM5b_7_31_POWER:
-	if (is_imm_over_range (oper, 1, ~(1 << 31), 1 << 31))
+	if (is_imm_over_range (oper, 1, (1u << 31) - 1, 1u << 31))
 	  {
 	    int log;
 	    int val = csky_insn.val[csky_insn.idx - 1];
diff --git a/gas/config/tc-mcore.c b/gas/config/tc-mcore.c
index a22ce814d1..b849a7c90f 100644
--- a/gas/config/tc-mcore.c
+++ b/gas/config/tc-mcore.c
@@ -1088,7 +1088,7 @@  md_assemble (char * str)
 
       if (* op_end == ',')
 	{
-	  op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31);
+	  op_end = parse_imm (op_end + 1, & reg, 1, 1u << 31);
 	  /* Further restrict the immediate to a power of two.  */
 	  if ((reg & (reg - 1)) == 0)
 	    reg = mylog2 (reg);
@@ -1144,7 +1144,7 @@  md_assemble (char * str)
 
       if (* op_end == ',')
 	{
-	  op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31);
+	  op_end = parse_imm (op_end + 1, & reg, 1, 1u << 31);
 
 	  /* Further restrict the immediate to a power of two.  */
 	  if ((reg & (reg - 1)) == 0)
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 9f78b5a89e..31acb77d78 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -4778,7 +4778,7 @@  gpr_read_mask (const struct mips_cl_insn *ip)
   if (pinfo2 & INSN2_READ_SP)
     mask |= 1 << SP;
   if (pinfo2 & INSN2_READ_GPR_31)
-    mask |= 1 << 31;
+    mask |= 1u << 31;
   /* Don't include register 0.  */
   return mask & ~1;
 }
@@ -4797,7 +4797,7 @@  gpr_write_mask (const struct mips_cl_insn *ip)
   if (pinfo & INSN_WRITE_GPR_24)
     mask |= 1 << 24;
   if (pinfo & INSN_WRITE_GPR_31)
-    mask |= 1 << 31;
+    mask |= 1u << 31;
   if (pinfo & INSN_UDI)
     /* UDI instructions have traditionally been assumed to write to RD.  */
     mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
diff --git a/gas/config/tc-nds32.c b/gas/config/tc-nds32.c
index 0f5973d41b..893b61fe26 100644
--- a/gas/config/tc-nds32.c
+++ b/gas/config/tc-nds32.c
@@ -5278,8 +5278,8 @@  nds32_elf_sethi_range (struct nds32_relocs_pattern *pattern)
    not, optimize option, 16 bit instruction is enable.  */
 
 #define SET_ADDEND(size, convertible, optimize, insn16_on) \
-  (((size) & 0xff) | ((convertible) ? 1 << 31 : 0) \
-   | ((optimize) ? 1<< 30 : 0) | (insn16_on ? 1 << 29 : 0))
+  (((size) & 0xff) | ((convertible) ? 1u << 31 : 0) \
+   | ((optimize) ? 1 << 30 : 0) | (insn16_on ? 1 << 29 : 0))
 #define MAC_COMBO (E_NDS32_HAS_FPU_MAC_INST|E_NDS32_HAS_MAC_DX_INST)
 
 static void
diff --git a/gas/config/tc-nios2.c b/gas/config/tc-nios2.c
index a7039e4c17..52cfb985c1 100644
--- a/gas/config/tc-nios2.c
+++ b/gas/config/tc-nios2.c
@@ -2710,7 +2710,7 @@  nios2_assemble_arg_R (const char *token, nios2_insn_infoS *insn)
 	  mask = (reglist & 0x00ffc000) >> 14;
 	  if (reglist & (1 << 28))
 	    mask |= 1 << 10;
-	  if (reglist & (1 << 31))
+	  if (reglist & (1u << 31))
 	    mask |= 1 << 11;
 	}
       insn->insn_code |= SET_IW_F1X4L17_REGMASK (mask);