[v2,2/2] RISC-V: Support assembler modifier %got_pcrel_hi.

Message ID 1583298485-8506-3-git-send-email-nelson.chu@sifive.com
State New
Headers show
Series
  • Add description for the RISC-V relocatable modifiers in as doc
Related show

Commit Message

Nelson Chu March 4, 2020, 5:08 a.m.
gas/
	* config/tc-riscv.c: Support the modifier %got_pcrel_hi.
	* doc/c-riscv.texi: Add documentation.
	* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
	modifier %got_pcrel_hi.
	* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
	* testsuite/gas/riscv/relax-reloc.d: Likewise.
	* testsuite/gas/riscv/relax-reloc.s: Likewise.
---
 gas/config/tc-riscv.c                    |  1 +
 gas/doc/c-riscv.texi                     | 17 +++++++++++++++++
 gas/testsuite/gas/riscv/no-relax-reloc.d |  4 +++-
 gas/testsuite/gas/riscv/no-relax-reloc.s |  7 +++++--
 gas/testsuite/gas/riscv/relax-reloc.d    |  7 +++++--
 gas/testsuite/gas/riscv/relax-reloc.s    |  7 +++++--
 6 files changed, 36 insertions(+), 7 deletions(-)

-- 
2.7.4

Comments

Fangrui Song March 8, 2020, 5:46 a.m. | #1
Is "assembler operator" more conventional than "assembler modifier"?

On 2020-03-03, Nelson Chu wrote:
>	gas/

>	* config/tc-riscv.c: Support the modifier %got_pcrel_hi.

>	* doc/c-riscv.texi: Add documentation.

>	* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new

>	modifier %got_pcrel_hi.

>	* testsuite/gas/riscv/no-relax-reloc.s: Likewise.

>	* testsuite/gas/riscv/relax-reloc.d: Likewise.

>	* testsuite/gas/riscv/relax-reloc.s: Likewise.

>---

> gas/config/tc-riscv.c                    |  1 +

> gas/doc/c-riscv.texi                     | 17 +++++++++++++++++

> gas/testsuite/gas/riscv/no-relax-reloc.d |  4 +++-

> gas/testsuite/gas/riscv/no-relax-reloc.s |  7 +++++--

> gas/testsuite/gas/riscv/relax-reloc.d    |  7 +++++--

> gas/testsuite/gas/riscv/relax-reloc.s    |  7 +++++--

> 6 files changed, 36 insertions(+), 7 deletions(-)

>

>diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c

>index ddd4d14..168561e 100644

>--- a/gas/config/tc-riscv.c

>+++ b/gas/config/tc-riscv.c

>@@ -1308,6 +1308,7 @@ static const struct percent_op_match percent_op_utype[] =

> {

>   {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},

>   {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},

>+  {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},

>   {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},

>   {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},

>   {"%hi", BFD_RELOC_RISCV_HI20},

>diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi

>index 6e932dc..488cf56 100644

>--- a/gas/doc/c-riscv.texi

>+++ b/gas/doc/c-riscv.texi

>@@ -257,6 +257,23 @@ Or you can use the pseudo lla/lw/sw/... instruction to do this.

> 	lla  a0, @var{symbol}

> @end smallexample

>

>+@item %got_pcrel_hi(@var{symbol})

>+The high 20 bits of relative address between pc and the GOT entry of

>+@var{symbol}.  This is usually used with the %pcrel_lo modifier to access

>+the GOT entry.

>+

>+@smallexample

>+@var{label}:

>+	auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20

>+	addi       a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I

>+

>+@var{label}:

>+	auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20

>+	load/store a0, %pcrel_lo(@var{label})(a0)  // R_RISCV_PCREL_LO12_I/S

>+@end smallexample

>+

>+Also, the pseudo la instruction with PIC has similar behavior.

>+

> @item %tprel_add(@var{symbol})

> This is used purely to associate the R_RISCV_TPREL_ADD relocation for

> TLS relaxation.  This one is only valid as the fourth operand to the normally

>diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d

>index 62f28e0..c2ca1aa 100644

>--- a/gas/testsuite/gas/riscv/no-relax-reloc.d

>+++ b/gas/testsuite/gas/riscv/no-relax-reloc.d

>@@ -9,4 +9,6 @@ RELOCATION RECORDS FOR .*

> 0+4 R_RISCV_LO12_I.*

> 0+8 R_RISCV_PCREL_HI20.*

> 0+c R_RISCV_PCREL_LO12_I.*

>-0+10 R_RISCV_CALL.*

>+0+10 R_RISCV_GOT_HI20.*

>+0+14 R_RISCV_PCREL_LO12_I.*

>+0+18 R_RISCV_CALL.*

>diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s

>index 7f1a484..2aab995 100644

>--- a/gas/testsuite/gas/riscv/no-relax-reloc.s

>+++ b/gas/testsuite/gas/riscv/no-relax-reloc.s

>@@ -2,7 +2,10 @@ target:

> 	lui	a5,%hi(target)

> 	lw	a5,%lo(target)(a5)

>

>-        .LA0: auipc     a5,%pcrel_hi(bar)

>-        lw      a0,%pcrel_lo(.LA0)(a5)

>+	.LA0: auipc     a5,%pcrel_hi(symbol1)

>+	lw      a0,%pcrel_lo(.LA0)(a5)

>+

>+	.LA1: auipc     a5,%got_pcrel_hi(symbol2)

>+	lw      a0,%pcrel_lo(.LA1)(a5)

>

> 	call target

>diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d

>index f5f592c..623218e 100644

>--- a/gas/testsuite/gas/riscv/relax-reloc.d

>+++ b/gas/testsuite/gas/riscv/relax-reloc.d

>@@ -13,5 +13,8 @@ RELOCATION RECORDS FOR .*

> 0+8 R_RISCV_RELAX.*

> 0+c R_RISCV_PCREL_LO12_I.*

> 0+c R_RISCV_RELAX.*

>-0+10 R_RISCV_CALL.*

>-0+10 R_RISCV_RELAX.*

>+0+10 R_RISCV_GOT_HI20.*

>+0+14 R_RISCV_PCREL_LO12_I.*

>+0+14 R_RISCV_RELAX.*

>+0+18 R_RISCV_CALL.*

>+0+18 R_RISCV_RELAX.*

>diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s

>index 7f1a484..2aab995 100644

>--- a/gas/testsuite/gas/riscv/relax-reloc.s

>+++ b/gas/testsuite/gas/riscv/relax-reloc.s

>@@ -2,7 +2,10 @@ target:

> 	lui	a5,%hi(target)

> 	lw	a5,%lo(target)(a5)

>

>-        .LA0: auipc     a5,%pcrel_hi(bar)

>-        lw      a0,%pcrel_lo(.LA0)(a5)

>+	.LA0: auipc     a5,%pcrel_hi(symbol1)

>+	lw      a0,%pcrel_lo(.LA0)(a5)

>+

>+	.LA1: auipc     a5,%got_pcrel_hi(symbol2)

>+	lw      a0,%pcrel_lo(.LA1)(a5)

>

> 	call target
Nelson Chu March 9, 2020, 1:41 a.m. | #2
Hi MaskRay,

On Sun, Mar 8, 2020 at 1:46 PM Fangrui Song <i@maskray.me> wrote:
>

> Is "assembler operator" more conventional than "assembler modifier"?

>


In GNU assembler document, many targets use similar names for these.
ARC calls this
"Assembler Modifiers", AVR and LM32 call this "Relocatable Expression
Modifiers".  However, many targets use "Symbolic Operand Modifiers",
including M32C, M68HC11(12), RL78, RX, TILE-Gx and TILEPro.  I also
see CR16 calls this "Operand Qualifiers".  For our RISC-V asm manual,
we call this "Assembler Relocation Functions".  I'm not sure which one
is better, but it seems like the "Symbolic Operand Modifiers" is more
clear to understand what it means?

Thanks
Nelson

Patch

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ddd4d14..168561e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1308,6 +1308,7 @@  static const struct percent_op_match percent_op_utype[] =
 {
   {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
   {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
+  {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
   {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
   {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
   {"%hi", BFD_RELOC_RISCV_HI20},
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 6e932dc..488cf56 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -257,6 +257,23 @@  Or you can use the pseudo lla/lw/sw/... instruction to do this.
 	lla  a0, @var{symbol}
 @end smallexample
 
+@item %got_pcrel_hi(@var{symbol})
+The high 20 bits of relative address between pc and the GOT entry of
+@var{symbol}.  This is usually used with the %pcrel_lo modifier to access
+the GOT entry.
+
+@smallexample
+@var{label}:
+	auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
+	addi       a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I
+
+@var{label}:
+	auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
+	load/store a0, %pcrel_lo(@var{label})(a0)  // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+Also, the pseudo la instruction with PIC has similar behavior.
+
 @item %tprel_add(@var{symbol})
 This is used purely to associate the R_RISCV_TPREL_ADD relocation for
 TLS relaxation.  This one is only valid as the fourth operand to the normally
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d
index 62f28e0..c2ca1aa 100644
--- a/gas/testsuite/gas/riscv/no-relax-reloc.d
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.d
@@ -9,4 +9,6 @@  RELOCATION RECORDS FOR .*
 0+4 R_RISCV_LO12_I.*
 0+8 R_RISCV_PCREL_HI20.*
 0+c R_RISCV_PCREL_LO12_I.*
-0+10 R_RISCV_CALL.*
+0+10 R_RISCV_GOT_HI20.*
+0+14 R_RISCV_PCREL_LO12_I.*
+0+18 R_RISCV_CALL.*
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s
index 7f1a484..2aab995 100644
--- a/gas/testsuite/gas/riscv/no-relax-reloc.s
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.s
@@ -2,7 +2,10 @@  target:
 	lui	a5,%hi(target)
 	lw	a5,%lo(target)(a5)
 
-        .LA0: auipc     a5,%pcrel_hi(bar)
-        lw      a0,%pcrel_lo(.LA0)(a5)
+	.LA0: auipc     a5,%pcrel_hi(symbol1)
+	lw      a0,%pcrel_lo(.LA0)(a5)
+
+	.LA1: auipc     a5,%got_pcrel_hi(symbol2)
+	lw      a0,%pcrel_lo(.LA1)(a5)
 
 	call target
diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d
index f5f592c..623218e 100644
--- a/gas/testsuite/gas/riscv/relax-reloc.d
+++ b/gas/testsuite/gas/riscv/relax-reloc.d
@@ -13,5 +13,8 @@  RELOCATION RECORDS FOR .*
 0+8 R_RISCV_RELAX.*
 0+c R_RISCV_PCREL_LO12_I.*
 0+c R_RISCV_RELAX.*
-0+10 R_RISCV_CALL.*
-0+10 R_RISCV_RELAX.*
+0+10 R_RISCV_GOT_HI20.*
+0+14 R_RISCV_PCREL_LO12_I.*
+0+14 R_RISCV_RELAX.*
+0+18 R_RISCV_CALL.*
+0+18 R_RISCV_RELAX.*
diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s
index 7f1a484..2aab995 100644
--- a/gas/testsuite/gas/riscv/relax-reloc.s
+++ b/gas/testsuite/gas/riscv/relax-reloc.s
@@ -2,7 +2,10 @@  target:
 	lui	a5,%hi(target)
 	lw	a5,%lo(target)(a5)
 
-        .LA0: auipc     a5,%pcrel_hi(bar)
-        lw      a0,%pcrel_lo(.LA0)(a5)
+	.LA0: auipc     a5,%pcrel_hi(symbol1)
+	lw      a0,%pcrel_lo(.LA0)(a5)
+
+	.LA1: auipc     a5,%got_pcrel_hi(symbol2)
+	lw      a0,%pcrel_lo(.LA1)(a5)
 
 	call target