[2/2] RISC-V: Support assembler modifier %got_pcrel_hi.

Message ID 1583230959-11401-3-git-send-email-nelson.chu@sifive.com
State Superseded
Headers show
Series
  • Add description for the RISC-V relocatable modifiers in as doc
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Commit Message

Nelson Chu March 3, 2020, 10:22 a.m.
gas/
	* config/tc-riscv.c: Support the modifier %got_pcrel_hi.
	* doc/c-riscv.texi: Add documentation.
	* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
	modifier %got_pcrel_hi.
	* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
	* testsuite/gas/riscv/relax-reloc.d: Likewise.
	* testsuite/gas/riscv/relax-reloc.s: Likewise.
---
 gas/config/tc-riscv.c                    |  1 +
 gas/doc/c-riscv.texi                     | 12 ++++++++++++
 gas/testsuite/gas/riscv/no-relax-reloc.d |  4 +++-
 gas/testsuite/gas/riscv/no-relax-reloc.s |  7 +++++--
 gas/testsuite/gas/riscv/relax-reloc.d    |  7 +++++--
 gas/testsuite/gas/riscv/relax-reloc.s    |  7 +++++--
 6 files changed, 31 insertions(+), 7 deletions(-)

-- 
2.7.4

Comments

Jim Wilson March 3, 2020, 10:16 p.m. | #1
On Tue, Mar 3, 2020 at 2:22 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>

>         gas/

>         * config/tc-riscv.c: Support the modifier %got_pcrel_hi.

>         * doc/c-riscv.texi: Add documentation.

>         * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new

>         modifier %got_pcrel_hi.

>         * testsuite/gas/riscv/no-relax-reloc.s: Likewise.

>         * testsuite/gas/riscv/relax-reloc.d: Likewise.

>         * testsuite/gas/riscv/relax-reloc.s: Likewise.


This looks good.  I'd just suggest some minor doc fixes to be
consistent with suggestions for the first patch.

> +@item %got_pcrel_hi(@var{symbol}

> +The high 20-bit of relative address between pc and the GOT entry of

> +@var{symbol}.  This is usually used with the %pcrel_lo to access the GOT entry.


20-bit -> 20 bits
"the %pcrel_lo" -> "%pcrel_lo" or "the %pcrel_lo modifier"

> +@smallexample

> +@var{label}:

> +       auipc           a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20

> +       addi/load/store a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I/S

> +@end smallexample

> +

> +Also, the pseudo la instruction with PIC has the similar behavior.


"the similar" -> "similar" or "the same"

Jim
Fangrui Song March 4, 2020, 12:07 a.m. | #2
On 2020-03-03, Jim Wilson wrote:
>On Tue, Mar 3, 2020@2:22 AM Nelson Chu <nelson.chu@sifive.com> wrote:

>>

>>         gas/

>>         * config/tc-riscv.c: Support the modifier %got_pcrel_hi.

>>         * doc/c-riscv.texi: Add documentation.

>>         * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new

>>         modifier %got_pcrel_hi.

>>         * testsuite/gas/riscv/no-relax-reloc.s: Likewise.

>>         * testsuite/gas/riscv/relax-reloc.d: Likewise.

>>         * testsuite/gas/riscv/relax-reloc.s: Likewise.

>

>This looks good.  I'd just suggest some minor doc fixes to be

>consistent with suggestions for the first patch.

>

>> +@item %got_pcrel_hi(@var{symbol}

>> +The high 20-bit of relative address between pc and the GOT entry of

>> +@var{symbol}.  This is usually used with the %pcrel_lo to access the GOT entry.

>

>20-bit -> 20 bits

>"the %pcrel_lo" -> "%pcrel_lo" or "the %pcrel_lo modifier"

>

>> +@smallexample

>> +@var{label}:

>> +       auipc           a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20

>> +       addi/load/store a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I/S

>> +@end smallexample

>> +

>> +Also, the pseudo la instruction with PIC has the similar behavior.

>

>"the similar" -> "similar" or "the same"

>

>Jim


What if %got_pcrel_hi refers to a STB_LOCAL symbol? For example,

auipc a0, %got_pcrel_hi(.L1)

It may be worth a test.

FWIW, llvm-mc -triple=riscv64 -filetype=obj a.s # create a R_RISCV_GOT_HI20 referencing .L1
There is no special treatment.
Nelson Chu March 4, 2020, 1:54 a.m. | #3
Hi MaskRay,

On Wed, Mar 4, 2020 at 8:07 AM Fangrui Song <i@maskray.me> wrote:
>

> What if %got_pcrel_hi refers to a STB_LOCAL symbol? For example,

>

> auipc a0, %got_pcrel_hi(.L1)

>

> It may be worth a test.

>

> FWIW, llvm-mc -triple=riscv64 -filetype=obj a.s # create a R_RISCV_GOT_HI20 referencing .L1

> There is no special treatment.


Consider the following case tmp.s:

        .option pic
        .option norelax
        .global foo
foo:
        la a0, foo
.L1:
        auipc a0, %got_pcrel_hi(foo)
        ld a0, %pcrel_lo(.L1)(a0)
.L2:
        auipc a0, %got_pcrel_hi(.L1)
        addi a0, a0, %pcrel_lo(.L2)

        la a0, .L1

$ ~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
tmp.s -o tmp.o
$ ~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-objdump
-dr tmp.o

tmp.o:     file format elf64-littleriscv


Disassembly of section .text:

0000000000000000 <foo>:
   0:   00000517                auipc   a0,0x0
                        0: R_RISCV_GOT_HI20     foo
   4:   00053503                ld      a0,0(a0) # 0 <foo>
                        4: R_RISCV_PCREL_LO12_I .L0

0000000000000008 <.L1>:
   8:   00000517                auipc   a0,0x0
                        8: R_RISCV_GOT_HI20     foo
   c:   00053503                ld      a0,0(a0) # 8 <.L1>
                        c: R_RISCV_PCREL_LO12_I .L1

0000000000000010 <.L2>:
  10:   00000517                auipc   a0,0x0
                        10: R_RISCV_GOT_HI20    .L1
  14:   00050513                mv      a0,a0
                        14: R_RISCV_PCREL_LO12_I        .L2
  18:   00000517                auipc   a0,0x0
                        18: R_RISCV_GOT_HI20    .L1
  1c:   00053503                ld      a0,0(a0) # 18 <.L2+0x8>
                        1c: R_RISCV_PCREL_LO12_I        .L0

`foo` is a global symbol.  `.L1` and `.L2` are local symbols.  I think
the current upstream GNU assembler treats them all the same for LA
macro with pic and %got_pcrel_hi.  So yes, the behavior should be the
same as llvm-mc.  BTW I get the same result for the linux toolchain.

Thanks
Nelson

Patch

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ddd4d14..168561e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1308,6 +1308,7 @@  static const struct percent_op_match percent_op_utype[] =
 {
   {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
   {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
+  {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
   {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
   {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
   {"%hi", BFD_RELOC_RISCV_HI20},
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 8212a17..72605e7 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -249,6 +249,18 @@  Or you can use the pseudo lla/lw/sw/... instruction to do this.
 	lla  a0, @var{symbol}
 @end smallexample
 
+@item %got_pcrel_hi(@var{symbol}
+The high 20-bit of relative address between pc and the GOT entry of
+@var{symbol}.  This is usually used with the %pcrel_lo to access the GOT entry.
+
+@smallexample
+@var{label}:
+	auipc           a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
+	addi/load/store a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I/S
+@end smallexample
+
+Also, the pseudo la instruction with PIC has the similar behavior.
+
 @item %tprel_add(@var{symbol}
 This is used purely to associate the R_RISCV_TPREL_ADD relocation for
 TLS relaxation.
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d
index 62f28e0..c2ca1aa 100644
--- a/gas/testsuite/gas/riscv/no-relax-reloc.d
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.d
@@ -9,4 +9,6 @@  RELOCATION RECORDS FOR .*
 0+4 R_RISCV_LO12_I.*
 0+8 R_RISCV_PCREL_HI20.*
 0+c R_RISCV_PCREL_LO12_I.*
-0+10 R_RISCV_CALL.*
+0+10 R_RISCV_GOT_HI20.*
+0+14 R_RISCV_PCREL_LO12_I.*
+0+18 R_RISCV_CALL.*
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s
index 7f1a484..2aab995 100644
--- a/gas/testsuite/gas/riscv/no-relax-reloc.s
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.s
@@ -2,7 +2,10 @@  target:
 	lui	a5,%hi(target)
 	lw	a5,%lo(target)(a5)
 
-        .LA0: auipc     a5,%pcrel_hi(bar)
-        lw      a0,%pcrel_lo(.LA0)(a5)
+	.LA0: auipc     a5,%pcrel_hi(symbol1)
+	lw      a0,%pcrel_lo(.LA0)(a5)
+
+	.LA1: auipc     a5,%got_pcrel_hi(symbol2)
+	lw      a0,%pcrel_lo(.LA1)(a5)
 
 	call target
diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d
index f5f592c..623218e 100644
--- a/gas/testsuite/gas/riscv/relax-reloc.d
+++ b/gas/testsuite/gas/riscv/relax-reloc.d
@@ -13,5 +13,8 @@  RELOCATION RECORDS FOR .*
 0+8 R_RISCV_RELAX.*
 0+c R_RISCV_PCREL_LO12_I.*
 0+c R_RISCV_RELAX.*
-0+10 R_RISCV_CALL.*
-0+10 R_RISCV_RELAX.*
+0+10 R_RISCV_GOT_HI20.*
+0+14 R_RISCV_PCREL_LO12_I.*
+0+14 R_RISCV_RELAX.*
+0+18 R_RISCV_CALL.*
+0+18 R_RISCV_RELAX.*
diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s
index 7f1a484..2aab995 100644
--- a/gas/testsuite/gas/riscv/relax-reloc.s
+++ b/gas/testsuite/gas/riscv/relax-reloc.s
@@ -2,7 +2,10 @@  target:
 	lui	a5,%hi(target)
 	lw	a5,%lo(target)(a5)
 
-        .LA0: auipc     a5,%pcrel_hi(bar)
-        lw      a0,%pcrel_lo(.LA0)(a5)
+	.LA0: auipc     a5,%pcrel_hi(symbol1)
+	lw      a0,%pcrel_lo(.LA0)(a5)
+
+	.LA1: auipc     a5,%got_pcrel_hi(symbol2)
+	lw      a0,%pcrel_lo(.LA1)(a5)
 
 	call target