Remove Intel syntax comments on movsx and movzx

Message ID 20200214134557.154514-1-hjl.tools@gmail.com
State New
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Series
  • Remove Intel syntax comments on movsx and movzx
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Commit Message

H.J. Lu Feb. 14, 2020, 1:45 p.m.
Since movsx and movzx are valid mnemonic in AT&T syntax, remove Intel
syntax comments on movsx and movzx to avoid confusing other readers.

	* i386-opc.tbl (movsx): Remove Intel syntax comments.
	(movzx): Likewise.
---
 opcodes/ChangeLog    | 5 +++++
 opcodes/i386-opc.tbl | 5 ++---
 2 files changed, 7 insertions(+), 3 deletions(-)

-- 
2.24.1

Comments

Jan Beulich Feb. 14, 2020, 1:52 p.m. | #1
On 14.02.2020 14:45, H.J. Lu wrote:
> Since movsx and movzx are valid mnemonic in AT&T syntax,


I disagree. I've just looked at the AT&T (Solaris) spec again, and
there's no mention of these two except as "Intel/AMD mnemonic".
But well, I see you've committed this already.

Jan
H.J. Lu Feb. 14, 2020, 2:12 p.m. | #2
On Fri, Feb 14, 2020 at 5:52 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 14.02.2020 14:45, H.J. Lu wrote:

> > Since movsx and movzx are valid mnemonic in AT&T syntax,

>

> I disagree. I've just looked at the AT&T (Solaris) spec again, and

> there's no mention of these two except as "Intel/AMD mnemonic".

> But well, I see you've committed this already.


We need to document what we have implemented and we can't change.

-- 
H.J.

Patch

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a53d646e42..103c508be0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@ 
+2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-opc.tbl (movsx): Remove Intel syntax comments.
+	(movzx): Likewise.
+
 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 
 	PR gas/25438
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 6eb7238589..01cf61a624 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -132,7 +132,6 @@  movswl, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf
 movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 }
 movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 }
 movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
-// Intel Syntax next 2 insns
 movsx, 2, 0xfbe, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
 movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
@@ -142,8 +141,8 @@  movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
 // Move with zero extend.
 movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
-// Intel Syntax next insn (the 64-bit variant is not particulary
-// useful since the zero extend 32->64 is implicit, but we can encode them).
+// The 64-bit variant is not particularly useful since the zero extend
+// 32->64 is implicit, but we can encode them.
 movzx, 2, 0xfb6, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 
 // Push instructions.