[MIPS] Loongson EXT fixes

Message ID 20200205124137.188485-1-jiaxun.yang@flygoat.com
State New
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Series
  • [MIPS] Loongson EXT fixes
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Commit Message

Jiaxun Yang Feb. 5, 2020, 12:41 p.m.
2020-02-05  Jiaxun Yang  <jiaxun.yang@flygoat.com>

	gas/
	* doc/as.texi: Add missing 2 for loongson-ext2.
	* testsuite/gas/mips/loongson-ext2.s: Add tests for gsandn & gsorn.
	* testsuite/gas/mips/loongson-ext2.d: Likewise.

	opcodes/
	* mips-dis.c: Add missing AFL flag matching for LOONGSON ASEs.
	* mips-opc.c: Add missing gsandn & gsorn opcodes.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

---
 gas/doc/as.texi                        | 2 +-
 gas/testsuite/gas/mips/loongson-ext2.d | 2 ++
 gas/testsuite/gas/mips/loongson-ext2.s | 2 ++
 opcodes/mips-dis.c                     | 8 ++++++++
 opcodes/mips-opc.c                     | 2 ++
 5 files changed, 15 insertions(+), 1 deletion(-)

-- 
2.25.0

Comments

Paul Hua Feb. 6, 2020, 6:44 a.m. | #1
> +++ b/gas/doc/as.texi

> @@ -1644,7 +1644,7 @@ This tells the assembler to accept Loongson EXT instructions.

>  @item -mloongson-ext2

>  @itemx -mno-loongson-ext2

>  Generate code for the Loongson EXTensions R2 (EXT2) instructions.

> -This option implies @samp{-mloongson-ext}.

> +This option implies @samp{-mloongson-ext2}.

>  This tells the assembler to accept Loongson EXT2 instructions.

>  @samp{-mno-loongson-ext2} turns off this option.

>


It is ok, the -mloongson-ext2 will trun on -mloongson-ext.

> diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c

> index 755bbe294b..18dde79294 100644

> --- a/opcodes/mips-dis.c

> +++ b/opcodes/mips-dis.c

> @@ -824,6 +824,14 @@ mips_convert_abiflags_ases (unsigned long afl_ases)

>      opcode_ases |= ASE_DSPR3;

>    if (afl_ases & AFL_ASE_MIPS16E2)

>      opcode_ases |= ASE_MIPS16E2;

> +  if (afl_ases & AFL_ASE_LOONGSON_MMI)

> +    opcode_ases |= ASE_LOONGSON_MMI;

> +  if (afl_ases & AFL_ASE_LOONGSON_CAM)

> +    opcode_ases |= ASE_LOONGSON_CAM;

> +  if (afl_ases & AFL_ASE_LOONGSON_EXT)

> +    opcode_ases |= ASE_LOONGSON_EXT;

> +  if (afl_ases & AFL_ASE_LOONGSON_EXT2)

> +    opcode_ases |= ASE_LOONGSON_EXT2;

>    return opcode_ases;

>  }


Thanks for catch this.

> diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c

> index 5270aeefa8..625b745edc 100644

> --- a/opcodes/mips-opc.c

> +++ b/opcodes/mips-opc.c

> @@ -526,6 +526,8 @@ const struct mips_opcode mips_builtin_opcodes[] =

>  {"ctz",                        "d,s",          0x70000022, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LEXT2,  0 },

>  {"dcto",               "d,s",          0x700000e2, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LEXT2,  0 },

>  {"dctz",               "d,s",          0x700000a2, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LEXT2,  0 },

> +{"gsandn",             "d,s,t",        0x70000483, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT2,  0 },

> +{"gsorn",              "d,s,t",        0x70000486, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT2,  0 },

>


The gsandn and gsorn belong to upcomming loongson-ext3.
Jiaxun Yang Feb. 6, 2020, 6:58 a.m. | #2
>> +++ b/gas/doc/as.texi

>> @@ -1644,7 +1644,7 @@ This tells the assembler to accept Loongson EXT instructions.

>> @item -mloongson-ext2

>> @itemx -mno-loongson-ext2

>> Generate code for the Loongson EXTensions R2 (EXT2) instructions.

>> -This option implies @samp{-mloongson-ext}.

>> +This option implies @samp{-mloongson-ext2}.

>> This tells the assembler to accept Loongson EXT2 instructions.

>> @samp{-mno-loongson-ext2} turns off this option.

> 

> It is ok, the -mloongson-ext2 will trun on -mloongson-ext.


Thanks for the clarification.

> 

>> diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c

>> index 755bbe294b..18dde79294 100644

>> --- a/opcodes/mips-dis.c

>> +++ b/opcodes/mips-dis.c

>> @@ -824,6 +824,14 @@ mips_convert_abiflags_ases (unsigned long afl_ases)

>> opcode_ases |= ASE_DSPR3;

>> if (afl_ases & AFL_ASE_MIPS16E2)

>> opcode_ases |= ASE_MIPS16E2;

>> + if (afl_ases & AFL_ASE_LOONGSON_MMI)

>> + opcode_ases |= ASE_LOONGSON_MMI;

>> + if (afl_ases & AFL_ASE_LOONGSON_CAM)

>> + opcode_ases |= ASE_LOONGSON_CAM;

>> + if (afl_ases & AFL_ASE_LOONGSON_EXT)

>> + opcode_ases |= ASE_LOONGSON_EXT;

>> + if (afl_ases & AFL_ASE_LOONGSON_EXT2)

>> + opcode_ases |= ASE_LOONGSON_EXT2;

>> return opcode_ases;

>> }

> 

> Thanks for catch this.

> 

>> diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c

>> index 5270aeefa8..625b745edc 100644

>> --- a/opcodes/mips-opc.c

>> +++ b/opcodes/mips-opc.c

>> @@ -526,6 +526,8 @@ const struct mips_opcode mips_builtin_opcodes[] =

>> {"ctz", "d,s", 0x70000022, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },

>> {"dcto", "d,s", 0x700000e2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },

>> {"dctz", "d,s", 0x700000a2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },

>> +{"gsandn", "d,s,t", 0x70000483, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT2, 0 },

>> +{"gsorn", "d,s,t", 0x70000486, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT2, 0 },

> 

> The gsandn and gsorn belong to upcomming loongson-ext3.


According to Loongson-3A2000 Vol.2 [1], they do exist in GS464E, so I thought it should
be a part of ext2, is it true?

I just discovered that test for ext2 and cam never got run, will fix it in v2.

Btw, as we still didn't see any see action from Loongson in mainline LoongISA2 support,
I'm cooperating with Xuerui Wang <wangxuerui@qiniu.com> to archive this. I'm working
on Binutils side while he is working on GCC.
We've already got binutils patches from Loongson about MSA2, EXT3, mipsr6p,
MSA Crypto, AMO, LSX, LASX and trying to improve them to meet upstream requirements.

Thanks.

[1]: http://loongson.cn/uploadfile/cpu/3A2000/Loongson3A2000_user2.pdf

--
Jiaxun Yang

Patch

diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 152bbfdd00..79c1efcd10 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -1644,7 +1644,7 @@  This tells the assembler to accept Loongson EXT instructions.
 @item -mloongson-ext2
 @itemx -mno-loongson-ext2
 Generate code for the Loongson EXTensions R2 (EXT2) instructions.
-This option implies @samp{-mloongson-ext}.
+This option implies @samp{-mloongson-ext2}.
 This tells the assembler to accept Loongson EXT2 instructions.
 @samp{-mno-loongson-ext2} turns off this option.
 
diff --git a/gas/testsuite/gas/mips/loongson-ext2.d b/gas/testsuite/gas/mips/loongson-ext2.d
index d8213867e7..13af6878ff 100644
--- a/gas/testsuite/gas/mips/loongson-ext2.d
+++ b/gas/testsuite/gas/mips/loongson-ext2.d
@@ -26,3 +26,5 @@  Disassembly of section .text:
 .*:	70801022 	ctz	\$2,\$4
 .*:	708010e2 	dcto	\$2,\$4
 .*:	708010a2 	dctz	\$2,\$4
+.*:	70861483        gsandn  \$2,\$4,\$6
+.*:	70861486        gsorn   \$2,\$4,\$6
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/loongson-ext2.s b/gas/testsuite/gas/mips/loongson-ext2.s
index 023a469666..0830cfac6f 100644
--- a/gas/testsuite/gas/mips/loongson-ext2.s
+++ b/gas/testsuite/gas/mips/loongson-ext2.s
@@ -5,3 +5,5 @@ 
 	ctz	$2,$4
 	dcto	$2,$4
 	dctz	$2,$4
+	gsandn	$2,$4,$6
+	gsorn	$2,$4,$6
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 755bbe294b..18dde79294 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -824,6 +824,14 @@  mips_convert_abiflags_ases (unsigned long afl_ases)
     opcode_ases |= ASE_DSPR3;
   if (afl_ases & AFL_ASE_MIPS16E2)
     opcode_ases |= ASE_MIPS16E2;
+  if (afl_ases & AFL_ASE_LOONGSON_MMI)
+    opcode_ases |= ASE_LOONGSON_MMI;
+  if (afl_ases & AFL_ASE_LOONGSON_CAM)
+    opcode_ases |= ASE_LOONGSON_CAM;
+  if (afl_ases & AFL_ASE_LOONGSON_EXT)
+    opcode_ases |= ASE_LOONGSON_EXT;
+  if (afl_ases & AFL_ASE_LOONGSON_EXT2)
+    opcode_ases |= ASE_LOONGSON_EXT2;
   return opcode_ases;
 }
 
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 5270aeefa8..625b745edc 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -526,6 +526,8 @@  const struct mips_opcode mips_builtin_opcodes[] =
 {"ctz",			"d,s",		0x70000022, 0xfc1f07ff,	WR_1|RD_2,		0,		0,		LEXT2,	0 },
 {"dcto",		"d,s",		0x700000e2, 0xfc1f07ff,	WR_1|RD_2,		0,		0,		LEXT2,	0 },
 {"dctz",		"d,s",		0x700000a2, 0xfc1f07ff,	WR_1|RD_2,		0,		0,		LEXT2,	0 },
+{"gsandn",		"d,s,t",	0x70000483, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		0,		LEXT2,	0 },
+{"gsorn",		"d,s,t",	0x70000486, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		0,		LEXT2,	0 },
 
 /* R5900 VU0 Macromode instructions. */
 {"vabs",		"+7+K,+6+K",	  0x4a0001fd, 0xfe0007ff,	CP,		VU0CH,		VU0,		0,	0 },