[committed,amdgcn] Fix early-clobber in vec_extract

Message ID 02e79850-5fce-17a4-44f1-efb9a382f19f@codesourcery.com
State New
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  • [committed,amdgcn] Fix early-clobber in vec_extract
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Commit Message

Andrew Stubbs Jan. 6, 2020, 3:47 p.m.
This patch fixes an execution test failure in gcc.dg/vect/vect-live-2.c.

The problem was that the input and output registers were the same, which 
isn't safe for this pattern. It could be fixed by reversing the 
instructions, but then that would still be broken for overlapping input 
and output register pairs. Other patterns use '0' to allow exact 
matches, but the input and outputs here are different size, and I'm not 
sure what happens there. Anyway, this is safe.

Andrew

Patch

Fix early-clobber in amdgcn vec_extract

2020-01-06  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
	clobber.

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 457a66c1505..9baef24b1c8 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -580,10 +580,10 @@ 
    (set_attr "laneselect" "yes")])
 
 (define_insn "vec_extract<mode><scalar_mode>"
-  [(set (match_operand:<SCALAR_MODE> 0 "register_operand"   "=Sg")
+  [(set (match_operand:<SCALAR_MODE> 0 "register_operand"   "=&Sg")
 	(vec_select:<SCALAR_MODE>
-	  (match_operand:VEC_2REG_MODE 1 "register_operand" "  v")
-	  (parallel [(match_operand:SI 2 "gcn_alu_operand"  "SvB")])))]
+	  (match_operand:VEC_2REG_MODE 1 "register_operand" "   v")
+	  (parallel [(match_operand:SI 2 "gcn_alu_operand"  " SvB")])))]
   ""
   "v_readlane_b32 %L0, %L1, %2\;v_readlane_b32 %H0, %H1, %2"
   [(set_attr "type" "vmult")