[AMDGCN] Use fixed registers for queue ptr sgpr pair

Message ID 20191204000149.4679daa4@squid.athome
State New
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Series
  • [AMDGCN] Use fixed registers for queue ptr sgpr pair
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Commit Message

Julian Brown Dec. 4, 2019, 12:01 a.m.
Hi,

When running tests on a slightly-revised version of the
worker-partitioning patch series previously posted starting here:

https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01475.html

I discovered that Kwok's patch to optimise GCN register usage
(r278301) was causing one of the new tests to fail:

https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01210.html

The patch marks the s6/s7 pair as unfixed, but that (as the "queue
pointer") is needed for some kinds of address-space conversion --
which may be synthesized either in normal or kernel entry-point
functions by the worker-partitioning support (gcn_addr_space_convert).
So, it's not safe to leave those registers for general use.

The solution seems to be just to fix the s6/s7 pair. I think I can
self-approve this as a bug fix. Any comments, though? (Andrew, Kwok?)

Tested with offloading to AMD GCN (alongside the worker-partitioning
patches).

Thanks,

Julian

ChangeLog

    gcc/
    * config/gcn/gcn.h (FIXED_REGISTERS): Make s6/s7 fixed registers.

Patch

commit a4e9b17ba2bcdc3ab206fa4424cb55bc320fd092
Author: Julian Brown <julian@codesourcery.com>
Date:   Mon Dec 2 16:53:50 2019 -0800

    Use fixed registers for queue ptr sgpr pair
    
            gcc/
            * config/gcn/gcn.h (FIXED_REGISTERS): Make s6/s7 fixed registers.

diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h
index e60b43122d5..bdf7188b5ff 100644
--- a/gcc/config/gcn/gcn.h
+++ b/gcc/config/gcn/gcn.h
@@ -160,7 +160,7 @@ 
 
 #define FIXED_REGISTERS {			    \
     /* Scalars.  */				    \
-    1, 1, 0, 0, 1, 1, 0, 0, 1, 1,		    \
+    1, 1, 0, 0, 1, 1, 1, 1, 1, 1,		    \
 /*		fp    sp    lr.  */		    \
     1, 1, 0, 0, 0, 0, 1, 1, 0, 0,		    \
 /*  exec_save, cc_save */			    \