[v2,6/6] aarch64: Add testsuite checks for asm-flag

Message ID 20191114100716.28827-7-richard.henderson@linaro.org
State New
Headers show
Series
  • Implement asm flag outputs for arm + aarch64
Related show

Commit Message

Richard Henderson Nov. 14, 2019, 10:07 a.m.
Inspired by the tests in gcc.target/i386.  Testing code generation,
diagnostics, and execution.

	* gcc.target/aarch64/asm-flag-1.c: New test.
	* gcc.target/aarch64/asm-flag-3.c: New test.
	* gcc.target/aarch64/asm-flag-5.c: New test.
	* gcc.target/aarch64/asm-flag-6.c: New test.
---
 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 35 +++++++++++
 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 38 ++++++++++++
 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++++++++
 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 62 +++++++++++++++++++
 4 files changed, 165 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c

-- 
2.17.1

Comments

Christophe Lyon Nov. 18, 2019, 12:30 p.m. | #1
On Thu, 14 Nov 2019 at 11:08, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Inspired by the tests in gcc.target/i386.  Testing code generation,

> diagnostics, and execution.

>

>         * gcc.target/aarch64/asm-flag-1.c: New test.

>         * gcc.target/aarch64/asm-flag-3.c: New test.

>         * gcc.target/aarch64/asm-flag-5.c: New test.

>         * gcc.target/aarch64/asm-flag-6.c: New test.


Hi Richard,


I'm sorry to notice that the last test (asm-flag-6.c) fails to execute
when compiling with -mabi=ilp32. I have less details than for Arm,
because here I'm using the Foundation Model as simulator instead of
Qemu. In addition, I'm using an old version of it, so maybe it's a
simulator bug. Does it work on your side?

Thanks,

Christophe

> ---

>  gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 35 +++++++++++

>  gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 38 ++++++++++++

>  gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++++++++

>  gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 62 +++++++++++++++++++

>  4 files changed, 165 insertions(+)

>  create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c

>  create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c

>  create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c

>  create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c

>

> diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c

> new file mode 100644

> index 00000000000..49901e59c38

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c

> @@ -0,0 +1,35 @@

> +/* Test the valid @cc<cc> asm flag outputs.  */

> +/* { dg-do compile } */

> +/* { dg-options "-O" } */

> +

> +#ifndef __GCC_ASM_FLAG_OUTPUTS__

> +#error "missing preprocessor define"

> +#endif

> +

> +void f(char *out)

> +{

> +  asm(""

> +      : "=@ccne"(out[0]), "=@cceq"(out[1]),

> +       "=@cccs"(out[2]), "=@cccc"(out[3]),

> +       "=@ccmi"(out[4]), "=@ccpl"(out[5]),

> +       "=@ccvs"(out[6]), "=@ccvc"(out[7]),

> +       "=@cchi"(out[8]), "=@ccls"(out[9]),

> +       "=@ccge"(out[10]), "=@cclt"(out[11]),

> +       "=@ccgt"(out[12]), "=@ccle"(out[13]),

> +       "=@cchs"(out[14]), "=@cclo"(out[15]));

> +}

> +

> +/* { dg-final { scan-assembler "cset.*, ne" } } */

> +/* { dg-final { scan-assembler "cset.*, eq" } } */

> +/* { dg-final { scan-assembler "cset.*, cs" } } */

> +/* { dg-final { scan-assembler "cset.*, cc" } } */

> +/* { dg-final { scan-assembler "cset.*, mi" } } */

> +/* { dg-final { scan-assembler "cset.*, pl" } } */

> +/* { dg-final { scan-assembler "cset.*, vs" } } */

> +/* { dg-final { scan-assembler "cset.*, vc" } } */

> +/* { dg-final { scan-assembler "cset.*, hi" } } */

> +/* { dg-final { scan-assembler "cset.*, ls" } } */

> +/* { dg-final { scan-assembler "cset.*, ge" } } */

> +/* { dg-final { scan-assembler "cset.*, ls" } } */

> +/* { dg-final { scan-assembler "cset.*, gt" } } */

> +/* { dg-final { scan-assembler "cset.*, le" } } */

> diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c

> new file mode 100644

> index 00000000000..e84e3431277

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c

> @@ -0,0 +1,38 @@

> +/* Test some of the valid @cc<cc> asm flag outputs.  */

> +/* { dg-do compile } */

> +/* { dg-options "-O" } */

> +

> +#define DO(C) \

> +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); }

> +

> +DO(ne)

> +DO(eq)

> +DO(cs)

> +DO(cc)

> +DO(hs)

> +DO(lo)

> +DO(mi)

> +DO(pl)

> +DO(vs)

> +DO(vc)

> +DO(hi)

> +DO(ls)

> +DO(ge)

> +DO(lt)

> +DO(gt)

> +DO(le)

> +

> +/* { dg-final { scan-assembler "bne" } } */

> +/* { dg-final { scan-assembler "beq" } } */

> +/* { dg-final { scan-assembler "bcs" } } */

> +/* { dg-final { scan-assembler "bcc" } } */

> +/* { dg-final { scan-assembler "bmi" } } */

> +/* { dg-final { scan-assembler "bpl" } } */

> +/* { dg-final { scan-assembler "bvs" } } */

> +/* { dg-final { scan-assembler "bvc" } } */

> +/* { dg-final { scan-assembler "bhi" } } */

> +/* { dg-final { scan-assembler "bls" } } */

> +/* { dg-final { scan-assembler "bge" } } */

> +/* { dg-final { scan-assembler "blt" } } */

> +/* { dg-final { scan-assembler "bgt" } } */

> +/* { dg-final { scan-assembler "ble" } } */

> diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c

> new file mode 100644

> index 00000000000..4d4394e1478

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c

> @@ -0,0 +1,30 @@

> +/* Test error conditions of asm flag outputs.  */

> +/* { dg-do compile } */

> +/* { dg-options "" } */

> +

> +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); }

> +void f_c(void) { char x; asm("" : "=@cccc"(x)); }

> +void f_s(void) { short x; asm("" : "=@cccc"(x)); }

> +void f_i(void) { int x; asm("" : "=@cccc"(x)); }

> +void f_l(void) { long x; asm("" : "=@cccc"(x)); }

> +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); }

> +

> +void f_f(void)

> +{

> +  float x;

> +  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */

> +}

> +

> +void f_d(void)

> +{

> +  double x;

> +  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */

> +}

> +

> +struct S { int x[3]; };

> +

> +void f_S(void)

> +{

> +  struct S x;

> +  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */

> +}

> diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c

> new file mode 100644

> index 00000000000..963b5a48c70

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c

> @@ -0,0 +1,62 @@

> +/* Executable testcase for 'output flags.'  */

> +/* { dg-do run } */

> +

> +int test_bits (long nzcv)

> +{

> +  long n, z, c, v;

> +

> +  __asm__ ("msr nzcv, %[in]"

> +          : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v)

> +          : [in] "r"(nzcv << 28));

> +

> +  return n * 8 + z * 4 + c * 2 + v == nzcv;

> +}

> +

> +int test_cmps (long x, long y)

> +{

> +  long gt, lt, ge, le;

> +

> +  __asm__ ("cmp %[x], %[y]"

> +          : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le)

> +          : [x] "r"(x), [y] "r"(y));

> +

> +  return (gt == (x > y)

> +         && lt == (x < y)

> +         && ge == (x >= y)

> +         && le == (x <= y));

> +}

> +

> +int test_cmpu (unsigned long x, unsigned long y)

> +{

> +  long gt, lt, ge, le;

> +

> +  __asm__ ("cmp %[x], %[y]"

> +          : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le)

> +          : [x] "r"(x), [y] "r"(y));

> +

> +  return (gt == (x > y)

> +         && lt == (x < y)

> +         && ge == (x >= y)

> +         && le == (x <= y));

> +}

> +

> +int main ()

> +{

> +  long i, j;

> +

> +  for (i = 0; i < 16; ++i)

> +    if (!test_bits (i))

> +      __builtin_abort ();

> +

> +  for (i = -1; i <= 1; ++i)

> +    for (j = -1; j <= 1; ++j)

> +      if (!test_cmps (i, j))

> +        __builtin_abort ();

> +

> +  for (i = 0; i <= 2; ++i)

> +    for (j = 0; j <= 2; ++j)

> +      if (!test_cmpu (i, j))

> +        __builtin_abort ();

> +

> +  return 0;

> +}

> --

> 2.17.1

>
Richard Henderson Nov. 18, 2019, 7:54 p.m. | #2
On 11/18/19 1:30 PM, Christophe Lyon wrote:
> I'm sorry to notice that the last test (asm-flag-6.c) fails to execute

> when compiling with -mabi=ilp32. I have less details than for Arm,

> because here I'm using the Foundation Model as simulator instead of

> Qemu. In addition, I'm using an old version of it, so maybe it's a

> simulator bug. Does it work on your side?


I don't know how to test ilp32 with qemu.  Is there a distribution that uses
this mode, and one tests in system mode?  We don't have user-only support for
ilp32.

I think I have reproduced this with newlib and aarch64-elf.  It could be
solvable by using either unsigned long long, or by using %w constraints with
the two cmp instructions.

Except that I made that change and the failure didn't go away.  I'm having
trouble building a version of gdb that can debug this...


r~
Andreas Schwab Nov. 18, 2019, 9:27 p.m. | #3
On Nov 18 2019, Richard Henderson wrote:

> Except that I made that change and the failure didn't go away.  I'm having

> trouble building a version of gdb that can debug this...


https://build.opensuse.org/package/show/devel:ARM:Factory:Contrib:ILP32/gdb
has a gdb package that has support for ILP32.

Andreas.

-- 
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."
Christophe Lyon Nov. 19, 2019, 8:29 a.m. | #4
On Mon, 18 Nov 2019 at 20:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> On 11/18/19 1:30 PM, Christophe Lyon wrote:

> > I'm sorry to notice that the last test (asm-flag-6.c) fails to execute

> > when compiling with -mabi=ilp32. I have less details than for Arm,

> > because here I'm using the Foundation Model as simulator instead of

> > Qemu. In addition, I'm using an old version of it, so maybe it's a

> > simulator bug. Does it work on your side?

>

> I don't know how to test ilp32 with qemu.  Is there a distribution that uses

> this mode, and one tests in system mode?  We don't have user-only support for

> ilp32.

>


Sorry I wasn't clear: I test aarch64-elf with -mabi=ilp32, using newlib.

> I think I have reproduced this with newlib and aarch64-elf.  It could be

> solvable by using either unsigned long long, or by using %w constraints with

> the two cmp instructions.

>

> Except that I made that change and the failure didn't go away.  I'm having

> trouble building a version of gdb that can debug this...

>

>

> r~
Richard Henderson Nov. 19, 2019, 9:23 a.m. | #5
On 11/19/19 9:29 AM, Christophe Lyon wrote:
> On Mon, 18 Nov 2019 at 20:54, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>>

>> On 11/18/19 1:30 PM, Christophe Lyon wrote:

>>> I'm sorry to notice that the last test (asm-flag-6.c) fails to execute

>>> when compiling with -mabi=ilp32. I have less details than for Arm,

>>> because here I'm using the Foundation Model as simulator instead of

>>> Qemu. In addition, I'm using an old version of it, so maybe it's a

>>> simulator bug. Does it work on your side?

>>

>> I don't know how to test ilp32 with qemu.  Is there a distribution that uses

>> this mode, and one tests in system mode?  We don't have user-only support for

>> ilp32.

>>

> 

> Sorry I wasn't clear: I test aarch64-elf with -mabi=ilp32, using newlib.


In the short term, can you please try this testsuite patch?


r~
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
index 963b5a48c70..54d7fbf317d 100644
--- a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
@@ -1,6 +1,12 @@
 /* Executable testcase for 'output flags.'  */
 /* { dg-do run } */
 
+#ifdef __LP64__
+#define W ""
+#else
+#define W "w"
+#endif
+
 int test_bits (long nzcv)
 {
   long n, z, c, v;
@@ -16,7 +22,7 @@ int test_cmps (long x, long y)
 {
   long gt, lt, ge, le;
 
-  __asm__ ("cmp %[x], %[y]"
+  __asm__ ("cmp %"W"[x], %"W"[y]"
 	   : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le)
 	   : [x] "r"(x), [y] "r"(y));
 
@@ -30,7 +36,7 @@ int test_cmpu (unsigned long x, unsigned long y)
 {
   long gt, lt, ge, le;
 
-  __asm__ ("cmp %[x], %[y]"
+  __asm__ ("cmp %"W"[x], %"W"[y]"
 	   : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le)
 	   : [x] "r"(x), [y] "r"(y));
Christophe Lyon Nov. 19, 2019, 10:04 a.m. | #6
On Tue, 19 Nov 2019 at 10:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> On 11/19/19 9:29 AM, Christophe Lyon wrote:

> > On Mon, 18 Nov 2019 at 20:54, Richard Henderson

> > <richard.henderson@linaro.org> wrote:

> >>

> >> On 11/18/19 1:30 PM, Christophe Lyon wrote:

> >>> I'm sorry to notice that the last test (asm-flag-6.c) fails to execute

> >>> when compiling with -mabi=ilp32. I have less details than for Arm,

> >>> because here I'm using the Foundation Model as simulator instead of

> >>> Qemu. In addition, I'm using an old version of it, so maybe it's a

> >>> simulator bug. Does it work on your side?

> >>

> >> I don't know how to test ilp32 with qemu.  Is there a distribution that uses

> >> this mode, and one tests in system mode?  We don't have user-only support for

> >> ilp32.

> >>

> >

> > Sorry I wasn't clear: I test aarch64-elf with -mabi=ilp32, using newlib.

>

> In the short term, can you please try this testsuite patch?

>

I confirm this patch makes the test pass.

>

> r~

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
new file mode 100644
index 00000000000..49901e59c38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
@@ -0,0 +1,35 @@ 
+/* Test the valid @cc<cc> asm flag outputs.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#ifndef __GCC_ASM_FLAG_OUTPUTS__
+#error "missing preprocessor define"
+#endif
+
+void f(char *out)
+{
+  asm(""
+      : "=@ccne"(out[0]), "=@cceq"(out[1]),
+	"=@cccs"(out[2]), "=@cccc"(out[3]),
+	"=@ccmi"(out[4]), "=@ccpl"(out[5]),
+	"=@ccvs"(out[6]), "=@ccvc"(out[7]),
+	"=@cchi"(out[8]), "=@ccls"(out[9]),
+	"=@ccge"(out[10]), "=@cclt"(out[11]),
+	"=@ccgt"(out[12]), "=@ccle"(out[13]),
+	"=@cchs"(out[14]), "=@cclo"(out[15]));
+}
+
+/* { dg-final { scan-assembler "cset.*, ne" } } */
+/* { dg-final { scan-assembler "cset.*, eq" } } */
+/* { dg-final { scan-assembler "cset.*, cs" } } */
+/* { dg-final { scan-assembler "cset.*, cc" } } */
+/* { dg-final { scan-assembler "cset.*, mi" } } */
+/* { dg-final { scan-assembler "cset.*, pl" } } */
+/* { dg-final { scan-assembler "cset.*, vs" } } */
+/* { dg-final { scan-assembler "cset.*, vc" } } */
+/* { dg-final { scan-assembler "cset.*, hi" } } */
+/* { dg-final { scan-assembler "cset.*, ls" } } */
+/* { dg-final { scan-assembler "cset.*, ge" } } */
+/* { dg-final { scan-assembler "cset.*, ls" } } */
+/* { dg-final { scan-assembler "cset.*, gt" } } */
+/* { dg-final { scan-assembler "cset.*, le" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
new file mode 100644
index 00000000000..e84e3431277
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
@@ -0,0 +1,38 @@ 
+/* Test some of the valid @cc<cc> asm flag outputs.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#define DO(C) \
+void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); }
+
+DO(ne)
+DO(eq)
+DO(cs)
+DO(cc)
+DO(hs)
+DO(lo)
+DO(mi)
+DO(pl)
+DO(vs)
+DO(vc)
+DO(hi)
+DO(ls)
+DO(ge)
+DO(lt)
+DO(gt)
+DO(le)
+
+/* { dg-final { scan-assembler "bne" } } */
+/* { dg-final { scan-assembler "beq" } } */
+/* { dg-final { scan-assembler "bcs" } } */
+/* { dg-final { scan-assembler "bcc" } } */
+/* { dg-final { scan-assembler "bmi" } } */
+/* { dg-final { scan-assembler "bpl" } } */
+/* { dg-final { scan-assembler "bvs" } } */
+/* { dg-final { scan-assembler "bvc" } } */
+/* { dg-final { scan-assembler "bhi" } } */
+/* { dg-final { scan-assembler "bls" } } */
+/* { dg-final { scan-assembler "bge" } } */
+/* { dg-final { scan-assembler "blt" } } */
+/* { dg-final { scan-assembler "bgt" } } */
+/* { dg-final { scan-assembler "ble" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
new file mode 100644
index 00000000000..4d4394e1478
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
@@ -0,0 +1,30 @@ 
+/* Test error conditions of asm flag outputs.  */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); }
+void f_c(void) { char x; asm("" : "=@cccc"(x)); }
+void f_s(void) { short x; asm("" : "=@cccc"(x)); }
+void f_i(void) { int x; asm("" : "=@cccc"(x)); }
+void f_l(void) { long x; asm("" : "=@cccc"(x)); }
+void f_ll(void) { long long x; asm("" : "=@cccc"(x)); }
+
+void f_f(void)
+{
+  float x;
+  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
+
+void f_d(void)
+{
+  double x;
+  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
+
+struct S { int x[3]; };
+
+void f_S(void)
+{
+  struct S x;
+  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
new file mode 100644
index 00000000000..963b5a48c70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
@@ -0,0 +1,62 @@ 
+/* Executable testcase for 'output flags.'  */
+/* { dg-do run } */
+
+int test_bits (long nzcv)
+{
+  long n, z, c, v;
+
+  __asm__ ("msr nzcv, %[in]"
+	   : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v)
+	   : [in] "r"(nzcv << 28));
+
+  return n * 8 + z * 4 + c * 2 + v == nzcv;
+}
+	
+int test_cmps (long x, long y)
+{
+  long gt, lt, ge, le;
+
+  __asm__ ("cmp %[x], %[y]"
+	   : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le)
+	   : [x] "r"(x), [y] "r"(y));
+
+  return (gt == (x > y)
+	  && lt == (x < y)
+	  && ge == (x >= y)
+	  && le == (x <= y));
+}
+
+int test_cmpu (unsigned long x, unsigned long y)
+{
+  long gt, lt, ge, le;
+
+  __asm__ ("cmp %[x], %[y]"
+	   : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le)
+	   : [x] "r"(x), [y] "r"(y));
+
+  return (gt == (x > y)
+	  && lt == (x < y)
+	  && ge == (x >= y)
+	  && le == (x <= y));
+}
+
+int main ()
+{
+  long i, j;
+
+  for (i = 0; i < 16; ++i)
+    if (!test_bits (i))
+      __builtin_abort ();
+
+  for (i = -1; i <= 1; ++i)
+    for (j = -1; j <= 1; ++j)
+      if (!test_cmps (i, j))
+        __builtin_abort ();
+
+  for (i = 0; i <= 2; ++i)
+    for (j = 0; j <= 2; ++j)
+      if (!test_cmpu (i, j))
+        __builtin_abort ();
+
+  return 0;
+}