[1/2] x86/Intel: make sure MOVSD/CMPSD have their Size32 honored

Message ID 972798d2-4b5c-0b34-363c-6a81b88dacec@suse.com
State New
Headers show
Series
  • x86/Intel: further CMPSD/MOVSD corrections
Related show

Commit Message

Jan Beulich Nov. 7, 2019, 10:18 a.m.
The combination of IgnoreSize and Size32 (or Size16) didn't work right:
While at the top of process_suffix() Size<N> carefully get honored to
force a respective suffix, code later in the function ignored the
attribute when determining whether to emit an insn size prefix. This
fixes a regression from d241b91073 ("x86/Intel: correct MOVSD and CMPSD
handling"). (The Size16 aspect of this can be observed when, just for
this purpose, also adding explicit "movsw" templates. The lack of an
IgnoreSize check in 'q' suffix handling means that no such issue
existed even if explicit "movsq" templates were added.)

Also further extend the test cases added/extended by that commit.

gas/
2019-11-07  Jan Beulich  <jbeulich@suse.com>

	PR/gas 25167
	* config/tc-i386.c (process_suffix): Honor size attribute when
	checking whether to add operand size prefix.
	* testsuite/gas/i386/intel-cmps.s,
	testsuite/gas/i386/intel-movs.s: Extend.
	* testsuite/gas/i386/intel-cmps32.d,
	testsuite/gas/i386/intel-cmps64.d,
	testsuite/gas/i386/intel-movs32.d,
	testsuite/gas/i386/intel-movs64.d: Adjust expectations.
	* testsuite/gas/i386/intel-cmps16.d,
	testsuite/gas/i386/intel-movs16.d: New.
	* testsuite/gas/i386/i386.exp: Run new tests.

Comments

H.J. Lu Nov. 7, 2019, 5:43 p.m. | #1
On Thu, Nov 7, 2019 at 2:18 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> The combination of IgnoreSize and Size32 (or Size16) didn't work right:

> While at the top of process_suffix() Size<N> carefully get honored to

> force a respective suffix, code later in the function ignored the

> attribute when determining whether to emit an insn size prefix. This

> fixes a regression from d241b91073 ("x86/Intel: correct MOVSD and CMPSD

> handling"). (The Size16 aspect of this can be observed when, just for

> this purpose, also adding explicit "movsw" templates. The lack of an

> IgnoreSize check in 'q' suffix handling means that no such issue

> existed even if explicit "movsq" templates were added.)

>

> Also further extend the test cases added/extended by that commit.

>

> gas/

> 2019-11-07  Jan Beulich  <jbeulich@suse.com>

>

>         PR/gas 25167

>         * config/tc-i386.c (process_suffix): Honor size attribute when

>         checking whether to add operand size prefix.

>         * testsuite/gas/i386/intel-cmps.s,

>         testsuite/gas/i386/intel-movs.s: Extend.

>         * testsuite/gas/i386/intel-cmps32.d,

>         testsuite/gas/i386/intel-cmps64.d,

>         testsuite/gas/i386/intel-movs32.d,

>         testsuite/gas/i386/intel-movs64.d: Adjust expectations.

>         * testsuite/gas/i386/intel-cmps16.d,

>         testsuite/gas/i386/intel-movs16.d: New.

>         * testsuite/gas/i386/i386.exp: Run new tests.

>

> --- a/gas/config/tc-i386.c

> +++ b/gas/config/tc-i386.c

> @@ -6466,7 +6466,8 @@ process_suffix (void)

>               return 0;

>         }

>        else if (i.suffix != QWORD_MNEM_SUFFIX

> -              && !i.tm.opcode_modifier.ignoresize

> +              && (!i.tm.opcode_modifier.ignoresize

> +                  || i.tm.opcode_modifier.size)

>                && !i.tm.opcode_modifier.floatmf

>                && !is_any_vex_encoding (&i.tm)

>                && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)


Ignore IgnoreSize with Size looks very odd.  I much prefer to remove CMPSD and
MOVSD support with explicit operands from Intel syntax, which aren't
even in Intel SDM.
We need CMPSD and MOVSD with explicit operands for AT&T syntax only because AT&T
syntax uses suffixes for memory operand size.


--
H.J.
H.J. Lu Nov. 7, 2019, 9:52 p.m. | #2
On Thu, Nov 7, 2019 at 9:43 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> On Thu, Nov 7, 2019 at 2:18 AM Jan Beulich <jbeulich@suse.com> wrote:

> >

> > The combination of IgnoreSize and Size32 (or Size16) didn't work right:

> > While at the top of process_suffix() Size<N> carefully get honored to

> > force a respective suffix, code later in the function ignored the

> > attribute when determining whether to emit an insn size prefix. This

> > fixes a regression from d241b91073 ("x86/Intel: correct MOVSD and CMPSD

> > handling"). (The Size16 aspect of this can be observed when, just for

> > this purpose, also adding explicit "movsw" templates. The lack of an

> > IgnoreSize check in 'q' suffix handling means that no such issue

> > existed even if explicit "movsq" templates were added.)

> >

> > Also further extend the test cases added/extended by that commit.

> >

> > gas/

> > 2019-11-07  Jan Beulich  <jbeulich@suse.com>

> >

> >         PR/gas 25167

> >         * config/tc-i386.c (process_suffix): Honor size attribute when

> >         checking whether to add operand size prefix.

> >         * testsuite/gas/i386/intel-cmps.s,

> >         testsuite/gas/i386/intel-movs.s: Extend.

> >         * testsuite/gas/i386/intel-cmps32.d,

> >         testsuite/gas/i386/intel-cmps64.d,

> >         testsuite/gas/i386/intel-movs32.d,

> >         testsuite/gas/i386/intel-movs64.d: Adjust expectations.

> >         * testsuite/gas/i386/intel-cmps16.d,

> >         testsuite/gas/i386/intel-movs16.d: New.

> >         * testsuite/gas/i386/i386.exp: Run new tests.

> >

> > --- a/gas/config/tc-i386.c

> > +++ b/gas/config/tc-i386.c

> > @@ -6466,7 +6466,8 @@ process_suffix (void)

> >               return 0;

> >         }

> >        else if (i.suffix != QWORD_MNEM_SUFFIX

> > -              && !i.tm.opcode_modifier.ignoresize

> > +              && (!i.tm.opcode_modifier.ignoresize

> > +                  || i.tm.opcode_modifier.size)

> >                && !i.tm.opcode_modifier.floatmf

> >                && !is_any_vex_encoding (&i.tm)

> >                && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)

>

> Ignore IgnoreSize with Size looks very odd.  I much prefer to remove CMPSD and

> MOVSD support with explicit operands from Intel syntax, which aren't

> even in Intel SDM.

> We need CMPSD and MOVSD with explicit operands for AT&T syntax only because AT&T

> syntax uses suffixes for memory operand size.

>


Another problem is Intel syntax sets instruction suffix from operand size:

[hjl@gnu-cfl-1 gas]$ cat 2.s
.intel_syntax noprefix
call WORD PTR [rax]
[hjl@gnu-cfl-1 gas]$ as -mintel64 -o 2.o 2.s
2.s: Assembler messages:
2.s:2: Error: invalid instruction suffix for `call'
[hjl@gnu-cfl-1 gas]$

It is operand size mismatch, not invalid instruction suffix.  In case
of CMPSD and
and MOVSD,the 'l' suffix is invalid, not DWORD on memory operand.  But suffix
check treats them the same.  This makes Intel syntax more complicated.   Should
Intel syntax disallow suffix in mnemonic?  It will make Intel syntax
closer to SDM.


-- 
H.J.
Jan Beulich Nov. 8, 2019, 7:37 a.m. | #3
On 07.11.2019 18:43,  H.J. Lu  wrote:
> On Thu, Nov 7, 2019 at 2:18 AM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> The combination of IgnoreSize and Size32 (or Size16) didn't work right:

>> While at the top of process_suffix() Size<N> carefully get honored to

>> force a respective suffix, code later in the function ignored the

>> attribute when determining whether to emit an insn size prefix. This

>> fixes a regression from d241b91073 ("x86/Intel: correct MOVSD and CMPSD

>> handling"). (The Size16 aspect of this can be observed when, just for

>> this purpose, also adding explicit "movsw" templates. The lack of an

>> IgnoreSize check in 'q' suffix handling means that no such issue

>> existed even if explicit "movsq" templates were added.)

>>

>> Also further extend the test cases added/extended by that commit.

>>

>> gas/

>> 2019-11-07  Jan Beulich  <jbeulich@suse.com>

>>

>>         PR/gas 25167

>>         * config/tc-i386.c (process_suffix): Honor size attribute when

>>         checking whether to add operand size prefix.

>>         * testsuite/gas/i386/intel-cmps.s,

>>         testsuite/gas/i386/intel-movs.s: Extend.

>>         * testsuite/gas/i386/intel-cmps32.d,

>>         testsuite/gas/i386/intel-cmps64.d,

>>         testsuite/gas/i386/intel-movs32.d,

>>         testsuite/gas/i386/intel-movs64.d: Adjust expectations.

>>         * testsuite/gas/i386/intel-cmps16.d,

>>         testsuite/gas/i386/intel-movs16.d: New.

>>         * testsuite/gas/i386/i386.exp: Run new tests.

>>

>> --- a/gas/config/tc-i386.c

>> +++ b/gas/config/tc-i386.c

>> @@ -6466,7 +6466,8 @@ process_suffix (void)

>>               return 0;

>>         }

>>        else if (i.suffix != QWORD_MNEM_SUFFIX

>> -              && !i.tm.opcode_modifier.ignoresize

>> +              && (!i.tm.opcode_modifier.ignoresize

>> +                  || i.tm.opcode_modifier.size)

>>                && !i.tm.opcode_modifier.floatmf

>>                && !is_any_vex_encoding (&i.tm)

>>                && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)

> 

> Ignore IgnoreSize with Size looks very odd.


IgnoreSize and Size<N> have different purposes. Combining them
doesn't happen very often, but if you go look you'll find that
there are more cases than just the two insns here. The reason a
similar construct isn't needed for QWORD_MNEM_SUFFIX is simply
because there's no checking of i.tm.opcode_modifier.ignoresize
to begin with. If there was, I'm sure Size would need to be
honored there as well.

>  I much prefer to remove CMPSD and

> MOVSD support with explicit operands from Intel syntax, which aren't

> even in Intel SDM.


Intel SDM isn't the only (or even the main) reference here. MASM
is what we want to be compatible with as much as possible. And
even without that, without explicit operands code needing to set
a segment override or non-default address size reads far more
clumsy.

As an aside - why did you ask to fix the regression (and even
supplied a change to do so on your own) when at the same time
you'd prefer to see these templates go away (which, as said, they
can't).

> We need CMPSD and MOVSD with explicit operands for AT&T syntax only because AT&T

> syntax uses suffixes for memory operand size.


There's no such thing as string insns named CMPSD or MOVSD in AT&T
syntax - it's CMPSL and MOVSL there. CMPSD and MOVSD are solely
SSE2 insns there.

Jan
Jan Beulich Nov. 8, 2019, 7:41 a.m. | #4
On 07.11.2019 22:52,  H.J. Lu  wrote:
> Another problem is Intel syntax sets instruction suffix from operand size:


An unrelated one, but yes.

> [hjl@gnu-cfl-1 gas]$ cat 2.s

> .intel_syntax noprefix

> call WORD PTR [rax]

> [hjl@gnu-cfl-1 gas]$ as -mintel64 -o 2.o 2.s

> 2.s: Assembler messages:

> 2.s:2: Error: invalid instruction suffix for `call'

> [hjl@gnu-cfl-1 gas]$

> 

> It is operand size mismatch, not invalid instruction suffix.  In case

> of CMPSD and

> and MOVSD,the 'l' suffix is invalid, not DWORD on memory operand.  But suffix

> check treats them the same.  This makes Intel syntax more complicated.   Should

> Intel syntax disallow suffix in mnemonic?  It will make Intel syntax

> closer to SDM.


There are some suffixes that need honoring. The original authors
of the code apparently decided that it's better to accept some
stray/bogus suffixes than to further complicate the code. I guess
once we have the No_*Suf attributes put straight (as mentioned by
Michael the other day, matching plans I've been having), then we
could see about further cleaning up Intel syntax behavior here.

Jan
H.J. Lu Nov. 8, 2019, 3:53 p.m. | #5
On Thu, Nov 7, 2019 at 11:41 PM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 07.11.2019 22:52,  H.J. Lu  wrote:

> > Another problem is Intel syntax sets instruction suffix from operand size:

>

> An unrelated one, but yes.

>

> > [hjl@gnu-cfl-1 gas]$ cat 2.s

> > .intel_syntax noprefix

> > call WORD PTR [rax]

> > [hjl@gnu-cfl-1 gas]$ as -mintel64 -o 2.o 2.s

> > 2.s: Assembler messages:

> > 2.s:2: Error: invalid instruction suffix for `call'

> > [hjl@gnu-cfl-1 gas]$

> >

> > It is operand size mismatch, not invalid instruction suffix.  In case

> > of CMPSD and

> > and MOVSD,the 'l' suffix is invalid, not DWORD on memory operand.  But suffix

> > check treats them the same.  This makes Intel syntax more complicated.   Should

> > Intel syntax disallow suffix in mnemonic?  It will make Intel syntax

> > closer to SDM.

>

> There are some suffixes that need honoring. The original authors

> of the code apparently decided that it's better to accept some

> stray/bogus suffixes than to further complicate the code. I guess

> once we have the No_*Suf attributes put straight (as mentioned by

> Michael the other day, matching plans I've been having), then we

> could see about further cleaning up Intel syntax behavior here.

>


I am checking in this.

We should check suffix in instruction mnemonic when matching instruction.
In Intel syntax, normally we check for memory operand size.  But the same
mnemonic with 2 different encodings can have the same memory operand
size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand
size in Intel syntax to distinguish them.  When there is no suffix in
mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic
suffix.

gas/

PR gas/25167
* config/tc-i386.c (match_template): Don't check instruction
suffix set from operand.
* testsuite/gas/i386/code16.d: New file.
* testsuite/gas/i386/code16.s: Likewise.
* testsuite/gas/i386/i386.exp: Run code16.

opcodes/

PR gas/25167
* i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
* i386-tbl.h: Regenerated.


-- 
H.J.
Jan Beulich Nov. 11, 2019, 11:06 a.m. | #6
On 08.11.2019 16:53, H.J. Lu wrote:
> On Thu, Nov 7, 2019 at 11:41 PM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> On 07.11.2019 22:52,  H.J. Lu  wrote:

>>> Another problem is Intel syntax sets instruction suffix from operand size:

>>

>> An unrelated one, but yes.

>>

>>> [hjl@gnu-cfl-1 gas]$ cat 2.s

>>> .intel_syntax noprefix

>>> call WORD PTR [rax]

>>> [hjl@gnu-cfl-1 gas]$ as -mintel64 -o 2.o 2.s

>>> 2.s: Assembler messages:

>>> 2.s:2: Error: invalid instruction suffix for `call'

>>> [hjl@gnu-cfl-1 gas]$

>>>

>>> It is operand size mismatch, not invalid instruction suffix.  In case

>>> of CMPSD and

>>> and MOVSD,the 'l' suffix is invalid, not DWORD on memory operand.  But suffix

>>> check treats them the same.  This makes Intel syntax more complicated.   Should

>>> Intel syntax disallow suffix in mnemonic?  It will make Intel syntax

>>> closer to SDM.

>>

>> There are some suffixes that need honoring. The original authors

>> of the code apparently decided that it's better to accept some

>> stray/bogus suffixes than to further complicate the code. I guess

>> once we have the No_*Suf attributes put straight (as mentioned by

>> Michael the other day, matching plans I've been having), then we

>> could see about further cleaning up Intel syntax behavior here.

>>

> 

> I am checking in this.

> 

> We should check suffix in instruction mnemonic when matching instruction.

> In Intel syntax, normally we check for memory operand size.  But the same

> mnemonic with 2 different encodings can have the same memory operand

> size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand

> size in Intel syntax to distinguish them.  When there is no suffix in

> mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic

> suffix.


So even after quite a bit of checking and thinking my gut feeling
still is that this may have broken some corner cases. But I can't
come up with a specific example, so maybe all is well.

On the positive side this fixes MOVDIRI handling: Previously only
the operand-size less cases below would have been accepted, whereas
now all 6 valid ones remain without diagnostic.

I suspect though that your change should have been accompanied
with further IgnoreSize dropping, as I think quite a few that we
still have in there are no longer needed now.

Btw, would you mind me putting in the testsuite parts of the
alternative patches I had sent for this PR?

Jan

	movdiri [rcx], eax
	movdiri dword ptr [rcx], eax
	movdiri qword ptr [rcx], eax

	movdiri [rcx], rax
	movdiri dword ptr [rcx], rax
	movdiri qword ptr [rcx], rax

	.code32
	movdiri [ecx], eax
	movdiri dword ptr [ecx], eax
	movdiri qword ptr [ecx], eax
H.J. Lu Nov. 11, 2019, 5:04 p.m. | #7
On Mon, Nov 11, 2019 at 3:06 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 08.11.2019 16:53, H.J. Lu wrote:

> > On Thu, Nov 7, 2019 at 11:41 PM Jan Beulich <jbeulich@suse.com> wrote:

> >>

> >> On 07.11.2019 22:52,  H.J. Lu  wrote:

> >>> Another problem is Intel syntax sets instruction suffix from operand size:

> >>

> >> An unrelated one, but yes.

> >>

> >>> [hjl@gnu-cfl-1 gas]$ cat 2.s

> >>> .intel_syntax noprefix

> >>> call WORD PTR [rax]

> >>> [hjl@gnu-cfl-1 gas]$ as -mintel64 -o 2.o 2.s

> >>> 2.s: Assembler messages:

> >>> 2.s:2: Error: invalid instruction suffix for `call'

> >>> [hjl@gnu-cfl-1 gas]$

> >>>

> >>> It is operand size mismatch, not invalid instruction suffix.  In case

> >>> of CMPSD and

> >>> and MOVSD,the 'l' suffix is invalid, not DWORD on memory operand.  But suffix

> >>> check treats them the same.  This makes Intel syntax more complicated.   Should

> >>> Intel syntax disallow suffix in mnemonic?  It will make Intel syntax

> >>> closer to SDM.

> >>

> >> There are some suffixes that need honoring. The original authors

> >> of the code apparently decided that it's better to accept some

> >> stray/bogus suffixes than to further complicate the code. I guess

> >> once we have the No_*Suf attributes put straight (as mentioned by

> >> Michael the other day, matching plans I've been having), then we

> >> could see about further cleaning up Intel syntax behavior here.

> >>

> >

> > I am checking in this.

> >

> > We should check suffix in instruction mnemonic when matching instruction.

> > In Intel syntax, normally we check for memory operand size.  But the same

> > mnemonic with 2 different encodings can have the same memory operand

> > size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand

> > size in Intel syntax to distinguish them.  When there is no suffix in

> > mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic

> > suffix.

>

> So even after quite a bit of checking and thinking my gut feeling

> still is that this may have broken some corner cases. But I can't

> come up with a specific example, so maybe all is well.

>

> On the positive side this fixes MOVDIRI handling: Previously only

> the operand-size less cases below would have been accepted, whereas

> now all 6 valid ones remain without diagnostic.

>

> I suspect though that your change should have been accompanied

> with further IgnoreSize dropping, as I think quite a few that we

> still have in there are no longer needed now.


I agree.

> Btw, would you mind me putting in the testsuite parts of the

> alternative patches I had sent for this PR?

>

> Jan

>

>         movdiri [rcx], eax

>         movdiri dword ptr [rcx], eax

>         movdiri qword ptr [rcx], eax

>

>         movdiri [rcx], rax

>         movdiri dword ptr [rcx], rax

>         movdiri qword ptr [rcx], rax

>

>         .code32

>         movdiri [ecx], eax

>         movdiri dword ptr [ecx], eax

>         movdiri qword ptr [ecx], eax

>


Can you submit a patch?

Thanks.

-- 
H.J.
Jan Beulich Nov. 12, 2019, 7:16 a.m. | #8
On 11.11.2019 18:04,  H.J. Lu  wrote:
> On Mon, Nov 11, 2019 at 3:06 AM Jan Beulich <jbeulich@suse.com> wrote:

>> On the positive side this fixes MOVDIRI handling: Previously only

>> the operand-size less cases below would have been accepted, whereas

>> now all 6 valid ones remain without diagnostic.


(Leaving this in context for the question below.)

>> Btw, would you mind me putting in the testsuite parts of the

>> alternative patches I had sent for this PR?


[You didn't reply to this at all.]

>>         movdiri [rcx], eax

>>         movdiri dword ptr [rcx], eax

>>         movdiri qword ptr [rcx], eax

>>

>>         movdiri [rcx], rax

>>         movdiri dword ptr [rcx], rax

>>         movdiri qword ptr [rcx], rax

>>

>>         .code32

>>         movdiri [ecx], eax

>>         movdiri dword ptr [ecx], eax

>>         movdiri qword ptr [ecx], eax

>>

> 

> Can you submit a patch?


A patch to do what? Extend existing testcases? Shouldn't this
once again have been the job of the person adding support for
the insn?

Jan
H.J. Lu Nov. 12, 2019, 8:43 p.m. | #9
On Mon, Nov 11, 2019 at 11:16 PM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 11.11.2019 18:04,  H.J. Lu  wrote:

> > On Mon, Nov 11, 2019 at 3:06 AM Jan Beulich <jbeulich@suse.com> wrote:

> >> On the positive side this fixes MOVDIRI handling: Previously only

> >> the operand-size less cases below would have been accepted, whereas

> >> now all 6 valid ones remain without diagnostic.

>

> (Leaving this in context for the question below.)

>

> >> Btw, would you mind me putting in the testsuite parts of the

> >> alternative patches I had sent for this PR?

>

> [You didn't reply to this at all.]


Sure, please submit a patch.

> >>         movdiri [rcx], eax

> >>         movdiri dword ptr [rcx], eax

> >>         movdiri qword ptr [rcx], eax

> >>

> >>         movdiri [rcx], rax

> >>         movdiri dword ptr [rcx], rax

> >>         movdiri qword ptr [rcx], rax

> >>

> >>         .code32

> >>         movdiri [ecx], eax

> >>         movdiri dword ptr [ecx], eax

> >>         movdiri qword ptr [ecx], eax

> >>

> >

> > Can you submit a patch?

>

> A patch to do what? Extend existing testcases? Shouldn't this

> once again have been the job of the person adding support for

> the insn?

>


I'd like to avoid touching Intel syntax.

-- 
H.J.
Jan Beulich Nov. 13, 2019, 1:22 p.m. | #10
On 12.11.2019 21:43,  H.J. Lu  wrote:
> On Mon, Nov 11, 2019 at 11:16 PM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> On 11.11.2019 18:04,  H.J. Lu  wrote:

>>> On Mon, Nov 11, 2019 at 3:06 AM Jan Beulich <jbeulich@suse.com> wrote:

>>>> On the positive side this fixes MOVDIRI handling: Previously only

>>>> the operand-size less cases below would have been accepted, whereas

>>>> now all 6 valid ones remain without diagnostic.

>>

>> (Leaving this in context for the question below.)

>>

>>>> Btw, would you mind me putting in the testsuite parts of the

>>>> alternative patches I had sent for this PR?

>>

>> [You didn't reply to this at all.]

> 

> Sure, please submit a patch.


Well, I did submit a pair of them already, and my question is if I
may put them in with the tc-i386.c change dropped.

>>>>         movdiri [rcx], eax

>>>>         movdiri dword ptr [rcx], eax

>>>>         movdiri qword ptr [rcx], eax

>>>>

>>>>         movdiri [rcx], rax

>>>>         movdiri dword ptr [rcx], rax

>>>>         movdiri qword ptr [rcx], rax

>>>>

>>>>         .code32

>>>>         movdiri [ecx], eax

>>>>         movdiri dword ptr [ecx], eax

>>>>         movdiri qword ptr [ecx], eax

>>>>

>>>

>>> Can you submit a patch?

>>

>> A patch to do what? Extend existing testcases? Shouldn't this

>> once again have been the job of the person adding support for

>> the insn?

> 

> I'd like to avoid touching Intel syntax.


So what are the answers to the first two questions then?

Jan
H.J. Lu Nov. 13, 2019, 9:10 p.m. | #11
On Wed, Nov 13, 2019 at 5:21 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 12.11.2019 21:43,  H.J. Lu  wrote:

> > On Mon, Nov 11, 2019 at 11:16 PM Jan Beulich <jbeulich@suse.com> wrote:

> >>

> >> On 11.11.2019 18:04,  H.J. Lu  wrote:

> >>> On Mon, Nov 11, 2019 at 3:06 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>>> On the positive side this fixes MOVDIRI handling: Previously only

> >>>> the operand-size less cases below would have been accepted, whereas

> >>>> now all 6 valid ones remain without diagnostic.

> >>

> >> (Leaving this in context for the question below.)

> >>

> >>>> Btw, would you mind me putting in the testsuite parts of the

> >>>> alternative patches I had sent for this PR?

> >>

> >> [You didn't reply to this at all.]

> >

> > Sure, please submit a patch.

>

> Well, I did submit a pair of them already, and my question is if I

> may put them in with the tc-i386.c change dropped.


Please submit a new one without the tc-i386.c change.  If it only
updates Intel syntax tests, it is pre-approved.

> >>>>         movdiri [rcx], eax

> >>>>         movdiri dword ptr [rcx], eax

> >>>>         movdiri qword ptr [rcx], eax

> >>>>

> >>>>         movdiri [rcx], rax

> >>>>         movdiri dword ptr [rcx], rax

> >>>>         movdiri qword ptr [rcx], rax

> >>>>

> >>>>         .code32

> >>>>         movdiri [ecx], eax

> >>>>         movdiri dword ptr [ecx], eax

> >>>>         movdiri qword ptr [ecx], eax

> >>>>

> >>>

> >>> Can you submit a patch?

> >>

> >> A patch to do what? Extend existing testcases? Shouldn't this

> >> once again have been the job of the person adding support for

> >> the insn?

> >

> > I'd like to avoid touching Intel syntax.

>

> So what are the answers to the first two questions then?

>


What are the questions again?

-- 
H.J.
Jan Beulich Nov. 14, 2019, 7:22 a.m. | #12
On 13.11.2019 22:10,  H.J. Lu  wrote:
> On Wed, Nov 13, 2019 at 5:21 AM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> On 12.11.2019 21:43,  H.J. Lu  wrote:

>>> On Mon, Nov 11, 2019 at 11:16 PM Jan Beulich <jbeulich@suse.com> wrote:

>>>>

>>>> On 11.11.2019 18:04,  H.J. Lu  wrote:

>>>>> On Mon, Nov 11, 2019 at 3:06 AM Jan Beulich <jbeulich@suse.com> wrote:

>>>>>> On the positive side this fixes MOVDIRI handling: Previously only

>>>>>> the operand-size less cases below would have been accepted, whereas

>>>>>> now all 6 valid ones remain without diagnostic.

>>>>

>>>> (Leaving this in context for the question below.)

>>>>

>>>>>> Btw, would you mind me putting in the testsuite parts of the

>>>>>> alternative patches I had sent for this PR?

>>>>

>>>> [You didn't reply to this at all.]

>>>

>>> Sure, please submit a patch.

>>

>> Well, I did submit a pair of them already, and my question is if I

>> may put them in with the tc-i386.c change dropped.

> 

> Please submit a new one without the tc-i386.c change.


Done.

>  If it only updates Intel syntax tests, it is pre-approved.


I realize that strictly speaking I wouldn't have needed approval
here, and hence should simply have gone ahead anyway.

>>>>>>         movdiri [rcx], eax

>>>>>>         movdiri dword ptr [rcx], eax

>>>>>>         movdiri qword ptr [rcx], eax

>>>>>>

>>>>>>         movdiri [rcx], rax

>>>>>>         movdiri dword ptr [rcx], rax

>>>>>>         movdiri qword ptr [rcx], rax

>>>>>>

>>>>>>         .code32

>>>>>>         movdiri [ecx], eax

>>>>>>         movdiri dword ptr [ecx], eax

>>>>>>         movdiri qword ptr [ecx], eax

>>>>>>

>>>>>

>>>>> Can you submit a patch?

>>>>

>>>> A patch to do what? Extend existing testcases? Shouldn't this

>>>> once again have been the job of the person adding support for

>>>> the insn?

>>>

>>> I'd like to avoid touching Intel syntax.

>>

>> So what are the answers to the first two questions then?

>>

> 

> What are the questions again?


You asked "Can you submit a patch?" which I responded to asking
"A patch to do what?"

Jan
H.J. Lu Nov. 14, 2019, 7:28 p.m. | #13
On Wed, Nov 13, 2019 at 11:22 PM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 13.11.2019 22:10,  H.J. Lu  wrote:

> > On Wed, Nov 13, 2019 at 5:21 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>

> >> On 12.11.2019 21:43,  H.J. Lu  wrote:

> >>> On Mon, Nov 11, 2019 at 11:16 PM Jan Beulich <jbeulich@suse.com> wrote:

> >>>>

> >>>> On 11.11.2019 18:04,  H.J. Lu  wrote:

> >>>>> On Mon, Nov 11, 2019 at 3:06 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>>>>> On the positive side this fixes MOVDIRI handling: Previously only

> >>>>>> the operand-size less cases below would have been accepted, whereas

> >>>>>> now all 6 valid ones remain without diagnostic.

> >>>>

> >>>> (Leaving this in context for the question below.)

> >>>>

> >>>>>> Btw, would you mind me putting in the testsuite parts of the

> >>>>>> alternative patches I had sent for this PR?

> >>>>

> >>>> [You didn't reply to this at all.]

> >>>

> >>> Sure, please submit a patch.

> >>

> >> Well, I did submit a pair of them already, and my question is if I

> >> may put them in with the tc-i386.c change dropped.

> >

> > Please submit a new one without the tc-i386.c change.

>

> Done.

>

> >  If it only updates Intel syntax tests, it is pre-approved.

>

> I realize that strictly speaking I wouldn't have needed approval

> here, and hence should simply have gone ahead anyway.

>

> >>>>>>         movdiri [rcx], eax

> >>>>>>         movdiri dword ptr [rcx], eax

> >>>>>>         movdiri qword ptr [rcx], eax

> >>>>>>

> >>>>>>         movdiri [rcx], rax

> >>>>>>         movdiri dword ptr [rcx], rax

> >>>>>>         movdiri qword ptr [rcx], rax

> >>>>>>

> >>>>>>         .code32

> >>>>>>         movdiri [ecx], eax

> >>>>>>         movdiri dword ptr [ecx], eax

> >>>>>>         movdiri qword ptr [ecx], eax

> >>>>>>

> >>>>>

> >>>>> Can you submit a patch?

> >>>>

> >>>> A patch to do what? Extend existing testcases? Shouldn't this

> >>>> once again have been the job of the person adding support for

> >>>> the insn?

> >>>

> >>> I'd like to avoid touching Intel syntax.

> >>

> >> So what are the answers to the first two questions then?

> >>

> >

> > What are the questions again?

>

> You asked "Can you submit a patch?" which I responded to asking

> "A patch to do what?"


I thought you were asking for test changes.


-- 
H.J.

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6466,7 +6466,8 @@  process_suffix (void)
 	      return 0;
 	}
       else if (i.suffix != QWORD_MNEM_SUFFIX
-	       && !i.tm.opcode_modifier.ignoresize
+	       && (!i.tm.opcode_modifier.ignoresize
+		   || i.tm.opcode_modifier.size)
 	       && !i.tm.opcode_modifier.floatmf
 	       && !is_any_vex_encoding (&i.tm)
 	       && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -531,7 +531,9 @@  if [expr ([istarget "i*86-*-*"] ||  [ist
 	run_list_test "reloc32" "--defsym _bad_=1"
 	run_dump_test "intel-got32"
 	run_dump_test "intel-movs32"
+	run_dump_test "intel-movs16"
 	run_dump_test "intel-cmps32"
+	run_dump_test "intel-cmps16"
 	run_list_test "inval-equ-1" "-al"
 	run_list_test "inval-equ-2" "-al"
 	run_dump_test "ifunc"
--- a/gas/testsuite/gas/i386/intel-cmps.s
+++ b/gas/testsuite/gas/i386/intel-cmps.s
@@ -1,8 +1,20 @@ 
 	.text
 	.intel_syntax noprefix
+.ifdef x86_16
+	.code16
+.endif
+
+.ifdef x86_64
+ .equ adi, rdi
+ .equ asi, rsi
+.else
+ .equ adi, di
+ .equ asi, si
+.endif
 
 cmps:
 	cmpsb
+
 	cmpsb	[esi], es:[edi]
 	cmpsb	fs:[esi], es:[edi]
 	cmpsb	[esi], [edi]
@@ -13,7 +25,18 @@  cmps:
 	cmps	[esi], byte ptr es:[edi]
 	cmps	byte ptr [esi], byte ptr es:[edi]
 
+	cmpsb	[asi], es:[adi]
+	cmpsb	fs:[asi], es:[adi]
+	cmpsb	[asi], [adi]
+	cmpsb	byte ptr [asi], es:[adi]
+	cmpsb	[asi], byte ptr es:[adi]
+	cmpsb	byte ptr [asi], byte ptr es:[adi]
+	cmps	byte ptr [asi], es:[adi]
+	cmps	[asi], byte ptr es:[adi]
+	cmps	byte ptr [asi], byte ptr es:[adi]
+
 	cmpsw
+
 	cmpsw	[esi], es:[edi]
 	cmpsw	fs:[esi], es:[edi]
 	cmpsw	[esi], [edi]
@@ -24,7 +47,18 @@  cmps:
 	cmps	[esi], word ptr es:[edi]
 	cmps	word ptr [esi], word ptr es:[edi]
 
+	cmpsw	[asi], es:[adi]
+	cmpsw	fs:[asi], es:[adi]
+	cmpsw	[asi], [adi]
+	cmpsw	word ptr [asi], es:[adi]
+	cmpsw	[asi], word ptr es:[adi]
+	cmpsw	word ptr [asi], word ptr es:[adi]
+	cmps	word ptr [asi], es:[adi]
+	cmps	[asi], word ptr es:[adi]
+	cmps	word ptr [asi], word ptr es:[adi]
+
 	cmpsd
+
 	cmpsd	[esi], es:[edi]
 	cmpsd	fs:[esi], es:[edi]
 	cmpsd	[esi], [edi]
@@ -35,8 +69,19 @@  cmps:
 	cmps	[esi], dword ptr es:[edi]
 	cmps	dword ptr [esi], dword ptr es:[edi]
 
+	cmpsd	[asi], es:[adi]
+	cmpsd	fs:[asi], es:[adi]
+	cmpsd	[asi], [adi]
+	cmpsd	dword ptr [asi], es:[adi]
+	cmpsd	[asi], dword ptr es:[adi]
+	cmpsd	dword ptr [asi], dword ptr es:[adi]
+	cmps	dword ptr [asi], es:[adi]
+	cmps	[asi], dword ptr es:[adi]
+	cmps	dword ptr [asi], dword ptr es:[adi]
+
 .ifdef x86_64
 	cmpsq
+
 	cmpsq	[rsi], es:[rdi]
 	cmpsq	fs:[rsi], es:[rdi]
 	cmpsq	[rsi], [rdi]
@@ -46,4 +91,14 @@  cmps:
 	cmps	qword ptr [rsi], es:[rdi]
 	cmps	[rsi], qword ptr es:[rdi]
 	cmps	qword ptr [rsi], qword ptr es:[rdi]
+
+	cmpsq	[esi], es:[edi]
+	cmpsq	fs:[esi], es:[edi]
+	cmpsq	[esi], [edi]
+	cmpsq	qword ptr [esi], es:[edi]
+	cmpsq	[esi], qword ptr es:[edi]
+	cmpsq	qword ptr [esi], qword ptr es:[edi]
+	cmps	qword ptr [esi], es:[edi]
+	cmps	[esi], qword ptr es:[edi]
+	cmps	qword ptr [esi], qword ptr es:[edi]
 .endif
--- /dev/null
+++ b/gas/testsuite/gas/i386/intel-cmps16.d
@@ -0,0 +1,68 @@ 
+#as: --defsym x86_16=1
+#objdump: -dMintel -Mi8086
+#source: intel-cmps.s
+#name: x86 Intel cmps (16-bit code)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <cmps>:
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	64 67 a6 *	cmps +BYTE PTR fs:\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	64 a6 *	cmps +BYTE PTR fs:\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	64 67 a7 *	cmps +WORD PTR fs:\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	64 a7 *	cmps +WORD PTR fs:\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(w *| +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	64 67 66 a7 *	cmps +DWORD PTR fs:?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	64 66 a7 *	cmps +DWORD PTR fs:?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(d *| +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\])
+#pass
--- a/gas/testsuite/gas/i386/intel-cmps32.d
+++ b/gas/testsuite/gas/i386/intel-cmps32.d
@@ -17,6 +17,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[esi\]),(BYTE PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[esi\]),(BYTE PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[esi\]),(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	64 67 a6 *	cmps +BYTE PTR fs:\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[si\],(BYTE PTR )?es:\[di\]
 [ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[esi\]),(WORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[esi\]),(WORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	64 66 a7 *	cmps +WORD PTR fs:\[esi\],(WORD PTR )?es:\[edi\]
@@ -27,6 +36,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[esi\]),(WORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[esi\]),(WORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[esi\]),(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	64 67 66 a7 *	cmps +WORD PTR fs:\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[si\],(WORD PTR )?es:\[di\]
 [ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[esi\]),(DWORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[esi\]),(DWORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	64 a7 *	cmps +DWORD PTR fs:?\[esi\],(DWORD PTR )?es:\[edi\]
@@ -37,4 +55,13 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[esi\]),(DWORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[esi\]),(DWORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[esi\]),(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	64 67 a7 *	cmps +DWORD PTR fs:?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\]
+[ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[si\],(DWORD PTR )?es:\[di\]
 #pass
--- a/gas/testsuite/gas/i386/intel-cmps64.d
+++ b/gas/testsuite/gas/i386/intel-cmps64.d
@@ -17,6 +17,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	67 a6 *	cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	64 a6 *	cmps +BYTE PTR fs:\[rsi\],(BYTE PTR )?es:\[rdi\]
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a6 *	cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\])
 [ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\]),(WORD PTR )?es:\[rdi\]
 [ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	64 67 66 a7 *	cmps +WORD PTR fs:\[esi\],(WORD PTR )?es:\[edi\]
@@ -27,6 +36,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	67 66 a7 *	cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	64 66 a7 *	cmps +WORD PTR fs:\[rsi\],(WORD PTR )?es:\[rdi\]
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	66 a7 *	cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\])
 [ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\]),(DWORD PTR )?es:\[rdi\]
 [ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	64 67 a7 *	cmps +DWORD PTR fs:\[esi\],(DWORD PTR )?es:\[edi\]
@@ -37,6 +55,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
 [ 	]*[a-f0-9]+:	67 a7 *	cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	64 a7 *	cmps +DWORD PTR fs:\[rsi\],(DWORD PTR )?es:\[rdi\]
+[ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\])
+[ 	]*[a-f0-9]+:	a7 *	cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\])
 [ 	]*[a-f0-9]+:	48 a7 *	cmps(q *| +QWORD PTR (ds:)?\[rsi\]),(QWORD PTR )?es:\[rdi\]
 [ 	]*[a-f0-9]+:	48 a7 *	cmps(q *| +QWORD PTR (ds:)?\[rsi\]),(QWORD PTR )?es:\[rdi\]
 [ 	]*[a-f0-9]+:	64 48 a7 *	cmps +QWORD PTR fs:?\[rsi\],(QWORD PTR )?es:\[rdi\]
@@ -47,4 +74,13 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	48 a7 *	cmps(q *| +QWORD PTR (ds:)?\[rsi\]),(QWORD PTR )?es:\[rdi\]
 [ 	]*[a-f0-9]+:	48 a7 *	cmps(q *| +QWORD PTR (ds:)?\[rsi\]),(QWORD PTR )?es:\[rdi\]
 [ 	]*[a-f0-9]+:	48 a7 *	cmps(q *| +QWORD PTR (ds:)?\[rsi\]),(QWORD PTR )?es:\[rdi\]
+[ 	]*[a-f0-9]+:	67 48 a7 *	cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	64 67 48 a7 *	cmps +QWORD PTR fs:?\[esi\],(QWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 48 a7 *	cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 48 a7 *	cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 48 a7 *	cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 48 a7 *	cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 48 a7 *	cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 48 a7 *	cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\]
+[ 	]*[a-f0-9]+:	67 48 a7 *	cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\]
 #pass
--- a/gas/testsuite/gas/i386/intel-movs.s
+++ b/gas/testsuite/gas/i386/intel-movs.s
@@ -1,8 +1,20 @@ 
 	.text
 	.intel_syntax noprefix
+.ifdef x86_16
+	.code16
+.endif
+
+.ifdef x86_64
+ .equ adi, rdi
+ .equ asi, rsi
+.else
+ .equ adi, di
+ .equ asi, si
+.endif
 
 movs:
 	movsb
+
 	movsb	es:[edi], [esi]
 	movsb	es:[edi], fs:[esi]
 	movsb	[edi], [esi]
@@ -13,7 +25,18 @@  movs:
 	movs	es:[edi], byte ptr [esi]
 	movs	byte ptr es:[edi], byte ptr [esi]
 
+	movsb	es:[adi], [asi]
+	movsb	es:[adi], fs:[asi]
+	movsb	[adi], [asi]
+	movsb	byte ptr es:[adi], [asi]
+	movsb	es:[adi], byte ptr [asi]
+	movsb	byte ptr es:[adi], byte ptr [asi]
+	movs	byte ptr es:[adi], [asi]
+	movs	es:[adi], byte ptr [asi]
+	movs	byte ptr es:[adi], byte ptr [asi]
+
 	movsw
+
 	movsw	es:[edi], [esi]
 	movsw	es:[edi], fs:[esi]
 	movsw	[edi], [esi]
@@ -24,7 +47,18 @@  movs:
 	movs	es:[edi], word ptr [esi]
 	movs	word ptr es:[edi], word ptr [esi]
 
+	movsw	es:[adi], [asi]
+	movsw	es:[adi], fs:[asi]
+	movsw	[adi], [asi]
+	movsw	word ptr es:[adi], [asi]
+	movsw	es:[adi], word ptr [asi]
+	movsw	word ptr es:[adi], word ptr [asi]
+	movs	word ptr es:[adi], [asi]
+	movs	es:[adi], word ptr [asi]
+	movs	word ptr es:[adi], word ptr [asi]
+
 	movsd
+
 	movsd	es:[edi], [esi]
 	movsd	es:[edi], fs:[esi]
 	movsd	[edi], [esi]
@@ -35,8 +69,19 @@  movs:
 	movs	es:[edi], dword ptr [esi]
 	movs	dword ptr es:[edi], dword ptr [esi]
 
+	movsd	es:[adi], [asi]
+	movsd	es:[adi], fs:[asi]
+	movsd	[adi], [asi]
+	movsd	dword ptr es:[adi], [asi]
+	movsd	es:[adi], dword ptr [asi]
+	movsd	dword ptr es:[adi], dword ptr [asi]
+	movs	dword ptr es:[adi], [asi]
+	movs	es:[adi], dword ptr [asi]
+	movs	dword ptr es:[adi], dword ptr [asi]
+
 .ifdef x86_64
 	movsq
+
 	movsq	es:[rdi], [rsi]
 	movsq	es:[rdi], fs:[rsi]
 	movsq	[rdi], [rsi]
@@ -46,4 +91,14 @@  movs:
 	movs	qword ptr es:[rdi], [rsi]
 	movs	es:[rdi], qword ptr [rsi]
 	movs	qword ptr es:[rdi], qword ptr [rsi]
+
+	movsq	es:[edi], [esi]
+	movsq	es:[edi], fs:[esi]
+	movsq	[edi], [esi]
+	movsq	qword ptr es:[edi], [esi]
+	movsq	es:[edi], qword ptr [esi]
+	movsq	qword ptr es:[edi], qword ptr [esi]
+	movs	qword ptr es:[edi], [esi]
+	movs	es:[edi], qword ptr [esi]
+	movs	qword ptr es:[edi], qword ptr [esi]
 .endif
--- /dev/null
+++ b/gas/testsuite/gas/i386/intel-movs16.d
@@ -0,0 +1,68 @@ 
+#as: --defsym x86_16=1
+#objdump: -dMintel -Mi8086
+#source: intel-movs.s
+#name: x86 Intel movs (16-bit code)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <movs>:
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	64 67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?fs:\[esi\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	64 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?fs:\[si\]
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	64 67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?fs:\[esi\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	64 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?fs:\[si\]
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	a5 *	movs(w *| +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	64 67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?fs:?\[esi\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	64 66 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?fs:?\[si\]
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(d *| +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\])
+#pass
--- a/gas/testsuite/gas/i386/intel-movs32.d
+++ b/gas/testsuite/gas/i386/intel-movs32.d
@@ -17,6 +17,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\])
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	64 67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?fs:\[si\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[di\],(BYTE PTR )?(ds:)?\[si\]
 [ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	64 66 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?fs:\[esi\]
@@ -27,6 +36,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\])
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	64 67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?fs:\[si\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[di\],(WORD PTR )?(ds:)?\[si\]
 [ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	64 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?fs:?\[esi\]
@@ -37,4 +55,13 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\])
 [ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\])
+[ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	64 67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?fs:?\[si\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\]
+[ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[di\],(DWORD PTR )?(ds:)?\[si\]
 #pass
--- a/gas/testsuite/gas/i386/intel-movs64.d
+++ b/gas/testsuite/gas/i386/intel-movs64.d
@@ -17,6 +17,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
 [ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
 [ 	]*[a-f0-9]+:	67 a4 *	movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	64 a4 *	movs +BYTE PTR es:\[rdi\],(BYTE PTR )?fs:\[rsi\]
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a4 *	movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
 [ 	]*[a-f0-9]+:	64 67 66 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?fs:\[esi\]
@@ -27,6 +36,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
 [ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
 [ 	]*[a-f0-9]+:	67 66 a5 *	movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	64 66 a5 *	movs +WORD PTR es:\[rdi\],(WORD PTR )?fs:\[rsi\]
+[ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	66 a5 *	movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
 [ 	]*[a-f0-9]+:	64 67 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?fs:\[esi\]
@@ -37,6 +55,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
 [ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
 [ 	]*[a-f0-9]+:	67 a5 *	movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	64 a5 *	movs +DWORD PTR es:\[rdi\],(DWORD PTR )?fs:\[rsi\]
+[ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	a5 *	movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	48 a5 *	movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	48 a5 *	movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	64 48 a5 *	movs +QWORD PTR es:\[rdi\],(QWORD PTR )?fs:?\[rsi\]
@@ -47,4 +74,13 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	48 a5 *	movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	48 a5 *	movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\])
 [ 	]*[a-f0-9]+:	48 a5 *	movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\])
+[ 	]*[a-f0-9]+:	67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	64 67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?fs:?\[esi\]
+[ 	]*[a-f0-9]+:	67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\]
+[ 	]*[a-f0-9]+:	67 48 a5 *	movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\]
 #pass