[11/13] x86: make AnySize an insn attribute

Message ID fdae9251-8bb7-4c7a-4c69-953daf5f46f5@suse.com
State New
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Series
  • x86: further insn template compaction
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Commit Message

Jan Beulich Oct. 30, 2019, 8:28 a.m.
... instead of an operand one. Which operand it applies to can be
determined from other operand properties, but as it turns out the only
place it is actually used at doesn't even need further qualification.

gas/
2019-10-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (operand_size_match): Adjust anysize use.

opcodes/
2019-10-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (opcode_modifiers): Add AnySize entry.
	(operand_types): Remove AnySize entry.
	* i386-opc.h (AnySize): Move between enums.
	(struct i386_opcode_modifier): Add anysize field.
	(OTUnused): Un-comment.
	(union i386_operand_type): Remove anysize field.
	* i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
	prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
	bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
	AnySize.
	* i386-tbl.h: Re-generate.

Comments

H.J. Lu Oct. 31, 2019, 8:16 p.m. | #1
On Wed, Oct 30, 2019 at 1:28 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> ... instead of an operand one. Which operand it applies to can be

> determined from other operand properties, but as it turns out the only

> place it is actually used at doesn't even need further qualification.

>

> gas/

> 2019-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * config/tc-i386.c (operand_size_match): Adjust anysize use.

>

> opcodes/

> 2019-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-gen.c (opcode_modifiers): Add AnySize entry.

>         (operand_types): Remove AnySize entry.

>         * i386-opc.h (AnySize): Move between enums.

>         (struct i386_opcode_modifier): Add anysize field.

>         (OTUnused): Un-comment.

>         (union i386_operand_type): Remove anysize field.

>         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,

>         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,

>         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move

>         AnySize.

>         * i386-tbl.h: Re-generate.

>


OK.

Thanks.

-- 
H.J.

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2073,7 +2073,7 @@  operand_size_match (const insn_template
     {
       if (i.types[j].bitfield.class != Reg
 	  && i.types[j].bitfield.class != RegSIMD
-	  && t->operand_types[j].bitfield.anysize)
+	  && t->opcode_modifier.anysize)
 	continue;
 
       if (t->operand_types[j].bitfield.class == Reg
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -619,6 +619,7 @@  static bitfield opcode_modifiers[] =
   BITFIELD (CheckRegSize),
   BITFIELD (IgnoreSize),
   BITFIELD (DefaultSize),
+  BITFIELD (Anysize),
   BITFIELD (No_bSuf),
   BITFIELD (No_wSuf),
   BITFIELD (No_lSuf),
@@ -726,7 +727,6 @@  static bitfield operand_types[] =
   BITFIELD (Ymmword),
   BITFIELD (Zmmword),
   BITFIELD (Unspecified),
-  BITFIELD (Anysize),
 #ifdef OTUnused
   BITFIELD (OTUnused),
 #endif
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -421,6 +421,8 @@  enum
   IgnoreSize,
   /* default insn size depends on mode */
   DefaultSize,
+  /* any memory size */
+  Anysize,
   /* b suffix on instruction illegal */
   No_bSuf,
   /* w suffix on instruction illegal */
@@ -649,6 +651,7 @@  typedef struct i386_opcode_modifier
   unsigned int checkregsize:1;
   unsigned int ignoresize:1;
   unsigned int defaultsize:1;
+  unsigned int anysize:1;
   unsigned int no_bsuf:1;
   unsigned int no_wsuf:1;
   unsigned int no_lsuf:1;
@@ -787,8 +790,6 @@  enum
   Zmmword,
   /* Unspecified memory size.  */
   Unspecified,
-  /* Any memory size.  */
-  Anysize,
 
   /* The number of bits in i386_operand_type.  */
   OTNum
@@ -800,9 +801,8 @@  enum
   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 
 /* If you get a compiler error for zero width of the unused field,
-   comment it out.
+   comment it out.  */
 #define OTUnused		OTNum
-*/
 
 typedef union i386_operand_type
 {
@@ -834,7 +834,6 @@  typedef union i386_operand_type
       unsigned int ymmword:1;
       unsigned int zmmword:1;
       unsigned int unspecified:1;
-      unsigned int anysize:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
 #endif
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -187,7 +187,7 @@  out, 1, 0xe6, None, 1, 0, W|No_sSuf|No_q
 out, 1, 0xee, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg }
 
 // Load effective address.
-lea, 2, 0x8d, None, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Anysize|BaseIndex, Reg16|Reg32|Reg64 }
+lea, 2, 0x8d, None, 1, 0, Modrm|Anysize|No_bSuf|No_sSuf|No_ldSuf, { BaseIndex, Reg16|Reg32|Reg64 }
 
 // Load segment registers from memory.
 lds, 2, 0xc5, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
@@ -886,7 +886,7 @@  xadd, 2, 0xfc0, None, 2, Cpu486, W|Check
 cmpxchg, 2, 0xfb0, None, 2, Cpu486, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 invd, 0, 0xf08, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 wbinvd, 0, 0xf09, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-invlpg, 1, 0xf01, 0x7, 2, Cpu486, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
+invlpg, 1, 0xf01, 0x7, 2, Cpu486, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 
 // 586 and late 486 extensions.
 cpuid, 0, 0xfa2, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
@@ -982,7 +982,7 @@  fucompi, 1, 0xdfe8, None, 2, Cpu687, No_
 // Pentium4 extensions.
 
 movnti, 2, 0xfc3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
-clflush, 1, 0xfae, 0x7, 2, CpuClflush, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
+clflush, 1, 0xfae, 0x7, 2, CpuClflush, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 lfence, 0, 0xfaee8, None, 3, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { 0 }
 mfence, 0, 0xfaef0, None, 3, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { 0 }
 // Processors that do not support PAUSE treat this opcode as a NOP instruction.
@@ -1328,10 +1328,10 @@  pmovmskb, 2, 0xfd7, None, 2, CpuSSE|Cpu3
 pmulhuw, 2, 0x66e4, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
 pmulhuw, 2, 0x660fe4, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
 pmulhuw, 2, 0xfe4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
-prefetchnta, 1, 0xf18, 0x0, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Anysize|BaseIndex }
-prefetcht0, 1, 0xf18, 0x1, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Anysize|BaseIndex }
-prefetcht1, 1, 0xf18, 0x2, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Anysize|BaseIndex }
-prefetcht2, 1, 0xf18, 0x3, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Anysize|BaseIndex }
+prefetchnta, 1, 0xf18, 0x0, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { BaseIndex }
+prefetcht0, 1, 0xf18, 0x1, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { BaseIndex }
+prefetcht1, 1, 0xf18, 0x2, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { BaseIndex }
+prefetcht2, 1, 0xf18, 0x3, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { BaseIndex }
 psadbw, 2, 0xff6, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
 psadbw, 2, 0x66f6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
 psadbw, 2, 0x660ff6, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
@@ -2772,8 +2772,8 @@  tzmsk,  2, 0x01,   0x4, 1, CpuTBM, Modrm
 
 // AMD 3DNow! instructions.
 
-prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow|CpuPRFCHW, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
-prefetchw, 1, 0xf0d, 0x1, 2, Cpu3dnow|CpuPRFCHW, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
+prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
+prefetchw, 1, 0xf0d, 0x1, 2, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 femms, 0, 0xf0e, None, 2, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 pavgusb, 2, 0xf0f, 0xbf, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
 pf2id, 2, 0xf0f, 0x1d, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
@@ -2873,16 +2873,16 @@  stac, 0, 0xf01cb, None, 3, CpuSMAP, No_b
 bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
 
 // MPX instructions.
-bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex, RegBND }
+bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex, RegBND }
 bndmov, 2, 0x660f1a, None, 2, CpuMPX, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex, RegBND }
-bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex }
-bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|BaseIndex, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|BaseIndex, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|BaseIndex, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|BaseIndex, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|BaseIndex, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|BaseIndex, RegBND }
+bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, BaseIndex }
+bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex, RegBND }
 
 // SHA instructions.
 sha1rnds4, 3, 0xf3acc, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
@@ -4020,13 +4020,13 @@  vscatterpf1qps, 1, 0x66C7, 6, 1, CpuAVX5
 
 // CpuPREFETCHWT1 instructions.
 
-prefetchwt1, 1, 0x0F0D, 2, 2, CpuPREFETCHWT1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
+prefetchwt1, 1, 0x0F0D, 2, 2, CpuPREFETCHWT1, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 
 // CpuPREFETCHWT1 instructions end.
 
 // CLFLUSHOPT instructions.
 
-clflushopt, 1, 0x660fae, 0x7, 2, CpuClflushOpt, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
+clflushopt, 1, 0x660fae, 0x7, 2, CpuClflushOpt, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 
 // CLFLUSHOPT instructions end.
 
@@ -4540,7 +4540,7 @@  vreducess, 5, 0x6657, None, 1, CpuAVX512
 
 // CLWB instructions.
 
-clwb, 1, 0x660fae, 0x6, 2, CpuCLWB, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
+clwb, 1, 0x660fae, 0x6, 2, CpuCLWB, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 
 // CLWB instructions end.
 
@@ -4746,7 +4746,7 @@  umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG,
 
 // CLDEMOTE instructions.
 
-cldemote, 1, 0x0f1c, 0x0, 2, CpuCLDEMOTE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
+cldemote, 1, 0x0f1c, 0x0, 2, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 
 // CLDEMOTE instructions end.