[08/13] x86: introduce operand type "instance"

Message ID f2821957-ee14-32aa-fd5a-9d403625d989@suse.com
State New
Headers show
Series
  • x86: further insn template compaction
Related show

Commit Message

Jan Beulich Oct. 30, 2019, 8:26 a.m.
Special register "class" instances can't be combined with one another
(neither in templates nor in register entries), and hence it is not a
good use of resources (memory as well as execution time) to represent
them as individual bits of a bit field.

Furthermore the generalization becoming possible will allow
improvements to the handling of insns accepting only individual
registers as their operands.

gas/
2019-10-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (operand_type_set, operand_type_and,
	operand_type_and_not, operand_type_or, operand_type_xor): Handle
	"instance" field specially.
	(operand_size_match, md_assemble, match_template, process_suffix,
	check_byte_reg, check_long_reg, check_qword_reg, check_word_reg,
	process_operands, build_modrm_byte): Use "instance" instead of
	"acc" / "inoutportreg" / "shiftcount" fields.
	(optimize_imm): Adjust comment.

opcodes/
2019-10-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (operand_type_init): Adjust
	OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
	OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
	OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
	(operand_instances): New.
	(operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
	(output_operand_type): New parameter "instance". Process it.
	(process_i386_operand_type): New local variable "instance".
	(main): Adjust static assertions.
	* i386-opc.h (INSTANCE_WIDTH): Define.
	(enum operand_instance): New.
	(Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
	(union i386_operand_type): Replace acc, inoutportreg, and
	shiftcount by instance.
	* i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
	* i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
	Add Instance=.
	* i386-init.h, i386-tbl.h: Re-generate.

Comments

H.J. Lu Oct. 31, 2019, 7:28 p.m. | #1
On Wed, Oct 30, 2019 at 1:26 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> Special register "class" instances can't be combined with one another

> (neither in templates nor in register entries), and hence it is not a

> good use of resources (memory as well as execution time) to represent

> them as individual bits of a bit field.

>

> Furthermore the generalization becoming possible will allow

> improvements to the handling of insns accepting only individual

> registers as their operands.

>

> gas/

> 2019-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * config/tc-i386.c (operand_type_set, operand_type_and,

>         operand_type_and_not, operand_type_or, operand_type_xor): Handle

>         "instance" field specially.

>         (operand_size_match, md_assemble, match_template, process_suffix,

>         check_byte_reg, check_long_reg, check_qword_reg, check_word_reg,

>         process_operands, build_modrm_byte): Use "instance" instead of

>         "acc" / "inoutportreg" / "shiftcount" fields.

>         (optimize_imm): Adjust comment.

>

> opcodes/

> 2019-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-gen.c (operand_type_init): Adjust

>         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,

>         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,

>         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.

>         (operand_instances): New.

>         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.

>         (output_operand_type): New parameter "instance". Process it.

>         (process_i386_operand_type): New local variable "instance".

>         (main): Adjust static assertions.

>         * i386-opc.h (INSTANCE_WIDTH): Define.

>         (enum operand_instance): New.

>         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.

>         (union i386_operand_type): Replace acc, inoutportreg, and

>         shiftcount by instance.

>         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.

>         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):

>         Add Instance=.

>         * i386-init.h, i386-tbl.h: Re-generate.

>


OK.

Thanks.

-- 
H.J.

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1609,6 +1609,7 @@  operand_type_set (union i386_operand_typ
     }
 
   x->bitfield.class = ClassNone;
+  x->bitfield.instance = InstanceNone;
 }
 
 static INLINE int
@@ -1827,6 +1828,8 @@  operand_type_and (i386_operand_type x, i
 {
   if (x.bitfield.class != y.bitfield.class)
     x.bitfield.class = ClassNone;
+  if (x.bitfield.instance != y.bitfield.instance)
+    x.bitfield.instance = InstanceNone;
 
   switch (ARRAY_SIZE (x.array))
     {
@@ -1849,6 +1852,7 @@  static INLINE i386_operand_type
 operand_type_and_not (i386_operand_type x, i386_operand_type y)
 {
   gas_assert (y.bitfield.class == ClassNone);
+  gas_assert (y.bitfield.instance == InstanceNone);
 
   switch (ARRAY_SIZE (x.array))
     {
@@ -1873,6 +1877,9 @@  operand_type_or (i386_operand_type x, i3
   gas_assert (x.bitfield.class == ClassNone ||
               y.bitfield.class == ClassNone ||
               x.bitfield.class == y.bitfield.class);
+  gas_assert (x.bitfield.instance == InstanceNone ||
+              y.bitfield.instance == InstanceNone ||
+              x.bitfield.instance == y.bitfield.instance);
 
   switch (ARRAY_SIZE (x.array))
     {
@@ -1895,6 +1902,7 @@  static INLINE i386_operand_type
 operand_type_xor (i386_operand_type x, i386_operand_type y)
 {
   gas_assert (y.bitfield.class == ClassNone);
+  gas_assert (y.bitfield.instance == InstanceNone);
 
   switch (ARRAY_SIZE (x.array))
     {
@@ -2082,7 +2090,7 @@  operand_size_match (const insn_template
 	  break;
 	}
 
-      if (t->operand_types[j].bitfield.acc
+      if (t->operand_types[j].bitfield.instance == Accum
 	  && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
 	{
 	  match = 0;
@@ -2119,7 +2127,7 @@  mismatch:
 	  && !match_simd_size (t, j, given))
 	goto mismatch;
 
-      if (t->operand_types[j].bitfield.acc
+      if (t->operand_types[j].bitfield.instance == Accum
 	  && (!match_operand_size (t, j, given)
 	      || !match_simd_size (t, j, given)))
 	goto mismatch;
@@ -4437,9 +4445,8 @@  md_assemble (char *line)
      with 3 operands or less.  */
   if (i.operands <= 3)
     for (j = 0; j < i.operands; j++)
-      if (i.types[j].bitfield.inoutportreg
-	  || i.types[j].bitfield.shiftcount
-	  || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
+      if (i.types[j].bitfield.instance != InstanceNone
+	  && !i.types[j].bitfield.xmmword)
 	i.reg_operands--;
 
   /* ImmExt should be processed after SSE2AVX.  */
@@ -5060,9 +5067,9 @@  optimize_imm (void)
   else if (i.reg_operands)
     {
       /* Figure out a suffix from the last register operand specified.
-	 We can't do this properly yet, ie. excluding InOutPortReg,
-	 but the following works for instructions with immediates.
-	 In any case, we can't set i.suffix yet.  */
+	 We can't do this properly yet, i.e. excluding special register
+	 instances, but the following works for instructions with
+	 immediates.  In any case, we can't set i.suffix yet.  */
       for (op = i.operands; --op >= 0;)
 	if (i.types[op].bitfield.class != Reg)
 	  continue;
@@ -5889,15 +5896,17 @@  match_template (char mnem_suffix)
 	     zero-extend %eax to %rax.  */
 	  if (flag_code == CODE_64BIT
 	      && t->base_opcode == 0x90
-	      && i.types[0].bitfield.acc && i.types[0].bitfield.dword
-	      && i.types[1].bitfield.acc && i.types[1].bitfield.dword)
+	      && i.types[0].bitfield.instance == Accum
+	      && i.types[0].bitfield.dword
+	      && i.types[1].bitfield.instance == Accum
+	      && i.types[1].bitfield.dword)
 	    continue;
 	  /* xrelease mov %eax, <disp> is another special case. It must not
 	     match the accumulator-only encoding of mov.  */
 	  if (flag_code != CODE_64BIT
 	      && i.hle_prefix
 	      && t->base_opcode == 0xa0
-	      && i.types[0].bitfield.acc
+	      && i.types[0].bitfield.instance == Accum
 	      && (i.flags[1] & Operand_Mem))
 	    continue;
 	  /* Fall through.  */
@@ -6277,8 +6286,8 @@  process_suffix (void)
 	  unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1;
 
 	  while (op--)
-	    if (!i.tm.operand_types[op].bitfield.inoutportreg
-		&& !i.tm.operand_types[op].bitfield.shiftcount)
+	    if (i.tm.operand_types[op].bitfield.instance == InstanceNone
+		|| i.tm.operand_types[op].bitfield.instance == Accum)
 	      {
 		if (i.types[op].bitfield.class != Reg)
 		  continue;
@@ -6598,8 +6607,10 @@  process_suffix (void)
 	  && ! (i.operands == 2
 		&& i.tm.base_opcode == 0x90
 		&& i.tm.extension_opcode == None
-		&& i.types[0].bitfield.acc && i.types[0].bitfield.qword
-		&& i.types[1].bitfield.acc && i.types[1].bitfield.qword))
+		&& i.types[0].bitfield.instance == Accum
+		&& i.types[0].bitfield.qword
+		&& i.types[1].bitfield.instance == Accum
+		&& i.types[1].bitfield.qword))
 	i.rex |= REX_W;
 
       break;
@@ -6661,7 +6672,8 @@  check_byte_reg (void)
 	continue;
 
       /* I/O port address operands are OK too.  */
-      if (i.tm.operand_types[op].bitfield.inoutportreg)
+      if (i.tm.operand_types[op].bitfield.instance == RegD
+	  && i.tm.operand_types[op].bitfield.word)
 	continue;
 
       /* crc32 doesn't generate this warning.  */
@@ -6722,7 +6734,7 @@  check_long_reg (void)
        them. (eg. movzb)  */
     else if (i.types[op].bitfield.byte
 	     && (i.tm.operand_types[op].bitfield.class == Reg
-		 || i.tm.operand_types[op].bitfield.acc)
+		 || i.tm.operand_types[op].bitfield.instance == Accum)
 	     && (i.tm.operand_types[op].bitfield.word
 		 || i.tm.operand_types[op].bitfield.dword))
       {
@@ -6737,7 +6749,7 @@  check_long_reg (void)
     else if ((!quiet_warnings || flag_code == CODE_64BIT)
 	     && i.types[op].bitfield.word
 	     && (i.tm.operand_types[op].bitfield.class == Reg
-		 || i.tm.operand_types[op].bitfield.acc)
+		 || i.tm.operand_types[op].bitfield.instance == Accum)
 	     && i.tm.operand_types[op].bitfield.dword)
       {
 	/* Prohibit these changes in the 64bit mode, since the
@@ -6759,7 +6771,7 @@  check_long_reg (void)
     /* Warn if the r prefix on a general reg is present.  */
     else if (i.types[op].bitfield.qword
 	     && (i.tm.operand_types[op].bitfield.class == Reg
-		 || i.tm.operand_types[op].bitfield.acc)
+		 || i.tm.operand_types[op].bitfield.instance == Accum)
 	     && i.tm.operand_types[op].bitfield.dword)
       {
 	if (intel_syntax
@@ -6793,7 +6805,7 @@  check_qword_reg (void)
        them. (eg. movzb)  */
     else if (i.types[op].bitfield.byte
 	     && (i.tm.operand_types[op].bitfield.class == Reg
-		 || i.tm.operand_types[op].bitfield.acc)
+		 || i.tm.operand_types[op].bitfield.instance == Accum)
 	     && (i.tm.operand_types[op].bitfield.word
 		 || i.tm.operand_types[op].bitfield.dword))
       {
@@ -6808,7 +6820,7 @@  check_qword_reg (void)
     else if ((i.types[op].bitfield.word
 	      || i.types[op].bitfield.dword)
 	     && (i.tm.operand_types[op].bitfield.class == Reg
-		 || i.tm.operand_types[op].bitfield.acc)
+		 || i.tm.operand_types[op].bitfield.instance == Accum)
 	     && i.tm.operand_types[op].bitfield.qword)
       {
 	/* Prohibit these changes in the 64bit mode, since the
@@ -6843,7 +6855,7 @@  check_word_reg (void)
        them. (eg. movzb)  */
     else if (i.types[op].bitfield.byte
 	     && (i.tm.operand_types[op].bitfield.class == Reg
-		 || i.tm.operand_types[op].bitfield.acc)
+		 || i.tm.operand_types[op].bitfield.instance == Accum)
 	     && (i.tm.operand_types[op].bitfield.word
 		 || i.tm.operand_types[op].bitfield.dword))
       {
@@ -6859,7 +6871,7 @@  check_word_reg (void)
 	     && (i.types[op].bitfield.dword
 		 || i.types[op].bitfield.qword)
 	     && (i.tm.operand_types[op].bitfield.class == Reg
-		 || i.tm.operand_types[op].bitfield.acc)
+		 || i.tm.operand_types[op].bitfield.instance == Accum)
 	     && i.tm.operand_types[op].bitfield.word)
       {
 	/* Prohibit these changes in the 64bit mode, since the
@@ -6984,14 +6996,14 @@  process_operands (void)
 		  && MAX_OPERANDS > dupl
 		  && operand_type_equal (&i.types[dest], &regxmm));
 
-      if (i.tm.operand_types[0].bitfield.acc
+      if (i.tm.operand_types[0].bitfield.instance == Accum
 	  && i.tm.operand_types[0].bitfield.xmmword)
 	{
 	  if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
 	    {
 	      /* Keep xmm0 for instructions with VEX prefix and 3
 		 sources.  */
-	      i.tm.operand_types[0].bitfield.acc = 0;
+	      i.tm.operand_types[0].bitfield.instance = InstanceNone;
 	      i.tm.operand_types[0].bitfield.class = RegSIMD;
 	      goto duplicate;
 	    }
@@ -7056,7 +7068,7 @@  duplicate:
        if (i.tm.opcode_modifier.immext)
 	 process_immext ();
     }
-  else if (i.tm.operand_types[0].bitfield.acc
+  else if (i.tm.operand_types[0].bitfield.instance == Accum
 	   && i.tm.operand_types[0].bitfield.xmmword)
     {
       unsigned int j;
@@ -7303,9 +7315,11 @@  build_modrm_byte (void)
 	  gas_assert (i.imm_operands == 1
 		      || (i.imm_operands == 0
 			  && (i.tm.opcode_modifier.vexvvvv == VEXXDS
-			      || i.types[0].bitfield.shiftcount)));
+			      || (i.types[0].bitfield.instance == RegC
+				  && i.types[0].bitfield.byte))));
 	  if (operand_type_check (i.types[0], imm)
-	      || i.types[0].bitfield.shiftcount)
+	      || (i.types[0].bitfield.instance == RegC
+		  && i.types[0].bitfield.byte))
 	    source = 1;
 	  else
 	    source = 0;
@@ -10416,7 +10430,8 @@  i386_att_operand (char *operand_string)
 
       /* Special case for (%dx) while doing input/output op.  */
       if (i.base_reg
-	  && i.base_reg->reg_type.bitfield.inoutportreg
+	  && i.base_reg->reg_type.bitfield.instance == RegD
+	  && i.base_reg->reg_type.bitfield.word
 	  && i.index_reg == 0
 	  && i.log2_scale_factor == 0
 	  && i.seg[i.mem_operands] == 0
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -418,9 +418,9 @@  static initializer operand_type_init[] =
   { "OPERAND_TYPE_DISP64",
     "Disp64" },
   { "OPERAND_TYPE_INOUTPORTREG",
-    "InOutPortReg" },
+    "Instance=RegD|Word" },
   { "OPERAND_TYPE_SHIFTCOUNT",
-    "ShiftCount" },
+    "Instance=RegC|Byte" },
   { "OPERAND_TYPE_CONTROL",
     "Class=RegCR" },
   { "OPERAND_TYPE_TEST",
@@ -430,7 +430,7 @@  static initializer operand_type_init[] =
   { "OPERAND_TYPE_FLOATREG",
     "Class=Reg|Tbyte" },
   { "OPERAND_TYPE_FLOATACC",
-    "Acc|Tbyte" },
+    "Instance=Accum|Tbyte" },
   { "OPERAND_TYPE_SREG",
     "Class=SReg" },
   { "OPERAND_TYPE_JUMPABSOLUTE",
@@ -450,13 +450,13 @@  static initializer operand_type_init[] =
   { "OPERAND_TYPE_ESSEG",
     "EsSeg" },
   { "OPERAND_TYPE_ACC8",
-    "Acc|Byte" },
+    "Instance=Accum|Byte" },
   { "OPERAND_TYPE_ACC16",
-    "Acc|Word" },
+    "Instance=Accum|Word" },
   { "OPERAND_TYPE_ACC32",
-    "Acc|Dword" },
+    "Instance=Accum|Dword" },
   { "OPERAND_TYPE_ACC64",
-    "Acc|Qword" },
+    "Instance=Accum|Qword" },
   { "OPERAND_TYPE_DISP16_32",
     "Disp16|Disp32" },
   { "OPERAND_TYPE_ANYDISP",
@@ -688,6 +688,19 @@  static const struct {
 
 #undef CLASS
 
+#define INSTANCE(n) #n, n
+
+static const struct {
+  const char *name;
+  enum operand_instance value;
+} operand_instances[] = {
+    INSTANCE (Accum),
+    INSTANCE (RegC),
+    INSTANCE (RegD),
+};
+
+#undef INSTANCE
+
 static bitfield operand_types[] =
 {
   BITFIELD (Imm1),
@@ -703,9 +716,6 @@  static bitfield operand_types[] =
   BITFIELD (Disp32),
   BITFIELD (Disp32S),
   BITFIELD (Disp64),
-  BITFIELD (InOutPortReg),
-  BITFIELD (ShiftCount),
-  BITFIELD (Acc),
   BITFIELD (JumpAbsolute),
   BITFIELD (EsSeg),
   BITFIELD (Byte),
@@ -1140,20 +1150,21 @@  enum stage {
 
 static void
 output_operand_type (FILE *table, enum operand_class class,
+		     enum operand_instance instance,
 		     const bitfield *types, unsigned int size,
 		     enum stage stage, const char *indent)
 {
   unsigned int i;
 
-  fprintf (table, "{ { %d, ", class);
+  fprintf (table, "{ { %d, %d, ", class, instance);
 
   for (i = 0; i < size - 1; i++)
     {
-      if (((i + 2) % 20) != 0)
+      if (((i + 3) % 20) != 0)
 	fprintf (table, "%d, ", types[i].value);
       else
 	fprintf (table, "%d,", types[i].value);
-      if (((i + 2) % 20) == 0)
+      if (((i + 3) % 20) == 0)
 	{
 	  /* We need \\ for macro.  */
 	  if (stage == stage_macros)
@@ -1172,6 +1183,7 @@  process_i386_operand_type (FILE *table,
 {
   char *str, *next, *last;
   enum operand_class class = ClassNone;
+  enum operand_instance instance = InstanceNone;
   bitfield types [ARRAY_SIZE (operand_types)];
 
   /* Copy the default operand type.  */
@@ -1199,6 +1211,17 @@  process_i386_operand_type (FILE *table,
 			break;
 		      }
 		}
+
+	      if (str && !strncmp(str, "Instance=", 9))
+		{
+		  for (i = 0; i < ARRAY_SIZE(operand_instances); ++i)
+		    if (!strcmp(str + 9, operand_instances[i].name))
+		      {
+			instance = operand_instances[i].value;
+			str = NULL;
+			break;
+		      }
+		}
 	    }
 	  if (str)
 	    {
@@ -1219,8 +1242,8 @@  process_i386_operand_type (FILE *table,
 	    set_bitfield("Disp32S", types, 1, ARRAY_SIZE (types), lineno);
 	}
     }
-  output_operand_type (table, class, types, ARRAY_SIZE (types), stage,
-		       indent);
+  output_operand_type (table, class, instance, types, ARRAY_SIZE (types),
+		       stage, indent);
 }
 
 static void
@@ -1710,9 +1733,11 @@  main (int argc, char **argv)
 
   /* Check the unused bitfield in i386_operand_type.  */
 #ifdef OTUnused
-  static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH == OTNum + 1);
+  static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH + INSTANCE_WIDTH
+		 == OTNum + 1);
 #else
-  static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH == OTNum);
+  static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH + INSTANCE_WIDTH
+		 == OTNum);
 
   c = OTNumOfBits - OTMax - 1;
   if (c)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -710,12 +710,23 @@  enum operand_class
   RegBND, /* Bound register */
 };
 
+/* Special operand instances.  */
+
+#define INSTANCE_WIDTH 3
+enum operand_instance
+{
+  InstanceNone,
+  Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
+  RegC,  /* Register to hold shift count = %cl */
+  RegD,  /* Register to hold in/out port addr = %dx */
+};
+
 /* Position of operand_type bits.  */
 
 enum
 {
-  /* Class */
-  Class = CLASS_WIDTH - 1,
+  /* Class and Instance */
+  ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
   /* 1 bit immediate */
   Imm1,
   /* 8 bit immediate */
@@ -747,14 +758,8 @@  enum
   Disp32S,
   /* 64 bit displacement */
   Disp64,
-  /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
-  Acc,
   /* Register which can be used for base or index in memory operand.  */
   BaseIndex,
-  /* Register to hold in/out port addr = dx */
-  InOutPortReg,
-  /* Register to hold shift count = cl */
-  ShiftCount,
   /* Absolute address for jump.  */
   JumpAbsolute,
   /* String insn operand with fixed es segment */
@@ -800,6 +805,7 @@  typedef union i386_operand_type
   struct
     {
       unsigned int class:CLASS_WIDTH;
+      unsigned int instance:INSTANCE_WIDTH;
       unsigned int imm1:1;
       unsigned int imm8:1;
       unsigned int imm8s:1;
@@ -812,10 +818,7 @@  typedef union i386_operand_type
       unsigned int disp32:1;
       unsigned int disp32s:1;
       unsigned int disp64:1;
-      unsigned int acc:1;
       unsigned int baseindex:1;
-      unsigned int inoutportreg:1;
-      unsigned int shiftcount:1;
       unsigned int jumpabsolute:1;
       unsigned int esseg:1;
       unsigned int byte:1;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -27,6 +27,10 @@ 
 #define Reg32 Class=Reg|Dword
 #define Reg64 Class=Reg|Qword
 
+#define Acc          Instance=Accum
+#define ShiftCount   Instance=RegC|Byte
+#define InOutPortReg Instance=RegD|Word
+
 #define FloatAcc Acc|Tbyte
 #define FloatReg Class=Reg|Tbyte
 
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -19,10 +19,10 @@ 
 // 02110-1301, USA.
 
 // Make %st first as we test for it.
-st, Class=Reg|Acc|Tbyte, 0, 0, 11, 33
+st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
 // 8 bit regs
-al, Class=Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
-cl, Class=Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
+al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
+cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
 ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
@@ -46,9 +46,9 @@  r13b, Class=Reg|Byte, RegRex|RegRex64, 5
 r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
 r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
 // 16 bit regs
-ax, Class=Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
+ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
 cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
-dx, Class=Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
+dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
 bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
 sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
 bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
@@ -63,7 +63,7 @@  r13w, Class=Reg|Word, RegRex, 5, Dw2Inva
 r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
 r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
 // 32 bit regs
-eax, Class=Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval
+eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
 ecx, Class=Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval
 edx, Class=Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval
 ebx, Class=Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval
@@ -79,7 +79,7 @@  r12d, Class=Reg|Dword|BaseIndex, RegRex,
 r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
 r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
 r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
-rax, Class=Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0
+rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
 rcx, Class=Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2
 rdx, Class=Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1
 rbx, Class=Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3
@@ -180,7 +180,7 @@  mm4, Class=RegMMX, 0, 4, 33, 45
 mm5, Class=RegMMX, 0, 5, 34, 46
 mm6, Class=RegMMX, 0, 6, 35, 47
 mm7, Class=RegMMX, 0, 7, 36, 48
-xmm0, Class=RegSIMD|Acc|Xmmword, 0, 0, 21, 17
+xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
 xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
 xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
 xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
@@ -292,7 +292,7 @@  eip, Dword, RegRex64, RegIP, 8, Dw2Inval
 riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
 eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
 // fp regs.
-st(0), Class=Reg|Acc|Tbyte, 0, 0, 11, 33
+st(0), Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
 st(1), Class=Reg|Tbyte, 0, 1, 12, 34
 st(2), Class=Reg|Tbyte, 0, 2, 13, 35
 st(3), Class=Reg|Tbyte, 0, 3, 14, 36