[07/13] x86: convert RegMask and RegBND from bitfield to enumerator

Message ID fef89b3b-5a51-37a0-bb8a-162fe0a19517@suse.com
State New
Headers show
Series
  • x86: further insn template compaction
Related show

Commit Message

Jan Beulich Oct. 30, 2019, 8:26 a.m.
This is to further shrink the operand type representation.

gas/
2019-10-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (optimize_encoding, build_modrm_byte,
	check_VecOperations, parse_real_register): Use "class" instead
	of "regmask" and "regbnd" fields.

opcodes/
2019-10-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (operand_type_init): Add Class= to
	OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
	OPERAND_TYPE_REGBND entry.
	(operand_classes): Add RegMask and RegBND entries.
	(operand_types): Drop RegMask and RegBND entry.
	* i386-opc.h (enum operand_class): Add RegMask and RegBND.
	(RegMask, RegBND): Delete.
	(union i386_operand_type): Remove regmask and regbnd fields.
	* i386-opc.tbl (RegMask, RegBND): Define.
	* i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
	Class=RegBND.
	* i386-init.h, i386-tbl.h: Re-generate.

Comments

H.J. Lu Oct. 31, 2019, 7:27 p.m. | #1
On Wed, Oct 30, 2019 at 1:26 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> This is to further shrink the operand type representation.

>

> gas/

> 2019-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * config/tc-i386.c (optimize_encoding, build_modrm_byte,

>         check_VecOperations, parse_real_register): Use "class" instead

>         of "regmask" and "regbnd" fields.

>

> opcodes/

> 2019-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-gen.c (operand_type_init): Add Class= to

>         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up

>         OPERAND_TYPE_REGBND entry.

>         (operand_classes): Add RegMask and RegBND entries.

>         (operand_types): Drop RegMask and RegBND entry.

>         * i386-opc.h (enum operand_class): Add RegMask and RegBND.

>         (RegMask, RegBND): Delete.

>         (union i386_operand_type): Remove regmask and regbnd fields.

>         * i386-opc.tbl (RegMask, RegBND): Define.

>         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by

>         Class=RegBND.

>         * i386-init.h, i386-tbl.h: Re-generate.

>


OK.

Thanks.

-- 
H.J.

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4154,7 +4154,7 @@  optimize_encoding (void)
 	  else
 	    return;
 	}
-      else if (i.tm.operand_types[0].bitfield.regmask)
+      else if (i.tm.operand_types[0].bitfield.class == RegMask)
 	{
 	  i.tm.base_opcode &= 0xff;
 	  i.tm.opcode_modifier.vexw = VEXW0;
@@ -7769,8 +7769,8 @@  build_modrm_byte (void)
 	  for (op = 0; op < i.operands; op++)
 	    {
 	      if (i.types[op].bitfield.class == Reg
-		  || i.types[op].bitfield.regbnd
-		  || i.types[op].bitfield.regmask
+		  || i.types[op].bitfield.class == RegBND
+		  || i.types[op].bitfield.class == RegMask
 		  || i.types[op].bitfield.class == SReg
 		  || i.types[op].bitfield.class == RegCR
 		  || i.types[op].bitfield.class == RegDR
@@ -9325,7 +9325,7 @@  check_VecOperations (char *op_string, ch
 	  else if ((mask = parse_register (op_string, &end_op)) != NULL)
 	    {
 	      /* k0 can't be used for write mask.  */
-	      if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
+	      if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
 		{
 		  as_bad (_("`%s%s' can't be used for write mask"),
 			  register_prefix, mask->reg_name);
@@ -11022,7 +11022,8 @@  parse_real_register (char *reg_string, c
 
   if (!cpu_arch_flags.bitfield.cpuavx512f)
     {
-      if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
+      if (r->reg_type.bitfield.zmmword
+	  || r->reg_type.bitfield.class == RegMask)
 	return (const reg_entry *) NULL;
 
       if (!cpu_arch_flags.bitfield.cpuavx)
@@ -11035,7 +11036,7 @@  parse_real_register (char *reg_string, c
 	}
     }
 
-  if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
+  if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
     return (const reg_entry *) NULL;
 
   /* Don't allow fake index register unless allow_index_reg isn't 0. */
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -444,7 +444,9 @@  static initializer operand_type_init[] =
   { "OPERAND_TYPE_REGZMM",
     "Class=RegSIMD|Zmmword" },
   { "OPERAND_TYPE_REGMASK",
-    "RegMask" },
+    "Class=RegMask" },
+  { "OPERAND_TYPE_REGBND",
+    "Class=RegBND" },
   { "OPERAND_TYPE_ESSEG",
     "EsSeg" },
   { "OPERAND_TYPE_ACC8",
@@ -477,8 +479,6 @@  static initializer operand_type_init[] =
     "Imm32|Imm32S|Imm64|Disp32|Disp64" },
   { "OPERAND_TYPE_ANYIMM",
     "Imm1|Imm8|Imm8S|Imm16|Imm32|Imm32S|Imm64" },
-  { "OPERAND_TYPE_REGBND",
-    "RegBND" },
 };
 
 typedef struct bitfield
@@ -682,13 +682,14 @@  static const struct {
   CLASS (RegTR),
   CLASS (RegMMX),
   CLASS (RegSIMD),
+  CLASS (RegMask),
+  CLASS (RegBND),
 };
 
 #undef CLASS
 
 static bitfield operand_types[] =
 {
-  BITFIELD (RegMask),
   BITFIELD (Imm1),
   BITFIELD (Imm8),
   BITFIELD (Imm8S),
@@ -718,7 +719,6 @@  static bitfield operand_types[] =
   BITFIELD (Zmmword),
   BITFIELD (Unspecified),
   BITFIELD (Anysize),
-  BITFIELD (RegBND),
 #ifdef OTUnused
   BITFIELD (OTUnused),
 #endif
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -706,6 +706,8 @@  enum operand_class
   RegTR, /* Test register */
   RegMMX, /* MMX register */
   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
+  RegMask, /* Vector Mask register */
+  RegBND, /* Bound register */
 };
 
 /* Position of operand_type bits.  */
@@ -714,8 +716,6 @@  enum
 {
   /* Class */
   Class = CLASS_WIDTH - 1,
-  /* Vector Mask registers */
-  RegMask,
   /* 1 bit immediate */
   Imm1,
   /* 8 bit immediate */
@@ -782,9 +782,6 @@  enum
   /* Any memory size.  */
   Anysize,
 
-  /* Bound register.  */
-  RegBND,
-
   /* The number of bits in i386_operand_type.  */
   OTNum
 };
@@ -803,7 +800,6 @@  typedef union i386_operand_type
   struct
     {
       unsigned int class:CLASS_WIDTH;
-      unsigned int regmask:1;
       unsigned int imm1:1;
       unsigned int imm8:1;
       unsigned int imm8s:1;
@@ -833,7 +829,6 @@  typedef union i386_operand_type
       unsigned int zmmword:1;
       unsigned int unspecified:1;
       unsigned int anysize:1;
-      unsigned int regbnd:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
 #endif
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -41,6 +41,10 @@ 
 #define RegYMM Class=RegSIMD|Ymmword
 #define RegZMM Class=RegSIMD|Zmmword
 
+#define RegMask Class=RegMask
+
+#define RegBND Class=RegBND
+
 #define Size16 Size=SIZE16
 #define Size32 Size=SIZE32
 #define Size64 Size=SIZE64
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -96,14 +96,14 @@  r13, Class=Reg|Qword|BaseIndex, RegRex,
 r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
 r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
 // Vector mask registers.
-k0, RegMask, 0, 0, 93, 118
-k1, RegMask, 0, 1, 94, 119
-k2, RegMask, 0, 2, 95, 120
-k3, RegMask, 0, 3, 96, 121
-k4, RegMask, 0, 4, 97, 122
-k5, RegMask, 0, 5, 98, 123
-k6, RegMask, 0, 6, 99, 124
-k7, RegMask, 0, 7, 100, 125
+k0, Class=RegMask, 0, 0, 93, 118
+k1, Class=RegMask, 0, 1, 94, 119
+k2, Class=RegMask, 0, 2, 95, 120
+k3, Class=RegMask, 0, 3, 96, 121
+k4, Class=RegMask, 0, 4, 97, 122
+k5, Class=RegMask, 0, 5, 98, 123
+k6, Class=RegMask, 0, 6, 99, 124
+k7, Class=RegMask, 0, 7, 100, 125
 // Segment registers.
 es, Class=SReg, 0, 0, 40, 50
 cs, Class=SReg, 0, 1, 41, 51
@@ -279,10 +279,10 @@  zmm29, Class=RegSIMD|Zmmword, RegVRex|Re
 zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
 zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
 // Bound registers for MPX
-bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
-bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
-bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
-bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
+bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
+bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
+bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
+bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
 // No Class=Reg will make these registers rejected for all purposes except
 // for addressing.  This saves creating one extra type for RIP/EIP.
 rip, Qword, RegRex64, RegIP, Dw2Inval, 16