[04/13] x86: convert SReg from bitfield to enumerator

Message ID 6fdb1588-de75-83f3-2e4f-8c4dc388603d@suse.com
State New
Headers show
Series
  • x86: further insn template compaction
Related show

Commit Message

Jan Beulich Oct. 30, 2019, 8:24 a.m.
This is to further shrink the operand type representation.

gas/
2019-10-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (pi, check_byte_reg, process_operands,
	build_modrm_byte, i386_att_operand, parse_real_register): Use
	"class" instead of "sreg" field.
	* config/tc-i386-intel.c (i386_intel_simplify_register,
	i386_intel_operand): Likewise.

opcodes/
2019-10-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (operand_type_init): Add Class= to
	OPERAND_TYPE_SREG entry.
	(operand_classes): Add SReg entry.
	(operand_types): Drop SReg entry.
	* i386-opc.h (enum operand_class): Add SReg.
	(SReg): Delete.
	(union i386_operand_type): Remove sreg field.
	* i386-opc.tbl (SReg): Define.
	* i386-reg.tbl: Replace SReg by Class=SReg.
	* i386-init.h, i386-tbl.h: Re-generate.

Comments

H.J. Lu Oct. 31, 2019, 7:25 p.m. | #1
On Wed, Oct 30, 2019 at 1:24 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> This is to further shrink the operand type representation.

>

> gas/

> 2019-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * config/tc-i386.c (pi, check_byte_reg, process_operands,

>         build_modrm_byte, i386_att_operand, parse_real_register): Use

>         "class" instead of "sreg" field.

>         * config/tc-i386-intel.c (i386_intel_simplify_register,

>         i386_intel_operand): Likewise.

>

> opcodes/

> 2019-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-gen.c (operand_type_init): Add Class= to

>         OPERAND_TYPE_SREG entry.

>         (operand_classes): Add SReg entry.

>         (operand_types): Drop SReg entry.

>         * i386-opc.h (enum operand_class): Add SReg.

>         (SReg): Delete.

>         (union i386_operand_type): Remove sreg field.

>         * i386-opc.tbl (SReg): Define.

>         * i386-reg.tbl: Replace SReg by Class=SReg.

>         * i386-init.h, i386-tbl.h: Re-generate.

>


OK.

Thanks.

-- 
H.J.

Patch

--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -283,7 +283,7 @@  i386_intel_simplify_register (expression
 	  as_bad (_("invalid use of register"));
 	  return 0;
 	}
-      if (i386_regtab[reg_num].reg_type.bitfield.sreg
+      if (i386_regtab[reg_num].reg_type.bitfield.class == SReg
 	  && i386_regtab[reg_num].reg_num == RegFlat)
 	{
 	  as_bad (_("invalid use of pseudo-register"));
@@ -984,7 +984,7 @@  i386_intel_operand (char *operand_string
 	      as_bad (_("segment register name expected"));
 	      return 0;
 	    }
-	  if (!i386_regtab[expP->X_add_number].reg_type.bitfield.sreg)
+	  if (i386_regtab[expP->X_add_number].reg_type.bitfield.class != SReg)
 	    {
 	      as_bad (_("invalid use of register"));
 	      return 0;
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3047,7 +3047,7 @@  pi (const char *line, i386_insn *x)
       if (x->types[j].bitfield.class == Reg
 	  || x->types[j].bitfield.regmmx
 	  || x->types[j].bitfield.regsimd
-	  || x->types[j].bitfield.sreg
+	  || x->types[j].bitfield.class == SReg
 	  || x->types[j].bitfield.control
 	  || x->types[j].bitfield.debug
 	  || x->types[j].bitfield.test)
@@ -6691,7 +6691,7 @@  check_byte_reg (void)
       if (i.types[op].bitfield.class == Reg
 	  || i.types[op].bitfield.regmmx
 	  || i.types[op].bitfield.regsimd
-	  || i.types[op].bitfield.sreg
+	  || i.types[op].bitfield.class == SReg
 	  || i.types[op].bitfield.control
 	  || i.types[op].bitfield.debug
 	  || i.types[op].bitfield.test)
@@ -7121,7 +7121,7 @@  duplicate:
 
       default_seg = build_modrm_byte ();
     }
-  else if (i.types[0].bitfield.sreg)
+  else if (i.types[0].bitfield.class == SReg)
     {
       if (flag_code != CODE_64BIT
 	  ? i.tm.base_opcode == POP_SEG_SHORT
@@ -7769,7 +7769,7 @@  build_modrm_byte (void)
 	      if (i.types[op].bitfield.class == Reg
 		  || i.types[op].bitfield.regbnd
 		  || i.types[op].bitfield.regmask
-		  || i.types[op].bitfield.sreg
+		  || i.types[op].bitfield.class == SReg
 		  || i.types[op].bitfield.control
 		  || i.types[op].bitfield.debug
 		  || i.types[op].bitfield.test)
@@ -10145,7 +10145,7 @@  i386_att_operand (char *operand_string)
       op_string = end_op;
       if (is_space_char (*op_string))
 	++op_string;
-      if (*op_string == ':' && r->reg_type.bitfield.sreg)
+      if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
 	{
 	  switch (r->reg_num)
 	    {
@@ -11008,7 +11008,7 @@  parse_real_register (char *reg_string, c
     return (const reg_entry *) NULL;
 
   if ((r->reg_type.bitfield.dword
-       || (r->reg_type.bitfield.sreg && r->reg_num > 3)
+       || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
        || r->reg_type.bitfield.control
        || r->reg_type.bitfield.debug
        || r->reg_type.bitfield.test)
@@ -11056,7 +11056,8 @@  parse_real_register (char *reg_string, c
       && flag_code != CODE_64BIT)
     return (const reg_entry *) NULL;
 
-  if (r->reg_type.bitfield.sreg && r->reg_num == RegFlat && !intel_syntax)
+  if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
+      && !intel_syntax)
     return (const reg_entry *) NULL;
 
   return r;
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -432,7 +432,7 @@  static initializer operand_type_init[] =
   { "OPERAND_TYPE_FLOATACC",
     "Acc|Tbyte" },
   { "OPERAND_TYPE_SREG",
-    "SReg" },
+    "Class=SReg" },
   { "OPERAND_TYPE_JUMPABSOLUTE",
     "JumpAbsolute" },
   { "OPERAND_TYPE_REGMMX",
@@ -676,6 +676,7 @@  static const struct {
   enum operand_class value;
 } operand_classes[] = {
   CLASS (Reg),
+  CLASS (SReg),
 };
 
 #undef CLASS
@@ -703,7 +704,6 @@  static bitfield operand_types[] =
   BITFIELD (Control),
   BITFIELD (Debug),
   BITFIELD (Test),
-  BITFIELD (SReg),
   BITFIELD (Acc),
   BITFIELD (JumpAbsolute),
   BITFIELD (EsSeg),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -700,6 +700,7 @@  enum operand_class
 {
   ClassNone,
   Reg, /* GPRs and FP regs, distinguished by operand size */
+  SReg, /* Segment register */
 };
 
 /* Position of operand_type bits.  */
@@ -720,8 +721,6 @@  enum
   Debug,
   /* Test register */
   Test,
-  /* Segment register */
-  SReg,
   /* 1 bit immediate */
   Imm1,
   /* 8 bit immediate */
@@ -815,7 +814,6 @@  typedef union i386_operand_type
       unsigned int control:1;
       unsigned int debug:1;
       unsigned int test:1;
-      unsigned int sreg:1;
       unsigned int imm1:1;
       unsigned int imm8:1;
       unsigned int imm8s:1;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -30,6 +30,8 @@ 
 #define FloatAcc Acc|Tbyte
 #define FloatReg Class=Reg|Tbyte
 
+#define SReg  Class=SReg
+
 #define RegXMM RegSIMD|Xmmword
 #define RegYMM RegSIMD|Ymmword
 #define RegZMM RegSIMD|Zmmword
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -105,13 +105,13 @@  k5, RegMask, 0, 5, 98, 123
 k6, RegMask, 0, 6, 99, 124
 k7, RegMask, 0, 7, 100, 125
 // Segment registers.
-es, SReg, 0, 0, 40, 50
-cs, SReg, 0, 1, 41, 51
-ss, SReg, 0, 2, 42, 52
-ds, SReg, 0, 3, 43, 53
-fs, SReg, 0, 4, 44, 54
-gs, SReg, 0, 5, 45, 55
-flat, SReg, 0, RegFlat, Dw2Inval, Dw2Inval
+es, Class=SReg, 0, 0, 40, 50
+cs, Class=SReg, 0, 1, 41, 51
+ss, Class=SReg, 0, 2, 42, 52
+ds, Class=SReg, 0, 3, 43, 53
+fs, Class=SReg, 0, 4, 44, 54
+gs, Class=SReg, 0, 5, 45, 55
+flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
 // Control registers.
 cr0, Control, 0, 0, Dw2Inval, Dw2Inval
 cr1, Control, 0, 1, Dw2Inval, Dw2Inval