[01/13] x86: re-arrange process_operands()

Message ID 9b64f820-6c17-0902-5643-63f14674e363@suse.com
State New
Headers show
Series
  • x86: further insn template compaction
Related show

Commit Message

Jan Beulich Oct. 30, 2019, 8:23 a.m.
Alter the sequence of conditions evaluated, without affecting the
overall result. This is going to help subsequent changes (and as a nice
side effect also slightly reduces overall indentation depth).

While doing this take the liberty of simplifying the calculation of the
operand index of the register operand in ShortForm handling.

gas/
2018-10-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (process_operands): Handle ShortForm insns
	later, splitting out their segment register sub-form.

Comments

H.J. Lu Oct. 31, 2019, 5:48 p.m. | #1
On Wed, Oct 30, 2019 at 1:23 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> Alter the sequence of conditions evaluated, without affecting the

> overall result. This is going to help subsequent changes (and as a nice

> side effect also slightly reduces overall indentation depth).

>

> While doing this take the liberty of simplifying the calculation of the

> operand index of the register operand in ShortForm handling.

>

> gas/

> 2018-10-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * config/tc-i386.c (process_operands): Handle ShortForm insns

>         later, splitting out their segment register sub-form.

>


OK.

Thanks.


-- 
H.J.

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7079,63 +7079,7 @@  duplicate:
       i.reg_operands++;
     }
 
-  if (i.tm.opcode_modifier.shortform)
-    {
-      if (i.types[0].bitfield.sreg)
-	{
-	  if (flag_code != CODE_64BIT
-	      ? i.tm.base_opcode == POP_SEG_SHORT
-		&& i.op[0].regs->reg_num == 1
-	      : (i.tm.base_opcode | 1) == POP_SEG386_SHORT
-		&& i.op[0].regs->reg_num < 4)
-	    {
-	      as_bad (_("you can't `%s %s%s'"),
-		      i.tm.name, register_prefix, i.op[0].regs->reg_name);
-	      return 0;
-	    }
-	  if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 )
-	    {
-	      i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
-	      i.tm.opcode_length = 2;
-	    }
-	  i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
-	}
-      else
-	{
-	  /* The register or float register operand is in operand
-	     0 or 1.  */
-	  unsigned int op;
-
-	  if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
-	      || operand_type_check (i.types[0], reg))
-	    op = 0;
-	  else
-	    op = 1;
-	  /* Register goes in low 3 bits of opcode.  */
-	  i.tm.base_opcode |= i.op[op].regs->reg_num;
-	  if ((i.op[op].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_B;
-	  if (!quiet_warnings && i.tm.opcode_modifier.ugh)
-	    {
-	      /* Warn about some common errors, but press on regardless.
-		 The first case can be generated by gcc (<= 2.8.1).  */
-	      if (i.operands == 2)
-		{
-		  /* Reversed arguments on faddp, fsubp, etc.  */
-		  as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
-			   register_prefix, i.op[!intel_syntax].regs->reg_name,
-			   register_prefix, i.op[intel_syntax].regs->reg_name);
-		}
-	      else
-		{
-		  /* Extraneous `l' suffix on fp insn.  */
-		  as_warn (_("translating to `%s %s%s'"), i.tm.name,
-			   register_prefix, i.op[0].regs->reg_name);
-		}
-	    }
-	}
-    }
-  else if (i.tm.opcode_modifier.modrm)
+  if (i.tm.opcode_modifier.modrm)
     {
       /* The opcode is completed (modulo i.tm.extension_opcode which
 	 must be put into the modrm byte).  Now, we make the modrm and
@@ -7143,6 +7087,25 @@  duplicate:
 
       default_seg = build_modrm_byte ();
     }
+  else if (i.types[0].bitfield.sreg)
+    {
+      if (flag_code != CODE_64BIT
+	  ? i.tm.base_opcode == POP_SEG_SHORT
+	    && i.op[0].regs->reg_num == 1
+	  : (i.tm.base_opcode | 1) == POP_SEG386_SHORT
+	    && i.op[0].regs->reg_num < 4)
+	{
+	  as_bad (_("you can't `%s %s%s'"),
+		  i.tm.name, register_prefix, i.op[0].regs->reg_name);
+	  return 0;
+	}
+      if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 )
+	{
+	  i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
+	  i.tm.opcode_length = 2;
+	}
+      i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
+    }
   else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
     {
       default_seg = &ds;
@@ -7153,6 +7116,35 @@  duplicate:
 	 on one of their operands, the default segment is ds.  */
       default_seg = &ds;
     }
+  else if (i.tm.opcode_modifier.shortform)
+    {
+      /* The register or float register operand is in operand
+	 0 or 1.  */
+      unsigned int op = !i.tm.operand_types[0].bitfield.reg;
+
+      /* Register goes in low 3 bits of opcode.  */
+      i.tm.base_opcode |= i.op[op].regs->reg_num;
+      if ((i.op[op].regs->reg_flags & RegRex) != 0)
+	i.rex |= REX_B;
+      if (!quiet_warnings && i.tm.opcode_modifier.ugh)
+	{
+	  /* Warn about some common errors, but press on regardless.
+	     The first case can be generated by gcc (<= 2.8.1).  */
+	  if (i.operands == 2)
+	    {
+	      /* Reversed arguments on faddp, fsubp, etc.  */
+	      as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
+		       register_prefix, i.op[!intel_syntax].regs->reg_name,
+		       register_prefix, i.op[intel_syntax].regs->reg_name);
+	    }
+	  else
+	    {
+	      /* Extraneous `l' suffix on fp insn.  */
+	      as_warn (_("translating to `%s %s%s'"), i.tm.name,
+		       register_prefix, i.op[0].regs->reg_name);
+	    }
+	}
+    }
 
   if (i.tm.base_opcode == 0x8d /* lea */
       && i.seg[0]