[gas,aarch64] Armv8.6-A CLI support [1/10]

Message ID 5db862d0.1c69fb81.ef399.6f22SMTPIN_ADDED_MISSING@mx.google.com
State New
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  • [gas,aarch64] Armv8.6-A CLI support [1/10]
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Commit Message

Mihail Ionescu Oct. 29, 2019, 3:20 p.m.
Hi,

This patch is part of a series that adds support for Armv8.6-A
to binutils.
This first patch adds the Armv8.6-A flag to binutils.
No instructions are behind it at the moment.

gas/ChangeLog:

2019-10-29  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-10-29  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (armv8.6-a): New arch.
	* doc/c-aarch64.texi (armv8.6-a): Document new arch.

include/ChangeLog:

2019-10-29  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-10-29  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_6): New.
	(AARCH64_ARCH_V8_6): New.

opcodes/ChangeLog:

2019-10-29  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-10-29  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-tbl.h (ARMV8_6): New macro.


Is it ok for trunk?


Regards,
Mihail


###############     Attachment also inlined for ease of reply    ###############
                Inline version does not contain generated files
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 522efebfe42ed797e510b4694c2c51827f55728e..36ce67a66bb553c8e34267828222ba6e23c9e351 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8904,6 +8904,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
   {"armv8.3-a", AARCH64_ARCH_V8_3},
   {"armv8.4-a", AARCH64_ARCH_V8_4},
   {"armv8.5-a", AARCH64_ARCH_V8_5},
+  {"armv8.6-a", AARCH64_ARCH_V8_6},
   {NULL, AARCH64_ARCH_NONE}
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 2c236e2c84a202598dcd16e70e4924e64575dcd8..a83a859e4d6cdf69b61080d728fafb68ff0131a2 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -100,7 +100,7 @@ issue an error message if an attempt is made to assemble an
 instruction which will not execute on the target architecture.  The
 following architecture names are recognized: @code{armv8-a},
 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
-and @code{armv8.5-a}.
+@code{armv8.5-a}, and @code{armv8.6-a}.
 
 If both @option{-mcpu} and @option{-march} are specified, the
 assembler will use the setting for @option{-mcpu}.  If neither are
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d0bbe01be6cd4084054a5646107d2bc6ad82bd07..493e8f8655b06d2cd6be93362f4e71959e17362b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -63,6 +63,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
 #define AARCH64_FEATURE_F16_FML	0x1000000000ULL	/* v8.2 FP16FML ins.  */
 #define AARCH64_FEATURE_V8_5	0x2000000000ULL	/* ARMv8.5 processors.  */
+#define AARCH64_FEATURE_V8_6	0x00000002	/* ARMv8.6 processors.  */
 
 /* Flag Manipulation insns.  */
 #define AARCH64_FEATURE_FLAGMANIP	0x4000000000ULL
@@ -129,7 +130,8 @@ typedef uint32_t aarch64_insn;
 						 | AARCH64_FEATURE_SCXTNUM \
 						 | AARCH64_FEATURE_ID_PFR2 \
 						 | AARCH64_FEATURE_SSBS)
-
+#define AARCH64_ARCH_V8_6	AARCH64_FEATURE (AARCH64_ARCH_V8_5,	\
+						 AARCH64_FEATURE_V8_6)
 
 #define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY		AARCH64_FEATURE (-1, 0)	/* Any basic core.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ee36f1c9922e66feef905ce3ac9de77be01cf39f..c1f4479c347e09339e0abe945663989f28a5550d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2343,6 +2343,8 @@ static const aarch64_feature_set aarch64_feature_sve2sm4 =
   AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0);
 static const aarch64_feature_set aarch64_feature_sve2bitperm =
   AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
+static const aarch64_feature_set aarch64_feature_v8_6 =
+  AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
 
 
 #define CORE		&aarch64_feature_v8
@@ -2384,6 +2386,7 @@ static const aarch64_feature_set aarch64_feature_sve2bitperm =
 #define SVE2_SHA3	&aarch64_feature_sve2sha3
 #define SVE2_SM4		&aarch64_feature_sve2sm4
 #define SVE2_BITPERM	&aarch64_feature_sve2bitperm
+#define ARMV8_6		&aarch64_feature_v8_6
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 522efebfe42ed797e510b4694c2c51827f55728e..36ce67a66bb553c8e34267828222ba6e23c9e351 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8904,6 +8904,7 @@  static const struct aarch64_arch_option_table aarch64_archs[] = {
   {"armv8.3-a", AARCH64_ARCH_V8_3},
   {"armv8.4-a", AARCH64_ARCH_V8_4},
   {"armv8.5-a", AARCH64_ARCH_V8_5},
+  {"armv8.6-a", AARCH64_ARCH_V8_6},
   {NULL, AARCH64_ARCH_NONE}
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 2c236e2c84a202598dcd16e70e4924e64575dcd8..a83a859e4d6cdf69b61080d728fafb68ff0131a2 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -100,7 +100,7 @@  issue an error message if an attempt is made to assemble an
 instruction which will not execute on the target architecture.  The
 following architecture names are recognized: @code{armv8-a},
 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
-and @code{armv8.5-a}.
+@code{armv8.5-a}, and @code{armv8.6-a}.
 
 If both @option{-mcpu} and @option{-march} are specified, the
 assembler will use the setting for @option{-mcpu}.  If neither are
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d0bbe01be6cd4084054a5646107d2bc6ad82bd07..493e8f8655b06d2cd6be93362f4e71959e17362b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -63,6 +63,7 @@  typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
 #define AARCH64_FEATURE_F16_FML	0x1000000000ULL	/* v8.2 FP16FML ins.  */
 #define AARCH64_FEATURE_V8_5	0x2000000000ULL	/* ARMv8.5 processors.  */
+#define AARCH64_FEATURE_V8_6	0x00000002	/* ARMv8.6 processors.  */
 
 /* Flag Manipulation insns.  */
 #define AARCH64_FEATURE_FLAGMANIP	0x4000000000ULL
@@ -129,7 +130,8 @@  typedef uint32_t aarch64_insn;
 						 | AARCH64_FEATURE_SCXTNUM \
 						 | AARCH64_FEATURE_ID_PFR2 \
 						 | AARCH64_FEATURE_SSBS)
-
+#define AARCH64_ARCH_V8_6	AARCH64_FEATURE (AARCH64_ARCH_V8_5,	\
+						 AARCH64_FEATURE_V8_6)
 
 #define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY		AARCH64_FEATURE (-1, 0)	/* Any basic core.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ee36f1c9922e66feef905ce3ac9de77be01cf39f..c1f4479c347e09339e0abe945663989f28a5550d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2343,6 +2343,8 @@  static const aarch64_feature_set aarch64_feature_sve2sm4 =
   AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0);
 static const aarch64_feature_set aarch64_feature_sve2bitperm =
   AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
+static const aarch64_feature_set aarch64_feature_v8_6 =
+  AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
 
 
 #define CORE		&aarch64_feature_v8
@@ -2384,6 +2386,7 @@  static const aarch64_feature_set aarch64_feature_sve2bitperm =
 #define SVE2_SHA3	&aarch64_feature_sve2sha3
 #define SVE2_SM4		&aarch64_feature_sve2sm4
 #define SVE2_BITPERM	&aarch64_feature_sve2bitperm
+#define ARMV8_6		&aarch64_feature_v8_6
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }