@@ -6244,49 +6244,26 @@ process_suffix (void)
Destination register type is more significant than source
register type. crc32 in SSE4.2 prefers source register
type. */
- if (i.tm.base_opcode == 0xf20f38f0 && i.types[0].bitfield.reg)
- {
- if (i.types[0].bitfield.byte)
- i.suffix = BYTE_MNEM_SUFFIX;
- else if (i.types[0].bitfield.word)
- i.suffix = WORD_MNEM_SUFFIX;
- else if (i.types[0].bitfield.dword)
- i.suffix = LONG_MNEM_SUFFIX;
- else if (i.types[0].bitfield.qword)
- i.suffix = QWORD_MNEM_SUFFIX;
- }
-
- if (!i.suffix)
- {
- int op;
+ unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1;
- if (i.tm.base_opcode == 0xf20f38f0)
- {
- /* We have to know the operand size for crc32. */
- as_bad (_("ambiguous memory operand size for `%s`"),
- i.tm.name);
- return 0;
- }
-
- for (op = i.operands; --op >= 0;)
- if (!i.tm.operand_types[op].bitfield.inoutportreg
- && !i.tm.operand_types[op].bitfield.shiftcount)
- {
- if (!i.types[op].bitfield.reg)
- continue;
- if (i.types[op].bitfield.byte)
- i.suffix = BYTE_MNEM_SUFFIX;
- else if (i.types[op].bitfield.word)
- i.suffix = WORD_MNEM_SUFFIX;
- else if (i.types[op].bitfield.dword)
- i.suffix = LONG_MNEM_SUFFIX;
- else if (i.types[op].bitfield.qword)
- i.suffix = QWORD_MNEM_SUFFIX;
- else
- continue;
- break;
- }
- }
+ while (op--)
+ if (!i.tm.operand_types[op].bitfield.inoutportreg
+ && !i.tm.operand_types[op].bitfield.shiftcount)
+ {
+ if (!i.types[op].bitfield.reg)
+ continue;
+ if (i.types[op].bitfield.byte)
+ i.suffix = BYTE_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.word)
+ i.suffix = WORD_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.dword)
+ i.suffix = LONG_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.qword)
+ i.suffix = QWORD_MNEM_SUFFIX;
+ else
+ continue;
+ break;
+ }
}
else if (i.suffix == BYTE_MNEM_SUFFIX)
{
@@ -6428,8 +6405,10 @@ process_suffix (void)
i.suffix = SHORT_MNEM_SUFFIX;
else if (flag_code == CODE_16BIT)
i.suffix = WORD_MNEM_SUFFIX;
- else
+ else if (!i.tm.opcode_modifier.no_lsuf)
i.suffix = LONG_MNEM_SUFFIX;
+ else
+ i.suffix = QWORD_MNEM_SUFFIX;
}
}
@@ -3,7 +3,7 @@
.*:7: Error: .*
.*:8: Error: .*
.*:9: Error: .*
-.*:10: Error: .*
+.*:10: Warning: .*
.*:11: Error: .*
.*:12: Error: .*
.*:13: Error: .*
@@ -27,7 +27,9 @@ GAS LISTING .*
[ ]*7[ ]+crc32w \(%esi\), %ax
[ ]*8[ ]+crc32 \(%esi\), %al
[ ]*9[ ]+crc32 \(%esi\), %ax
-[ ]*10[ ]+crc32 \(%esi\), %eax
+[ ]*10[ ]+\?\?\?\? F20F38F1[ ]+crc32 \(%esi\), %eax
+\*\*\*\* Warning: .* `crc32'
+[ ]*10[ ]+06
[ ]*11[ ]+crc32 %al, %al
[ ]*12[ ]+crc32b %al, %al
[ ]*13[ ]+crc32 %ax, %ax
@@ -26,6 +26,7 @@ Disassembly of section .text:
*[a-f0-9]+: 81 3f 34 12 cmpw \$0x1234,\(%bx\)
*[a-f0-9]+: a7 cmpsw %es:\(%di\),%ds:\(%si\)
*[a-f0-9]+: 67 a7 cmpsw %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+: f2 0f 38 f1 07 crc32w \(%bx\),%eax
*[a-f0-9]+: f2 0f 2a 07 cvtsi2sdl \(%bx\),%xmm0
*[a-f0-9]+: f3 0f 2a 07 cvtsi2ssl \(%bx\),%xmm0
*[a-f0-9]+: ff 0f decw \(%bx\)
@@ -17,6 +17,7 @@
.*:[1-9][0-9]*: Warning: .* `cmp'
.*:[1-9][0-9]*: Warning: .* `cmps'
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
.*:[1-9][0-9]*: Warning: .* `dec'
.*:[1-9][0-9]*: Warning: .* `div'
.*:[1-9][0-9]*: Warning: .* `fadd'
@@ -20,6 +20,7 @@ noreg:
cmp $0x1234, (%bx)
cmps
cmps %es:(%edi), (%esi)
+ crc32 (%bx), %eax
cvtsi2sd (%bx), %xmm0
cvtsi2ss (%bx), %xmm0
dec (%bx)
@@ -30,6 +30,7 @@ Disassembly of section .text:
*[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%eax\)
*[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
*[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+: f2 0f 38 f1 00 crc32l \(%eax\),%eax
*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%eax\),%xmm0
*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%eax\),%xmm0
*[a-f0-9]+: ff 08 decl \(%eax\)
@@ -21,6 +21,7 @@
.*:[1-9][0-9]*: Warning: .* `cmp'
.*:[1-9][0-9]*: Warning: .* `cmps'
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
.*:[1-9][0-9]*: Warning: .* `dec'
.*:[1-9][0-9]*: Warning: .* `div'
.*:[1-9][0-9]*: Warning: .* `fadd'
@@ -23,6 +23,7 @@ noreg:
cmp $0x12345678, (%eax)
cmps
cmps %es:(%edi), (%esi)
+ crc32 (%eax), %eax
cvtsi2sd (%eax), %xmm0
cvtsi2ss (%eax), %xmm0
dec (%eax)
@@ -30,6 +30,8 @@ Disassembly of section .text:
*[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%rax\)
*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
+ *[a-f0-9]+: f2 0f 38 f1 00 crc32l \(%rax\),%eax
+ *[a-f0-9]+: f2 48 0f 38 f1 00 crc32q \(%rax\),%rax
*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
*[a-f0-9]+: ff 08 decl \(%rax\)
@@ -21,6 +21,8 @@
.*:[1-9][0-9]*: Warning: .* `cmp'
.*:[1-9][0-9]*: Warning: .* `cmps'
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Warning: .* `crc32'
.*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
.*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
.*:[1-9][0-9]*: Warning: .* `dec'
@@ -23,6 +23,8 @@ noreg:
cmp $0x12345678, (%rax)
cmps
cmps %es:(%rdi), (%rsi)
+ crc32 (%rax), %eax
+ crc32 (%rax), %rax
cvtsi2sd (%rax), %xmm0
cvtsi2ss (%rax), %xmm0
dec (%rax)
@@ -3,8 +3,8 @@
.*:7: Error: .*
.*:8: Error: .*
.*:9: Error: .*
-.*:10: Error: .*
-.*:11: Error: .*
+.*:10: Warning: .*
+.*:11: Warning: .*
.*:12: Error: .*
.*:13: Error: .*
.*:14: Error: .*
@@ -38,8 +38,12 @@ GAS LISTING .*
[ ]*7[ ]+crc32w \(%rsi\), %ax
[ ]*8[ ]+crc32 \(%rsi\), %al
[ ]*9[ ]+crc32 \(%rsi\), %ax
-[ ]*10[ ]+crc32 \(%rsi\), %eax
-[ ]*11[ ]+crc32 \(%rsi\), %rax
+[ ]*10[ ]+\?\?\?\? F20F38F1[ ]+crc32 \(%rsi\), %eax
+\*\*\*\* Warning: .* `crc32'
+[ ]*10[ ]+06
+[ ]*11[ ]+\?\?\?\? F2480F38[ ]+crc32 \(%rsi\), %rax
+\*\*\*\* Warning: .* `crc32'
+[ ]*11[ ]+F106
[ ]*12[ ]+crc32 %al, %al
[ ]*13[ ]+crc32b %al, %al
[ ]*14[ ]+crc32 %ax, %ax