x86: Optimize with EVEX128 encoding for AVX512VL

Message ID CAMe9rOqe6g_kynGhYmuBuzWbRAe+YonKEDdnHTDW+oqBc3w8vQ@mail.gmail.com
State New
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Series
  • x86: Optimize with EVEX128 encoding for AVX512VL
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Commit Message

H.J. Lu March 8, 2018, 1:54 p.m.
On Thu, Mar 8, 2018 at 4:56 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Mar 8, 2018 at 12:23 AM, Jan Beulich <JBeulich@suse.com> wrote:

>> H.J.,

>>

>> having taken another look at the optimizations you've added

>> recently, I have a couple of remarks to make:

>>

>> 1) I don't think optimizations should raise the ISA requirements.

>> The conversions you do from AVX512F to AVX512VL insns are in

>> direct contradiction to the Disp32 -> Disp8 conversion I had

>> suggested a couple of weeks ago, and that you objected to even if

>> done very carefully (I still intend to produce a patch to that effect,

>> to see whether you would want to reconsider). Since changing the

>> vector length doesn't alter the encoding length, and doesn't - afaict -

>> provide any other benefits, I don't think those conversions are

>> useful at all. All that is useful imo are conversions from EVEX to VEX.

>

> It does reduce the vector size which may reduce CPU power and boost

> CPU frequency.  I am checking this patch to use AVX512VL only if it is

> enabled.

>

>> 2) Considering what the ORM states, I wonder whether it wouldn't

>> be beneficial to uniformly convert all zeroing insns to VXORP*/VPXOR*.

>

> I will check.

>

>> 3) While merge masking indeed precludes the optimization, zeroing

>> masking doesn't - after all it doesn't matter for what reason the

>> respective part of the destination gets zeroed.

>

> Would you mind creating a patch to do that?

>

>> 4) I don't think {evex} prefixes should be ignored, i.e. I think the

>> conversion to VEX encoding should be suppressed if that prefix

>> was given.

>

> Yes.  I will fix it.

>


I am checking in this updated patch to cover {evex} prefix.

-- 
H.J.

Comments

Jan Beulich March 8, 2018, 2:03 p.m. | #1
>>> On 08.03.18 at 14:54, <hjl.tools@gmail.com> wrote:

> On Thu, Mar 8, 2018 at 4:56 AM, H.J. Lu <hjl.tools@gmail.com> wrote:

>> On Thu, Mar 8, 2018 at 12:23 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>> H.J.,

>>>

>>> having taken another look at the optimizations you've added

>>> recently, I have a couple of remarks to make:

>>>

>>> 1) I don't think optimizations should raise the ISA requirements.

>>> The conversions you do from AVX512F to AVX512VL insns are in

>>> direct contradiction to the Disp32 -> Disp8 conversion I had

>>> suggested a couple of weeks ago, and that you objected to even if

>>> done very carefully (I still intend to produce a patch to that effect,

>>> to see whether you would want to reconsider). Since changing the

>>> vector length doesn't alter the encoding length, and doesn't - afaict -

>>> provide any other benefits, I don't think those conversions are

>>> useful at all. All that is useful imo are conversions from EVEX to VEX.

>>

>> It does reduce the vector size which may reduce CPU power and boost

>> CPU frequency.  I am checking this patch to use AVX512VL only if it is

>> enabled.

>>

>>> 2) Considering what the ORM states, I wonder whether it wouldn't

>>> be beneficial to uniformly convert all zeroing insns to VXORP*/VPXOR*.

>>

>> I will check.

>>

>>> 3) While merge masking indeed precludes the optimization, zeroing

>>> masking doesn't - after all it doesn't matter for what reason the

>>> respective part of the destination gets zeroed.

>>

>> Would you mind creating a patch to do that?

>>

>>> 4) I don't think {evex} prefixes should be ignored, i.e. I think the

>>> conversion to VEX encoding should be suppressed if that prefix

>>> was given.

>>

>> Yes.  I will fix it.

>>

> 

> I am checking in this updated patch to cover {evex} prefix.


Do you really need that extra pseudo_evex_prefix field, i.e.
why can't you just check i.vec_encoding?

Jan
H.J. Lu March 8, 2018, 2:34 p.m. | #2
On Thu, Mar 8, 2018 at 6:03 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.03.18 at 14:54, <hjl.tools@gmail.com> wrote:

>> On Thu, Mar 8, 2018 at 4:56 AM, H.J. Lu <hjl.tools@gmail.com> wrote:

>>> On Thu, Mar 8, 2018 at 12:23 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>> H.J.,

>>>>

>>>> having taken another look at the optimizations you've added

>>>> recently, I have a couple of remarks to make:

>>>>

>>>> 1) I don't think optimizations should raise the ISA requirements.

>>>> The conversions you do from AVX512F to AVX512VL insns are in

>>>> direct contradiction to the Disp32 -> Disp8 conversion I had

>>>> suggested a couple of weeks ago, and that you objected to even if

>>>> done very carefully (I still intend to produce a patch to that effect,

>>>> to see whether you would want to reconsider). Since changing the

>>>> vector length doesn't alter the encoding length, and doesn't - afaict -

>>>> provide any other benefits, I don't think those conversions are

>>>> useful at all. All that is useful imo are conversions from EVEX to VEX.

>>>

>>> It does reduce the vector size which may reduce CPU power and boost

>>> CPU frequency.  I am checking this patch to use AVX512VL only if it is

>>> enabled.

>>>

>>>> 2) Considering what the ORM states, I wonder whether it wouldn't

>>>> be beneficial to uniformly convert all zeroing insns to VXORP*/VPXOR*.

>>>

>>> I will check.

>>>

>>>> 3) While merge masking indeed precludes the optimization, zeroing

>>>> masking doesn't - after all it doesn't matter for what reason the

>>>> respective part of the destination gets zeroed.

>>>

>>> Would you mind creating a patch to do that?

>>>

>>>> 4) I don't think {evex} prefixes should be ignored, i.e. I think the

>>>> conversion to VEX encoding should be suppressed if that prefix

>>>> was given.

>>>

>>> Yes.  I will fix it.

>>>

>>

>> I am checking in this updated patch to cover {evex} prefix.

>

> Do you really need that extra pseudo_evex_prefix field, i.e.

> why can't you just check i.vec_encoding?

>


Yes, it is needed since  i.vec_encoding will be changed to
vex_encoding_evex by:

 /* Upper 16 vector register is only available with VREX in 64bit
     mode.  */
  if ((r->reg_flags & RegVRex))
    {
      if (i.vec_encoding == vex_encoding_default)
        i.vec_encoding = vex_encoding_evex;


-- 
H.J.
Jan Beulich March 8, 2018, 3:28 p.m. | #3
>>> On 08.03.18 at 15:34, <hjl.tools@gmail.com> wrote:

> On Thu, Mar 8, 2018 at 6:03 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>> On 08.03.18 at 14:54, <hjl.tools@gmail.com> wrote:

>>> On Thu, Mar 8, 2018 at 4:56 AM, H.J. Lu <hjl.tools@gmail.com> wrote:

>>>> On Thu, Mar 8, 2018 at 12:23 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>> H.J.,

>>>>>

>>>>> having taken another look at the optimizations you've added

>>>>> recently, I have a couple of remarks to make:

>>>>>

>>>>> 1) I don't think optimizations should raise the ISA requirements.

>>>>> The conversions you do from AVX512F to AVX512VL insns are in

>>>>> direct contradiction to the Disp32 -> Disp8 conversion I had

>>>>> suggested a couple of weeks ago, and that you objected to even if

>>>>> done very carefully (I still intend to produce a patch to that effect,

>>>>> to see whether you would want to reconsider). Since changing the

>>>>> vector length doesn't alter the encoding length, and doesn't - afaict -

>>>>> provide any other benefits, I don't think those conversions are

>>>>> useful at all. All that is useful imo are conversions from EVEX to VEX.

>>>>

>>>> It does reduce the vector size which may reduce CPU power and boost

>>>> CPU frequency.  I am checking this patch to use AVX512VL only if it is

>>>> enabled.

>>>>

>>>>> 2) Considering what the ORM states, I wonder whether it wouldn't

>>>>> be beneficial to uniformly convert all zeroing insns to VXORP*/VPXOR*.

>>>>

>>>> I will check.

>>>>

>>>>> 3) While merge masking indeed precludes the optimization, zeroing

>>>>> masking doesn't - after all it doesn't matter for what reason the

>>>>> respective part of the destination gets zeroed.

>>>>

>>>> Would you mind creating a patch to do that?

>>>>

>>>>> 4) I don't think {evex} prefixes should be ignored, i.e. I think the

>>>>> conversion to VEX encoding should be suppressed if that prefix

>>>>> was given.

>>>>

>>>> Yes.  I will fix it.

>>>>

>>>

>>> I am checking in this updated patch to cover {evex} prefix.

>>

>> Do you really need that extra pseudo_evex_prefix field, i.e.

>> why can't you just check i.vec_encoding?

>>

> 

> Yes, it is needed since  i.vec_encoding will be changed to

> vex_encoding_evex by:

> 

>  /* Upper 16 vector register is only available with VREX in 64bit

>      mode.  */

>   if ((r->reg_flags & RegVRex))

>     {

>       if (i.vec_encoding == vex_encoding_default)

>         i.vec_encoding = vex_encoding_evex;


But in that case you can't lower to VEX encoding anyway.

Jan
H.J. Lu March 8, 2018, 4:08 p.m. | #4
On Thu, Mar 8, 2018 at 7:28 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.03.18 at 15:34, <hjl.tools@gmail.com> wrote:

>> On Thu, Mar 8, 2018 at 6:03 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>>> On 08.03.18 at 14:54, <hjl.tools@gmail.com> wrote:

>>>> On Thu, Mar 8, 2018 at 4:56 AM, H.J. Lu <hjl.tools@gmail.com> wrote:

>>>>> On Thu, Mar 8, 2018 at 12:23 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>>> H.J.,

>>>>>>

>>>>>> having taken another look at the optimizations you've added

>>>>>> recently, I have a couple of remarks to make:

>>>>>>

>>>>>> 1) I don't think optimizations should raise the ISA requirements.

>>>>>> The conversions you do from AVX512F to AVX512VL insns are in

>>>>>> direct contradiction to the Disp32 -> Disp8 conversion I had

>>>>>> suggested a couple of weeks ago, and that you objected to even if

>>>>>> done very carefully (I still intend to produce a patch to that effect,

>>>>>> to see whether you would want to reconsider). Since changing the

>>>>>> vector length doesn't alter the encoding length, and doesn't - afaict -

>>>>>> provide any other benefits, I don't think those conversions are

>>>>>> useful at all. All that is useful imo are conversions from EVEX to VEX.

>>>>>

>>>>> It does reduce the vector size which may reduce CPU power and boost

>>>>> CPU frequency.  I am checking this patch to use AVX512VL only if it is

>>>>> enabled.

>>>>>

>>>>>> 2) Considering what the ORM states, I wonder whether it wouldn't

>>>>>> be beneficial to uniformly convert all zeroing insns to VXORP*/VPXOR*.

>>>>>

>>>>> I will check.

>>>>>

>>>>>> 3) While merge masking indeed precludes the optimization, zeroing

>>>>>> masking doesn't - after all it doesn't matter for what reason the

>>>>>> respective part of the destination gets zeroed.

>>>>>

>>>>> Would you mind creating a patch to do that?

>>>>>

>>>>>> 4) I don't think {evex} prefixes should be ignored, i.e. I think the

>>>>>> conversion to VEX encoding should be suppressed if that prefix

>>>>>> was given.

>>>>>

>>>>> Yes.  I will fix it.

>>>>>

>>>>

>>>> I am checking in this updated patch to cover {evex} prefix.

>>>

>>> Do you really need that extra pseudo_evex_prefix field, i.e.

>>> why can't you just check i.vec_encoding?

>>>

>>

>> Yes, it is needed since  i.vec_encoding will be changed to

>> vex_encoding_evex by:

>>

>>  /* Upper 16 vector register is only available with VREX in 64bit

>>      mode.  */

>>   if ((r->reg_flags & RegVRex))

>>     {

>>       if (i.vec_encoding == vex_encoding_default)

>>         i.vec_encoding = vex_encoding_evex;

>

> But in that case you can't lower to VEX encoding anyway.

>


You are right.  Here is the updated patch.


-- 
H.J.
From fb7acc543698c8d60c4f001e2b1d73be6365bf88 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 8 Mar 2018 04:19:14 -0800
Subject: [PATCH] x86: Optimize with EVEX128 encoding for AVX512VL

We can optimize AVX512 instructions with EVEX128 only if AVX512VL is
enabled:

1. Instruction is an AVX512VL instruction. Or
2. AVX512VL is enabled explicitly by -march=+avx512vl/".arch .avx512vl".

We should optimize EVEX instructions with EVEX128 encoding when pseudo
{evex} prefix is used.

	* config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags.
	(md_parse_option): Likewise.
	(optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
	for cpuavx512vl instead of cpu_arch_flags.  Optimize EVEX with
	EVEX128 when EVEX encoding is required.
	* testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
	x86-64-optimize-5 and x86-64-optimize-6.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-4.d: New file.
	* testsuite/gas/i386/optimize-4.s: Likewise.
	* testsuite/gas/i386/optimize-5.d: Likewise.
	* testsuite/gas/i386/optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
---
 gas/config/tc-i386.c                       |  36 +++++++---
 gas/testsuite/gas/i386/i386.exp            |   4 ++
 gas/testsuite/gas/i386/optimize-1.d        |  24 +++----
 gas/testsuite/gas/i386/optimize-4.d        |  63 ++++++++++++++++
 gas/testsuite/gas/i386/optimize-4.s        |   6 ++
 gas/testsuite/gas/i386/optimize-5.d        |  63 ++++++++++++++++
 gas/testsuite/gas/i386/optimize-5.s        |   8 +++
 gas/testsuite/gas/i386/x86-64-optimize-2.d |  72 +++++++++----------
 gas/testsuite/gas/i386/x86-64-optimize-5.d | 111 +++++++++++++++++++++++++++++
 gas/testsuite/gas/i386/x86-64-optimize-5.s |   6 ++
 gas/testsuite/gas/i386/x86-64-optimize-6.d | 111 +++++++++++++++++++++++++++++
 gas/testsuite/gas/i386/x86-64-optimize-6.s |   8 +++
 12 files changed, 453 insertions(+), 59 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/optimize-4.d
 create mode 100644 gas/testsuite/gas/i386/optimize-4.s
 create mode 100644 gas/testsuite/gas/i386/optimize-5.d
 create mode 100644 gas/testsuite/gas/i386/optimize-5.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-5.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-5.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-6.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-6.s

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 1c64d08ab2..001b016879 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2622,6 +2622,10 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
 		  cpu_arch_flags = flags;
 		  cpu_arch_isa_flags = flags;
 		}
+	      else
+		cpu_arch_isa_flags
+		  = cpu_flags_or (cpu_arch_isa_flags,
+				  cpu_arch[j].flags);
 	      (void) restore_line_pointer (e);
 	      demand_empty_rest_of_line ();
 	      return;
@@ -3871,7 +3875,8 @@ optimize_encoding (void)
 	       || (!i.mask
 		   && !i.rounding
 		   && is_evex_encoding (&i.tm)
-		   && cpu_arch_flags.bitfield.cpuavx512vl))
+		   && (i.tm.cpu_flags.bitfield.cpuavx512vl
+		       || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
 	   && ((i.tm.base_opcode == 0x55
 		|| i.tm.base_opcode == 0x6655
 		|| i.tm.base_opcode == 0x66df
@@ -3915,19 +3920,24 @@ optimize_encoding (void)
        */
       if (is_evex_encoding (&i.tm))
 	{
-	  /* If only lower 16 vector registers are used, we can use
-	     VEX encoding.  */
-	  for (j = 0; j < 3; j++)
-	    if (register_number (i.op[j].regs) > 15)
-	      break;
-
-	  if (j < 3)
+	  if (i.vec_encoding == vex_encoding_evex)
 	    i.tm.opcode_modifier.evex = EVEX128;
 	  else
 	    {
-	      i.tm.opcode_modifier.vex = VEX128;
-	      i.tm.opcode_modifier.vexw = VEXW0;
-	      i.tm.opcode_modifier.evex = 0;
+	      /* If only lower 16 vector registers are used, we can use
+		 VEX encoding.  */
+	      for (j = 0; j < 3; j++)
+		if (register_number (i.op[j].regs) > 15)
+		  break;
+
+	      if (j < 3)
+		i.tm.opcode_modifier.evex = EVEX128;
+	      else
+		{
+		  i.tm.opcode_modifier.vex = VEX128;
+		  i.tm.opcode_modifier.vexw = VEXW0;
+		  i.tm.opcode_modifier.evex = 0;
+		}
 	    }
 	}
       else
@@ -10524,6 +10534,10 @@ md_parse_option (int c, const char *arg)
 		      cpu_arch_flags = flags;
 		      cpu_arch_isa_flags = flags;
 		    }
+		  else
+		    cpu_arch_isa_flags
+		      = cpu_flags_or (cpu_arch_isa_flags,
+				      cpu_arch[j].flags);
 		  break;
 		}
 	    }
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index f28e6a96d9..fd87562c3a 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -442,6 +442,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "optimize-1"
     run_dump_test "optimize-2"
     run_dump_test "optimize-3"
+    run_dump_test "optimize-4"
+    run_dump_test "optimize-5"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -928,6 +930,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-optimize-2"
     run_dump_test "x86-64-optimize-3"
     run_dump_test "x86-64-optimize-4"
+    run_dump_test "x86-64-optimize-5"
+    run_dump_test "x86-64-optimize-6"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/optimize-1.d b/gas/testsuite/gas/i386/optimize-1.d
index 3ea6e75b9a..f7da296697 100644
--- a/gas/testsuite/gas/i386/optimize-1.d
+++ b/gas/testsuite/gas/i386/optimize-1.d
@@ -10,52 +10,52 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 55 e9    	vandnpd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 48 55 e9    	vandnps %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 df e9    	vpandnd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 df e9    	vpandnq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 57 e9    	vxorpd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 48 57 e9    	vxorps %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 ef e9    	vpxord %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 ef e9    	vpxorq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 f8 e9    	vpsubb %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 f9 e9    	vpsubw %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 fa e9    	vpsubd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 fb e9    	vpsubq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
 #pass
diff --git a/gas/testsuite/gas/i386/optimize-4.d b/gas/testsuite/gas/i386/optimize-4.d
new file mode 100644
index 0000000000..8c1cea51ed
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-4.d
@@ -0,0 +1,63 @@
+#as: -O2 -march=+avx512vl -I${srcdir}/$subdir
+#objdump: -drw
+#name: optimized encoding 4 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/optimize-4.s b/gas/testsuite/gas/i386/optimize-4.s
new file mode 100644
index 0000000000..b44c44af9a
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-4.s
@@ -0,0 +1,6 @@
+# Check instructions with optimized encoding
+
+.include "optimize-1.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
+	{evex} vandnpd %ymm1, %ymm1, %ymm5
diff --git a/gas/testsuite/gas/i386/optimize-5.d b/gas/testsuite/gas/i386/optimize-5.d
new file mode 100644
index 0000000000..13cd578790
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-5.d
@@ -0,0 +1,63 @@
+#as: -O2 -I${srcdir}/$subdir
+#objdump: -drw
+#name: optimized encoding 5 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/optimize-5.s b/gas/testsuite/gas/i386/optimize-5.s
new file mode 100644
index 0000000000..66c762bd3b
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-5.s
@@ -0,0 +1,8 @@
+# Check instructions with optimized encoding
+
+	.arch .avx512vl
+
+.include "optimize-1.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
+	{evex} vandnpd %ymm1, %ymm1, %ymm5
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.d b/gas/testsuite/gas/i386/x86-64-optimize-2.d
index f59e9b6808..9222efe8c1 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.d
@@ -10,100 +10,100 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 55 f9    	vandnpd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 55 c1    	vandnpd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 55 c9    	vandnpd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 74 48 55 f9    	vandnps %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 48 55 c1    	vandnps %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 40 55 c9    	vandnps %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 df f9    	vpandnd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 48 df c1    	vpandnd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 df c9    	vpandnd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 df f9    	vpandnq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 df c1    	vpandnq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 df c9    	vpandnq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 57 f9    	vxorpd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 57 c1    	vxorpd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 57 c9    	vxorpd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 74 48 57 f9    	vxorps %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 48 57 c1    	vxorps %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 40 57 c9    	vxorps %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 ef f9    	vpxord %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 ef c1    	vpxord %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 ef c9    	vpxord %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 ef f9    	vpxorq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 ef c1    	vpxorq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 ef c9    	vpxorq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 f8 f9    	vpsubb %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 48 f8 c1    	vpsubb %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 f8 c9    	vpsubb %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 f9 f9    	vpsubw %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 f9 c1    	vpsubw %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 f9 c9    	vpsubw %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 fa f9    	vpsubd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 fa c1    	vpsubd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 fa c9    	vpsubd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 fb f9    	vpsubq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 48 fb c1    	vpsubq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 fb c9    	vpsubq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.d b/gas/testsuite/gas/i386/x86-64-optimize-5.d
new file mode 100644
index 0000000000..3ef5746cef
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.d
@@ -0,0 +1,111 @@
+#as: -O2 -march=+avx512vl -I${srcdir}/$subdir
+#objdump: -drw
+#name: x86-64 optimized encoding 5 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.s b/gas/testsuite/gas/i386/x86-64-optimize-5.s
new file mode 100644
index 0000000000..6b4ff103ab
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.s
@@ -0,0 +1,6 @@
+# Check 64bit instructions with optimized encoding
+
+.include "x86-64-optimize-2.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
+	{evex} vandnpd %ymm1, %ymm1, %ymm5
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.d b/gas/testsuite/gas/i386/x86-64-optimize-6.d
new file mode 100644
index 0000000000..527f1a039f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.d
@@ -0,0 +1,111 @@
+#as: -O2 -I${srcdir}/$subdir
+#objdump: -drw
+#name: x86-64 optimized encoding 6 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.s b/gas/testsuite/gas/i386/x86-64-optimize-6.s
new file mode 100644
index 0000000000..70ccbc41be
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.s
@@ -0,0 +1,8 @@
+# Check 64bit instructions with optimized encoding
+
+	.arch .avx512vl
+
+.include "x86-64-optimize-2.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
+	{evex} vandnpd %ymm1, %ymm1, %ymm5
Jan Beulich March 8, 2018, 4:46 p.m. | #5
>>> On 08.03.18 at 17:08, <hjl.tools@gmail.com> wrote:

> On Thu, Mar 8, 2018 at 7:28 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>> On 08.03.18 at 15:34, <hjl.tools@gmail.com> wrote:

>>> On Thu, Mar 8, 2018 at 6:03 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>> Do you really need that extra pseudo_evex_prefix field, i.e.

>>>> why can't you just check i.vec_encoding?

>>>>

>>>

>>> Yes, it is needed since  i.vec_encoding will be changed to

>>> vex_encoding_evex by:

>>>

>>>  /* Upper 16 vector register is only available with VREX in 64bit

>>>      mode.  */

>>>   if ((r->reg_flags & RegVRex))

>>>     {

>>>       if (i.vec_encoding == vex_encoding_default)

>>>         i.vec_encoding = vex_encoding_evex;

>>

>> But in that case you can't lower to VEX encoding anyway.

>>

> 

> You are right.  Here is the updated patch.


LGTM, FWIW.

Jan
H.J. Lu March 8, 2018, 4:49 p.m. | #6
On Thu, Mar 8, 2018 at 8:46 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 08.03.18 at 17:08, <hjl.tools@gmail.com> wrote:

>> On Thu, Mar 8, 2018 at 7:28 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>>> On 08.03.18 at 15:34, <hjl.tools@gmail.com> wrote:

>>>> On Thu, Mar 8, 2018 at 6:03 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>> Do you really need that extra pseudo_evex_prefix field, i.e.

>>>>> why can't you just check i.vec_encoding?

>>>>>

>>>>

>>>> Yes, it is needed since  i.vec_encoding will be changed to

>>>> vex_encoding_evex by:

>>>>

>>>>  /* Upper 16 vector register is only available with VREX in 64bit

>>>>      mode.  */

>>>>   if ((r->reg_flags & RegVRex))

>>>>     {

>>>>       if (i.vec_encoding == vex_encoding_default)

>>>>         i.vec_encoding = vex_encoding_evex;

>>>

>>> But in that case you can't lower to VEX encoding anyway.

>>>

>>

>> You are right.  Here is the updated patch.

>

> LGTM, FWIW.

>


I will give it some tests and check it in later.

Thanks.

-- 
H.J.
H.J. Lu March 9, 2018, 3:56 a.m. | #7
On Thu, Mar 8, 2018 at 8:49 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Mar 8, 2018 at 8:46 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>> On 08.03.18 at 17:08, <hjl.tools@gmail.com> wrote:

>>> On Thu, Mar 8, 2018 at 7:28 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>>>> On 08.03.18 at 15:34, <hjl.tools@gmail.com> wrote:

>>>>> On Thu, Mar 8, 2018 at 6:03 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>>> Do you really need that extra pseudo_evex_prefix field, i.e.

>>>>>> why can't you just check i.vec_encoding?

>>>>>>

>>>>>

>>>>> Yes, it is needed since  i.vec_encoding will be changed to

>>>>> vex_encoding_evex by:

>>>>>

>>>>>  /* Upper 16 vector register is only available with VREX in 64bit

>>>>>      mode.  */

>>>>>   if ((r->reg_flags & RegVRex))

>>>>>     {

>>>>>       if (i.vec_encoding == vex_encoding_default)

>>>>>         i.vec_encoding = vex_encoding_evex;

>>>>

>>>> But in that case you can't lower to VEX encoding anyway.

>>>>

>>>

>>> You are right.  Here is the updated patch.

>>

>> LGTM, FWIW.

>>

>

> I will give it some tests and check it in later.

>

> Thanks.

>


This is the patch I am checking in.  If i.vec_encoding == vex_encoding_evex,
we need to use EVEX128 encoding.


-- 
H.J.
From 7323bd55197ee58f7cd42307a54c7efce4638032 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 8 Mar 2018 04:19:14 -0800
Subject: [PATCH] x86: Optimize with EVEX128 encoding for AVX512VL

We can optimize AVX512 instructions with EVEX128 only if AVX512VL is
enabled:

1. Instruction is an AVX512VL instruction. Or
2. AVX512VL is enabled explicitly by -march=+avx512vl/".arch .avx512vl".

We should optimize EVEX instructions with EVEX128 encoding when pseudo
{evex} prefix is used.

	* config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags.
	(md_parse_option): Likewise.
	(optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
	for cpuavx512vl instead of cpu_arch_flags.  Optimize EVEX with
	EVEX128 when EVEX encoding is required.
	* testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
	x86-64-optimize-5 and x86-64-optimize-6.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-4.d: New file.
	* testsuite/gas/i386/optimize-4.s: Likewise.
	* testsuite/gas/i386/optimize-5.d: Likewise.
	* testsuite/gas/i386/optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
---
 gas/config/tc-i386.c                       |  19 ++---
 gas/testsuite/gas/i386/i386.exp            |   4 ++
 gas/testsuite/gas/i386/optimize-1.d        |  24 +++----
 gas/testsuite/gas/i386/optimize-4.d        |  63 ++++++++++++++++
 gas/testsuite/gas/i386/optimize-4.s        |   6 ++
 gas/testsuite/gas/i386/optimize-5.d        |  63 ++++++++++++++++
 gas/testsuite/gas/i386/optimize-5.s        |   8 +++
 gas/testsuite/gas/i386/x86-64-optimize-2.d |  72 +++++++++----------
 gas/testsuite/gas/i386/x86-64-optimize-5.d | 111 +++++++++++++++++++++++++++++
 gas/testsuite/gas/i386/x86-64-optimize-5.s |   6 ++
 gas/testsuite/gas/i386/x86-64-optimize-6.d | 111 +++++++++++++++++++++++++++++
 gas/testsuite/gas/i386/x86-64-optimize-6.s |   8 +++
 12 files changed, 439 insertions(+), 56 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/optimize-4.d
 create mode 100644 gas/testsuite/gas/i386/optimize-4.s
 create mode 100644 gas/testsuite/gas/i386/optimize-5.d
 create mode 100644 gas/testsuite/gas/i386/optimize-5.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-5.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-5.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-6.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-6.s

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 1c64d08ab2..ef7b64b40b 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2622,6 +2622,10 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
 		  cpu_arch_flags = flags;
 		  cpu_arch_isa_flags = flags;
 		}
+	      else
+		cpu_arch_isa_flags
+		  = cpu_flags_or (cpu_arch_isa_flags,
+				  cpu_arch[j].flags);
 	      (void) restore_line_pointer (e);
 	      demand_empty_rest_of_line ();
 	      return;
@@ -3871,7 +3875,8 @@ optimize_encoding (void)
 	       || (!i.mask
 		   && !i.rounding
 		   && is_evex_encoding (&i.tm)
-		   && cpu_arch_flags.bitfield.cpuavx512vl))
+		   && (i.tm.cpu_flags.bitfield.cpuavx512vl
+		       || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
 	   && ((i.tm.base_opcode == 0x55
 		|| i.tm.base_opcode == 0x6655
 		|| i.tm.base_opcode == 0x66df
@@ -3915,13 +3920,7 @@ optimize_encoding (void)
        */
       if (is_evex_encoding (&i.tm))
 	{
-	  /* If only lower 16 vector registers are used, we can use
-	     VEX encoding.  */
-	  for (j = 0; j < 3; j++)
-	    if (register_number (i.op[j].regs) > 15)
-	      break;
-
-	  if (j < 3)
+	  if (i.vec_encoding == vex_encoding_evex)
 	    i.tm.opcode_modifier.evex = EVEX128;
 	  else
 	    {
@@ -10524,6 +10523,10 @@ md_parse_option (int c, const char *arg)
 		      cpu_arch_flags = flags;
 		      cpu_arch_isa_flags = flags;
 		    }
+		  else
+		    cpu_arch_isa_flags
+		      = cpu_flags_or (cpu_arch_isa_flags,
+				      cpu_arch[j].flags);
 		  break;
 		}
 	    }
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index f28e6a96d9..fd87562c3a 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -442,6 +442,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "optimize-1"
     run_dump_test "optimize-2"
     run_dump_test "optimize-3"
+    run_dump_test "optimize-4"
+    run_dump_test "optimize-5"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -928,6 +930,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-optimize-2"
     run_dump_test "x86-64-optimize-3"
     run_dump_test "x86-64-optimize-4"
+    run_dump_test "x86-64-optimize-5"
+    run_dump_test "x86-64-optimize-6"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/optimize-1.d b/gas/testsuite/gas/i386/optimize-1.d
index 3ea6e75b9a..f7da296697 100644
--- a/gas/testsuite/gas/i386/optimize-1.d
+++ b/gas/testsuite/gas/i386/optimize-1.d
@@ -10,52 +10,52 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 55 e9    	vandnpd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 48 55 e9    	vandnps %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 df e9    	vpandnd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 df e9    	vpandnq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 57 e9    	vxorpd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 48 57 e9    	vxorps %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 ef e9    	vpxord %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 ef e9    	vpxorq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 f8 e9    	vpsubb %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 f9 e9    	vpsubw %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 fa e9    	vpsubd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 fb e9    	vpsubq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
 #pass
diff --git a/gas/testsuite/gas/i386/optimize-4.d b/gas/testsuite/gas/i386/optimize-4.d
new file mode 100644
index 0000000000..8c1cea51ed
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-4.d
@@ -0,0 +1,63 @@
+#as: -O2 -march=+avx512vl -I${srcdir}/$subdir
+#objdump: -drw
+#name: optimized encoding 4 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/optimize-4.s b/gas/testsuite/gas/i386/optimize-4.s
new file mode 100644
index 0000000000..b44c44af9a
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-4.s
@@ -0,0 +1,6 @@
+# Check instructions with optimized encoding
+
+.include "optimize-1.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
+	{evex} vandnpd %ymm1, %ymm1, %ymm5
diff --git a/gas/testsuite/gas/i386/optimize-5.d b/gas/testsuite/gas/i386/optimize-5.d
new file mode 100644
index 0000000000..13cd578790
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-5.d
@@ -0,0 +1,63 @@
+#as: -O2 -I${srcdir}/$subdir
+#objdump: -drw
+#name: optimized encoding 5 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/optimize-5.s b/gas/testsuite/gas/i386/optimize-5.s
new file mode 100644
index 0000000000..66c762bd3b
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-5.s
@@ -0,0 +1,8 @@
+# Check instructions with optimized encoding
+
+	.arch .avx512vl
+
+.include "optimize-1.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
+	{evex} vandnpd %ymm1, %ymm1, %ymm5
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.d b/gas/testsuite/gas/i386/x86-64-optimize-2.d
index f59e9b6808..9222efe8c1 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.d
@@ -10,100 +10,100 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 55 f9    	vandnpd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 55 c1    	vandnpd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 55 c9    	vandnpd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 74 48 55 f9    	vandnps %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 48 55 c1    	vandnps %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 40 55 c9    	vandnps %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 df f9    	vpandnd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 48 df c1    	vpandnd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 df c9    	vpandnd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 df f9    	vpandnq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 df c1    	vpandnq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 df c9    	vpandnq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 57 f9    	vxorpd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 57 c1    	vxorpd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 57 c9    	vxorpd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 74 48 57 f9    	vxorps %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 48 57 c1    	vxorps %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 40 57 c9    	vxorps %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 ef f9    	vpxord %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 ef c1    	vpxord %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 ef c9    	vpxord %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 ef f9    	vpxorq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 ef c1    	vpxorq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 ef c9    	vpxorq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 f8 f9    	vpsubb %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 48 f8 c1    	vpsubb %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 f8 c9    	vpsubb %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 f9 f9    	vpsubw %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 f9 c1    	vpsubw %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 f9 c9    	vpsubw %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 fa f9    	vpsubd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 fa c1    	vpsubd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 fa c9    	vpsubd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 fb f9    	vpsubq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 48 fb c1    	vpsubq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 fb c9    	vpsubq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.d b/gas/testsuite/gas/i386/x86-64-optimize-5.d
new file mode 100644
index 0000000000..3ef5746cef
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.d
@@ -0,0 +1,111 @@
+#as: -O2 -march=+avx512vl -I${srcdir}/$subdir
+#objdump: -drw
+#name: x86-64 optimized encoding 5 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.s b/gas/testsuite/gas/i386/x86-64-optimize-5.s
new file mode 100644
index 0000000000..6b4ff103ab
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.s
@@ -0,0 +1,6 @@
+# Check 64bit instructions with optimized encoding
+
+.include "x86-64-optimize-2.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
+	{evex} vandnpd %ymm1, %ymm1, %ymm5
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.d b/gas/testsuite/gas/i386/x86-64-optimize-6.d
new file mode 100644
index 0000000000..527f1a039f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.d
@@ -0,0 +1,111 @@
+#as: -O2 -I${srcdir}/$subdir
+#objdump: -drw
+#name: x86-64 optimized encoding 6 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.s b/gas/testsuite/gas/i386/x86-64-optimize-6.s
new file mode 100644
index 0000000000..70ccbc41be
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.s
@@ -0,0 +1,8 @@
+# Check 64bit instructions with optimized encoding
+
+	.arch .avx512vl
+
+.include "x86-64-optimize-2.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
+	{evex} vandnpd %ymm1, %ymm1, %ymm5
Jan Beulich March 9, 2018, 8:30 a.m. | #8
>>> On 09.03.18 at 04:56, <hjl.tools@gmail.com> wrote:

> This is the patch I am checking in.  If i.vec_encoding == vex_encoding_evex,

> we need to use EVEX128 encoding.


But this retains some of the ISA extensions problem - only EVEX512
should be used without "i.tm.cpu_flags.bitfield.cpuavx512vl ||
cpu_arch_isa_flags.bitfield.cpuavx512vl".

Jan
H.J. Lu March 9, 2018, 11:21 a.m. | #9
On Fri, Mar 9, 2018 at 12:30 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 09.03.18 at 04:56, <hjl.tools@gmail.com> wrote:

>> This is the patch I am checking in.  If i.vec_encoding == vex_encoding_evex,

>> we need to use EVEX128 encoding.

>

> But this retains some of the ISA extensions problem - only EVEX512

> should be used without "i.tm.cpu_flags.bitfield.cpuavx512vl ||

> cpu_arch_isa_flags.bitfield.cpuavx512vl".

>


The condition is:

         && (i.tm.opcode_modifier.vex
               || (!i.mask
                   && !i.rounding
                   && is_evex_encoding (&i.tm)
                   && (i.tm.cpu_flags.bitfield.cpuavx512vl
                       || cpu_arch_isa_flags.bitfield.cpuavx512vl)))

For EVEX512 instructions, if

i.tm.cpu_flags.bitfield.cpuavx512vl || cpu_arch_isa_flags.bitfield.cpuavx512vl

false, the optimization is disabled.

-- 
H.J.
Jan Beulich March 9, 2018, 11:54 a.m. | #10
>>> On 09.03.18 at 12:21, <hjl.tools@gmail.com> wrote:

> On Fri, Mar 9, 2018 at 12:30 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>> On 09.03.18 at 04:56, <hjl.tools@gmail.com> wrote:

>>> This is the patch I am checking in.  If i.vec_encoding == vex_encoding_evex,

>>> we need to use EVEX128 encoding.

>>

>> But this retains some of the ISA extensions problem - only EVEX512

>> should be used without "i.tm.cpu_flags.bitfield.cpuavx512vl ||

>> cpu_arch_isa_flags.bitfield.cpuavx512vl".

>>

> 

> The condition is:

> 

>          && (i.tm.opcode_modifier.vex

>                || (!i.mask

>                    && !i.rounding

>                    && is_evex_encoding (&i.tm)

>                    && (i.tm.cpu_flags.bitfield.cpuavx512vl

>                        || cpu_arch_isa_flags.bitfield.cpuavx512vl)))

> 

> For EVEX512 instructions, if

> 

> i.tm.cpu_flags.bitfield.cpuavx512vl || 

> cpu_arch_isa_flags.bitfield.cpuavx512vl

> 

> false, the optimization is disabled.


Oh, yes, I see - that asn't visible from the patch alone. I'm sorry
for the noise. I now also see why you could nicely get rid of that
extra loop over the register numbers.

Jan
H.J. Lu March 9, 2018, 3:47 p.m. | #11
On Fri, Mar 9, 2018 at 3:54 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 09.03.18 at 12:21, <hjl.tools@gmail.com> wrote:

>> On Fri, Mar 9, 2018 at 12:30 AM, Jan Beulich <JBeulich@suse.com> wrote:

>>>>>> On 09.03.18 at 04:56, <hjl.tools@gmail.com> wrote:

>>>> This is the patch I am checking in.  If i.vec_encoding == vex_encoding_evex,

>>>> we need to use EVEX128 encoding.

>>>

>>> But this retains some of the ISA extensions problem - only EVEX512

>>> should be used without "i.tm.cpu_flags.bitfield.cpuavx512vl ||

>>> cpu_arch_isa_flags.bitfield.cpuavx512vl".

>>>

>>

>> The condition is:

>>

>>          && (i.tm.opcode_modifier.vex

>>                || (!i.mask

>>                    && !i.rounding

>>                    && is_evex_encoding (&i.tm)

>>                    && (i.tm.cpu_flags.bitfield.cpuavx512vl

>>                        || cpu_arch_isa_flags.bitfield.cpuavx512vl)))

>>

>> For EVEX512 instructions, if

>>

>> i.tm.cpu_flags.bitfield.cpuavx512vl ||

>> cpu_arch_isa_flags.bitfield.cpuavx512vl

>>

>> false, the optimization is disabled.

>

> Oh, yes, I see - that asn't visible from the patch alone. I'm sorry

> for the noise. I now also see why you could nicely get rid of that

> extra loop over the register numbers.

>


We can do better.  If EVEX encoding isn't required, we can encode
EVEX instructions with VEX128.  I am checking in this patch.

-- 
H.J.
From d34afb133d7224a91e179151fa7f4a6e5eb07e03 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Fri, 9 Mar 2018 07:43:30 -0800
Subject: [PATCH] x86: Encode EVEX instructions with VEX128 if possible

If EVEX encoding isn't required, we can encode EVEX instructions with
VEX128.

	* config/tc-i386.c (optimize_encoding): Encode EVEX instructions
	with VEX128 if EVEX encoding isn't required.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
---
 gas/config/tc-i386.c                       |  3 ++-
 gas/testsuite/gas/i386/optimize-1.d        | 24 ++++++++++++------------
 gas/testsuite/gas/i386/x86-64-optimize-2.d | 24 ++++++++++++------------
 3 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 724376096f..e94e01cf10 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3875,7 +3875,8 @@ optimize_encoding (void)
 	       || (!i.mask
 		   && !i.rounding
 		   && is_evex_encoding (&i.tm)
-		   && (i.tm.cpu_flags.bitfield.cpuavx512vl
+		   && (i.vec_encoding != vex_encoding_evex
+		       || i.tm.cpu_flags.bitfield.cpuavx512vl
 		       || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
 	   && ((i.tm.base_opcode == 0x55
 		|| i.tm.base_opcode == 0x6655
diff --git a/gas/testsuite/gas/i386/optimize-1.d b/gas/testsuite/gas/i386/optimize-1.d
index f7da296697..3ea6e75b9a 100644
--- a/gas/testsuite/gas/i386/optimize-1.d
+++ b/gas/testsuite/gas/i386/optimize-1.d
@@ -10,52 +10,52 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 f5 48 55 e9    	vandnpd %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 74 48 55 e9    	vandnps %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 75 48 df e9    	vpandnd %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 f5 48 df e9    	vpandnq %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 f5 48 57 e9    	vxorpd %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 74 48 57 e9    	vxorps %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 75 48 ef e9    	vpxord %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 f5 48 ef e9    	vpxorq %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 75 48 f8 e9    	vpsubb %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 75 48 f9 e9    	vpsubw %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 75 48 fa e9    	vpsubd %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	62 f1 f5 48 fb e9    	vpsubq %zmm1,%zmm1,%zmm5
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.d b/gas/testsuite/gas/i386/x86-64-optimize-2.d
index 9222efe8c1..ba3a2df887 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 f5 48 55 f9    	vandnpd %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 f5 48 55 c1    	vandnpd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
@@ -18,7 +18,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 74 48 55 f9    	vandnps %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 74 48 55 c1    	vandnps %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
@@ -27,7 +27,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 75 48 df f9    	vpandnd %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 75 48 df c1    	vpandnd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
@@ -35,7 +35,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 f5 48 df f9    	vpandnq %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 f5 48 df c1    	vpandnq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
@@ -43,7 +43,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 f5 48 57 f9    	vxorpd %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 f5 48 57 c1    	vxorpd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
@@ -51,7 +51,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 74 48 57 f9    	vxorps %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 74 48 57 c1    	vxorps %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
@@ -60,7 +60,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 75 48 ef f9    	vpxord %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 75 48 ef c1    	vpxord %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
@@ -68,7 +68,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 f5 48 ef f9    	vpxorq %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 f5 48 ef c1    	vpxorq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
@@ -76,7 +76,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 75 48 f8 f9    	vpsubb %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 75 48 f8 c1    	vpsubb %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
@@ -84,7 +84,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 75 48 f9 f9    	vpsubw %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 75 48 f9 c1    	vpsubw %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
@@ -92,7 +92,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 75 48 fa f9    	vpsubd %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 75 48 fa c1    	vpsubd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
@@ -100,7 +100,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
- +[a-f0-9]+:	62 71 f5 48 fb f9    	vpsubq %zmm1,%zmm1,%zmm15
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 e1 f5 48 fb c1    	vpsubq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16

Patch

From b8ff5edf57f7d9c46091225fe052ea0434b491a5 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 8 Mar 2018 04:19:14 -0800
Subject: [PATCH] x86: Optimize with EVEX128 encoding for AVX512VL

We can optimize AVX512 instructions with EVEX128 only if AVX512VL is
enabled:

1. Instruction is an AVX512VL instruction. Or
2. AVX512VL is enabled explicitly by -march=+avx512vl/".arch .avx512vl".

Also we shouldn't optimize AVX512 instructions with pseudo {evex} prefix.

	* config/tc-i386.c (_i386_insn): Add pseudo_evex_prefix.
	(set_cpu_arch): Set cpu_arch_isa_flags.
	(md_parse_option): Likewise.
	(optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
	for cpuavx512vl instead of cpu_arch_flags.  Don't optimize EVEX
	if i.pseudo_evex_prefix is TRUE.
	(parse_insn): Set i.pseudo_evex_prefix for {evex}.
	* testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
	x86-64-optimize-5 and x86-64-optimize-6.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-4.d: New file.
	* testsuite/gas/i386/optimize-4.s: Likewise.
	* testsuite/gas/i386/optimize-5.d: Likewise.
	* testsuite/gas/i386/optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
---
 gas/config/tc-i386.c                       |  18 ++++-
 gas/testsuite/gas/i386/i386.exp            |   4 ++
 gas/testsuite/gas/i386/optimize-1.d        |  24 +++----
 gas/testsuite/gas/i386/optimize-4.d        |  62 ++++++++++++++++
 gas/testsuite/gas/i386/optimize-4.s        |   5 ++
 gas/testsuite/gas/i386/optimize-5.d        |  62 ++++++++++++++++
 gas/testsuite/gas/i386/optimize-5.s        |   7 ++
 gas/testsuite/gas/i386/x86-64-optimize-2.d |  72 +++++++++----------
 gas/testsuite/gas/i386/x86-64-optimize-5.d | 110 +++++++++++++++++++++++++++++
 gas/testsuite/gas/i386/x86-64-optimize-5.s |   5 ++
 gas/testsuite/gas/i386/x86-64-optimize-6.d | 110 +++++++++++++++++++++++++++++
 gas/testsuite/gas/i386/x86-64-optimize-6.s |   7 ++
 12 files changed, 436 insertions(+), 50 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/optimize-4.d
 create mode 100644 gas/testsuite/gas/i386/optimize-4.s
 create mode 100644 gas/testsuite/gas/i386/optimize-5.d
 create mode 100644 gas/testsuite/gas/i386/optimize-5.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-5.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-5.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-6.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-optimize-6.s

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 0fe6c9334e..1638023e71 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -381,6 +381,9 @@  struct _i386_insn
 	vex_encoding_evex
       } vec_encoding;
 
+    /* Pseudo {evex} prefix.  */
+    bfd_boolean pseudo_evex_prefix;
+
     /* REP prefix.  */
     const char *rep_prefix;
 
@@ -2626,6 +2629,10 @@  set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
 		  cpu_arch_flags = flags;
 		  cpu_arch_isa_flags = flags;
 		}
+	      else
+		cpu_arch_isa_flags
+		  = cpu_flags_or (cpu_arch_isa_flags,
+				  cpu_arch[j].flags);
 	      (void) restore_line_pointer (e);
 	      demand_empty_rest_of_line ();
 	      return;
@@ -3867,10 +3874,12 @@  optimize_encoding (void)
 	   && i.op[0].regs == i.op[1].regs
 	   && !i.types[2].bitfield.xmmword
 	   && (i.tm.opcode_modifier.vex
-	       || (!i.mask
+	       || (!i.pseudo_evex_prefix
+		   && !i.mask
 		   && !i.rounding
 		   && is_evex_encoding (&i.tm)
-		   && cpu_arch_flags.bitfield.cpuavx512vl))
+		   && (i.tm.cpu_flags.bitfield.cpuavx512vl
+		       || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
 	   && ((i.tm.base_opcode == 0x55
 		|| i.tm.base_opcode == 0x6655
 		|| i.tm.base_opcode == 0x66df
@@ -4363,6 +4372,7 @@  parse_insn (char *line, char *mnemonic)
 		case 0x6:
 		  /* {evex} */
 		  i.vec_encoding = vex_encoding_evex;
+		  i.pseudo_evex_prefix = TRUE;
 		  break;
 		case 0x7:
 		  /* {rex} */
@@ -10533,6 +10543,10 @@  md_parse_option (int c, const char *arg)
 		      cpu_arch_flags = flags;
 		      cpu_arch_isa_flags = flags;
 		    }
+		  else
+		    cpu_arch_isa_flags
+		      = cpu_flags_or (cpu_arch_isa_flags,
+				      cpu_arch[j].flags);
 		  break;
 		}
 	    }
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9dd2546393..fec3e51932 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -442,6 +442,8 @@  if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "optimize-1"
     run_dump_test "optimize-2"
     run_dump_test "optimize-3"
+    run_dump_test "optimize-4"
+    run_dump_test "optimize-5"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -928,6 +930,8 @@  if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-optimize-2"
     run_dump_test "x86-64-optimize-3"
     run_dump_test "x86-64-optimize-4"
+    run_dump_test "x86-64-optimize-5"
+    run_dump_test "x86-64-optimize-6"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/optimize-1.d b/gas/testsuite/gas/i386/optimize-1.d
index 3ea6e75b9a..f7da296697 100644
--- a/gas/testsuite/gas/i386/optimize-1.d
+++ b/gas/testsuite/gas/i386/optimize-1.d
@@ -10,52 +10,52 @@  Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 55 e9    	vandnpd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 48 55 e9    	vandnps %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 df e9    	vpandnd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 df e9    	vpandnq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 57 e9    	vxorpd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 48 57 e9    	vxorps %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 ef e9    	vpxord %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 ef e9    	vpxorq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 f8 e9    	vpsubb %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 f9 e9    	vpsubw %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 48 fa e9    	vpsubd %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
  +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
- +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 fb e9    	vpsubq %zmm1,%zmm1,%zmm5
  +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
 #pass
diff --git a/gas/testsuite/gas/i386/optimize-4.d b/gas/testsuite/gas/i386/optimize-4.d
new file mode 100644
index 0000000000..4169d1be45
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-4.d
@@ -0,0 +1,62 @@ 
+#as: -O2 -march=+avx512vl -I${srcdir}/$subdir
+#objdump: -drw
+#name: optimized encoding 4 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 55 e9    	vandnpd %zmm1,%zmm1,%zmm5
+#pass
diff --git a/gas/testsuite/gas/i386/optimize-4.s b/gas/testsuite/gas/i386/optimize-4.s
new file mode 100644
index 0000000000..e1bfa515c6
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-4.s
@@ -0,0 +1,5 @@ 
+# Check instructions with optimized encoding
+
+.include "optimize-1.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
diff --git a/gas/testsuite/gas/i386/optimize-5.d b/gas/testsuite/gas/i386/optimize-5.d
new file mode 100644
index 0000000000..35b7978b9e
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-5.d
@@ -0,0 +1,62 @@ 
+#as: -O2 -I${srcdir}/$subdir
+#objdump: -drw
+#name: optimized encoding 5 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 f1 f5 4f 55 e9    	vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 55 e9    	vandnpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 55 e9    	vandnps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 55 e9    	vandnps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 55 e9          	vandnps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f df e9    	vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af df e9    	vpandnd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f df e9    	vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af df e9    	vpandnq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 df e9          	vpandn %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f 57 e9    	vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af 57 e9    	vxorpd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 57 e9          	vxorpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 74 4f 57 e9    	vxorps %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 74 af 57 e9    	vxorps %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f0 57 e9          	vxorps %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f ef e9    	vpxord %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af ef e9    	vpxord %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f ef e9    	vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af ef e9    	vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 ef e9          	vpxor  %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f8 e9    	vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f8 e9    	vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f8 e9          	vpsubb %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f f9 e9    	vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af f9 e9    	vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 f9 e9          	vpsubw %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 75 4f fa e9    	vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 75 af fa e9    	vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fa e9          	vpsubd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 4f fb e9    	vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
+ +[a-f0-9]+:	62 f1 f5 af fb e9    	vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	c5 f1 fb e9          	vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 48 55 e9    	vandnpd %zmm1,%zmm1,%zmm5
+#pass
diff --git a/gas/testsuite/gas/i386/optimize-5.s b/gas/testsuite/gas/i386/optimize-5.s
new file mode 100644
index 0000000000..8e9e0f116a
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-5.s
@@ -0,0 +1,7 @@ 
+# Check instructions with optimized encoding
+
+	.arch .avx512vl
+
+.include "optimize-1.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.d b/gas/testsuite/gas/i386/x86-64-optimize-2.d
index f59e9b6808..9222efe8c1 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.d
@@ -10,100 +10,100 @@  Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 55 f9    	vandnpd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 55 c1    	vandnpd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 55 c9    	vandnpd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 74 48 55 f9    	vandnps %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 48 55 c1    	vandnps %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 40 55 c9    	vandnps %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 df f9    	vpandnd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 48 df c1    	vpandnd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 df c9    	vpandnd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 df f9    	vpandnq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 df c1    	vpandnq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 df c9    	vpandnq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 57 f9    	vxorpd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 57 c1    	vxorpd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 57 c9    	vxorpd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 74 48 57 f9    	vxorps %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 48 57 c1    	vxorps %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 40 57 c9    	vxorps %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
  +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 ef f9    	vpxord %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 ef c1    	vpxord %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 ef c9    	vpxord %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 ef f9    	vpxorq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 48 ef c1    	vpxorq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 ef c9    	vpxorq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 f8 f9    	vpsubb %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 48 f8 c1    	vpsubb %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 f8 c9    	vpsubb %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 f9 f9    	vpsubw %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 f9 c1    	vpsubw %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 f9 c9    	vpsubw %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 75 48 fa f9    	vpsubd %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 48 fa c1    	vpsubd %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 40 fa c9    	vpsubd %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
  +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	62 71 f5 48 fb f9    	vpsubq %zmm1,%zmm1,%zmm15
  +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
- +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 48 fb c1    	vpsubq %zmm1,%zmm1,%zmm16
  +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 40 fb c9    	vpsubq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.d b/gas/testsuite/gas/i386/x86-64-optimize-5.d
new file mode 100644
index 0000000000..f4590b7fd5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.d
@@ -0,0 +1,110 @@ 
+#as: -O2 -march=+avx512vl -I${srcdir}/$subdir
+#objdump: -drw
+#name: x86-64 optimized encoding 5 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 f1 f5 48 55 e9    	vandnpd %zmm1,%zmm1,%zmm5
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.s b/gas/testsuite/gas/i386/x86-64-optimize-5.s
new file mode 100644
index 0000000000..e8bd954b80
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.s
@@ -0,0 +1,5 @@ 
+# Check 64bit instructions with optimized encoding
+
+.include "x86-64-optimize-2.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.d b/gas/testsuite/gas/i386/x86-64-optimize-6.d
new file mode 100644
index 0000000000..3ab798c041
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.d
@@ -0,0 +1,110 @@ 
+#as: -O2 -I${srcdir}/$subdir
+#objdump: -drw
+#name: x86-64 optimized encoding 6 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 71 f5 4f 55 f9    	vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 55 f9    	vandnpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 55 f9          	vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 55 c1    	vandnpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 55 c9    	vandnpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 55 f9    	vandnps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 55 f9    	vandnps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 55 f9          	vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 55 c1    	vandnps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 55 c9    	vandnps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f df f9    	vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af df f9    	vpandnd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 df c1    	vpandnd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 df c9    	vpandnd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f df f9    	vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af df f9    	vpandnq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 df f9          	vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 df c1    	vpandnq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 df c9    	vpandnq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f 57 f9    	vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af 57 f9    	vxorpd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 57 f9          	vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 57 c1    	vxorpd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 57 c9    	vxorpd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 74 4f 57 f9    	vxorps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 74 af 57 f9    	vxorps %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 70 57 f9          	vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 74 08 57 c1    	vxorps %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 74 00 57 c9    	vxorps %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 71 75 4f ef f9    	vpxord %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af ef f9    	vpxord %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 ef c1    	vpxord %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 ef c9    	vpxord %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f ef f9    	vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af ef f9    	vpxorq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 ef f9          	vpxor  %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 ef c1    	vpxorq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 ef c9    	vpxorq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f8 f9    	vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f8 f9    	vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f8 f9          	vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f8 c1    	vpsubb %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f8 c9    	vpsubb %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f f9 f9    	vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af f9 f9    	vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 f9 f9          	vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 f9 c1    	vpsubw %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 f9 c9    	vpsubw %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 75 4f fa f9    	vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 75 af fa f9    	vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fa f9          	vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 75 08 fa c1    	vpsubd %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 75 00 fa c9    	vpsubd %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 71 f5 4f fb f9    	vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+:	62 71 f5 af fb f9    	vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	c5 71 fb f9          	vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 e1 f5 08 fb c1    	vpsubq %xmm1,%xmm1,%xmm16
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 b1 f5 00 fb c9    	vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:	62 f1 f5 48 55 e9    	vandnpd %zmm1,%zmm1,%zmm5
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.s b/gas/testsuite/gas/i386/x86-64-optimize-6.s
new file mode 100644
index 0000000000..0c8c743d4b
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.s
@@ -0,0 +1,7 @@ 
+# Check 64bit instructions with optimized encoding
+
+	.arch .avx512vl
+
+.include "x86-64-optimize-2.s"
+
+	{evex} vandnpd %zmm1, %zmm1, %zmm5
-- 
2.14.3