[v2,MIPS] Add machine mode to get_fcsr pattern operand

Message ID 1566546354-14448-1-git-send-email-mihailo.stojanovic@rt-rk.com
State New
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Series
  • [v2,MIPS] Add machine mode to get_fcsr pattern operand
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Commit Message

Mihailo Stojanovic Aug. 23, 2019, 7:45 a.m.
Hi,

Missing machine mode for the unspec_volatile operand of get_fcsr
patterns causes an ICE in simplify_subreg on n64 ABI.

This adds the missing machine modes and a new test.

Tested on mips64el-mti-linux-gnu.

Ok for trunk and possibly backport?

Cheers,
Mihailo

gcc/

        * config/mips/mips.md (mips_get_fcsr, *mips_get_fcsr): Use SI
        machine mode for unspec_volatile operand.
        * testsuite/gcc.target/mips/get-fcsr-3.c: New test.
---
 gcc/config/mips/mips.md                    | 4 ++--
 gcc/testsuite/gcc.target/mips/get-fcsr-3.c | 9 +++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/get-fcsr-3.c

-- 
2.7.4

Comments

Jeff Law Aug. 23, 2019, 7:11 p.m. | #1
On 8/23/19 1:45 AM, Mihailo Stojanovic wrote:
> Hi,

> 

> Missing machine mode for the unspec_volatile operand of get_fcsr

> patterns causes an ICE in simplify_subreg on n64 ABI.

> 

> This adds the missing machine modes and a new test.

> 

> Tested on mips64el-mti-linux-gnu.

> 

> Ok for trunk and possibly backport?

> 

> Cheers,

> Mihailo

> 

> gcc/

> 

>         * config/mips/mips.md (mips_get_fcsr, *mips_get_fcsr): Use SI

>         machine mode for unspec_volatile operand.

>         * testsuite/gcc.target/mips/get-fcsr-3.c: New test.

Committed to the trunk, gcc-9 and gcc-8 branches.

Thanks,
jeff
> ---

Patch

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index e17b1d5..4ad5c62 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -7588,7 +7588,7 @@ 
 ;; __builtin_mips_get_fcsr: move the FCSR into operand 0.
 (define_expand "mips_get_fcsr"
   [(set (match_operand:SI 0 "register_operand")
-  	(unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
+       (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))]
   "TARGET_HARD_FLOAT_ABI"
 {
   if (TARGET_MIPS16)
@@ -7600,7 +7600,7 @@ 
 
 (define_insn "*mips_get_fcsr"
   [(set (match_operand:SI 0 "register_operand" "=d")
-  	(unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
+       (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))]
   "TARGET_HARD_FLOAT"
   "cfc1\t%0,$31")
 
diff --git a/gcc/testsuite/gcc.target/mips/get-fcsr-3.c b/gcc/testsuite/gcc.target/mips/get-fcsr-3.c
new file mode 100644
index 0000000..7bb97b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/get-fcsr-3.c
@@ -0,0 +1,9 @@ 
+/* { dg-options "-mabi=64 -mhard-float" } */
+
+NOMIPS16 unsigned int
+foo (void)
+{
+  return __builtin_mips_get_fcsr () & 0x1;
+}
+
+/* { dg-final { scan-assembler "cfc1" } } */