[AArch64,gas] Update MTE system register encodings

Message ID 433543fa-2434-b057-9d8e-6235ab9b8c52@foss.arm.com
State New
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  • [AArch64,gas] Update MTE system register encodings
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Commit Message

Kyrill Tkachov Aug. 21, 2019, 4:42 p.m.
Hi all,

The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, 
TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers.
This patch brings binutils up to date.

The references for the encodings are at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 
(also contains TFSR_EL12 description)
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3

Tested check-gas for aarch64-none-elf.

Ok for master and the 2.32 branch?

Thanks,
Kyrill

opcodes/
2019-08-21  Kyrylo Tkachov <kyrylo.tkachov@arm.com>

     * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
     tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
     (aarch64_sys_reg_supported_p): Update checks for the above.

gas/
2019-08-21  Kyrylo Tkachov <kyrylo.tkachov@arm.com>

     * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for
     tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.

Comments

Nick Clifton Aug. 22, 2019, 8:39 a.m. | #1
Hi Kyrill,

> Ok for master and the 2.32 branch?


Approved for both.  Please apply.

Cheers
  Nick

> opcodes/

> 2019-08-21  Kyrylo Tkachov <kyrylo.tkachov@arm.com>

> 

>     * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,

>     tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.

>     (aarch64_sys_reg_supported_p): Update checks for the above.

> 

> gas/

> 2019-08-21  Kyrylo Tkachov <kyrylo.tkachov@arm.com>

> 

>     * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for

>     tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.

>

Patch

diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d
index bc3d0bdb7f5d497f1d0729b50f95446184cbb359..c25536d6ca5a7e882df29951d698ec861cfb13bb 100644
--- a/gas/testsuite/gas/aarch64/sysreg-4.d
+++ b/gas/testsuite/gas/aarch64/sysreg-4.d
@@ -21,21 +21,21 @@  Disassembly of section \.text:
 .*:	d5380388 	mrs	x8, id_pfr2_el1
 .*:	d53b42e1 	mrs	x1, tco
 .*:	d53b42e2 	mrs	x2, tco
-.*:	d5386621 	mrs	x1, tfsre0_el1
-.*:	d5386501 	mrs	x1, tfsr_el1
-.*:	d53c6502 	mrs	x2, tfsr_el2
-.*:	d53e6603 	mrs	x3, tfsr_el3
-.*:	d53d660c 	mrs	x12, tfsr_el12
+.*:	d5385621 	mrs	x1, tfsre0_el1
+.*:	d5385601 	mrs	x1, tfsr_el1
+.*:	d53c5602 	mrs	x2, tfsr_el2
+.*:	d53e5603 	mrs	x3, tfsr_el3
+.*:	d53d560c 	mrs	x12, tfsr_el12
 .*:	d53810a1 	mrs	x1, rgsr_el1
 .*:	d53810c3 	mrs	x3, gcr_el1
 .*:	d5390084 	mrs	x4, gmid_el1
 .*:	d51b42e1 	msr	tco, x1
 .*:	d51b42e2 	msr	tco, x2
-.*:	d5186621 	msr	tfsre0_el1, x1
-.*:	d5186501 	msr	tfsr_el1, x1
-.*:	d51c6502 	msr	tfsr_el2, x2
-.*:	d51e6603 	msr	tfsr_el3, x3
-.*:	d51d660c 	msr	tfsr_el12, x12
+.*:	d5185621 	msr	tfsre0_el1, x1
+.*:	d5185601 	msr	tfsr_el1, x1
+.*:	d51c5602 	msr	tfsr_el2, x2
+.*:	d51e5603 	msr	tfsr_el3, x3
+.*:	d51d560c 	msr	tfsr_el12, x12
 .*:	d51810a1 	msr	rgsr_el1, x1
 .*:	d51810c3 	msr	gcr_el1, x3
 .*:	d503489f 	msr	tco, #0x8
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a0085698181ae072a5a28e45afda44915ae6ae3f..2e205e56a66f1c60c565e12e257f2f2a8b5b8cdb 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3966,11 +3966,11 @@  const aarch64_sys_reg aarch64_sys_regs [] =
   { "rndr",		CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
   { "rndrrs",		CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
   { "tco",		CPENC(3,3,C4,C2,7), F_ARCHEXT },
-  { "tfsre0_el1",	CPENC(3,0,C6,C6,1), F_ARCHEXT },
-  { "tfsr_el1",		CPENC(3,0,C6,C5,0), F_ARCHEXT },
-  { "tfsr_el2",		CPENC(3,4,C6,C5,0), F_ARCHEXT },
-  { "tfsr_el3",		CPENC(3,6,C6,C6,0), F_ARCHEXT },
-  { "tfsr_el12",	CPENC(3,5,C6,C6,0), F_ARCHEXT },
+  { "tfsre0_el1",	CPENC(3,0,C5,C6,1), F_ARCHEXT },
+  { "tfsr_el1",		CPENC(3,0,C5,C6,0), F_ARCHEXT },
+  { "tfsr_el2",		CPENC(3,4,C5,C6,0), F_ARCHEXT },
+  { "tfsr_el3",		CPENC(3,6,C5,C6,0), F_ARCHEXT },
+  { "tfsr_el12",	CPENC(3,5,C5,C6,0), F_ARCHEXT },
   { "rgsr_el1",		CPENC(3,0,C1,C0,5), F_ARCHEXT },
   { "gcr_el1",		CPENC(3,0,C1,C0,6), F_ARCHEXT },
   { "gmid_el1",		CPENC(3,1,C0,C0,4), F_ARCHEXT | F_REG_READ }, /* RO */
@@ -4439,11 +4439,11 @@  aarch64_sys_reg_supported_p (const aarch64_feature_set features,
 
   /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG.  */
   if ((reg->value == CPENC (3, 3, C4, C2, 7)
-       || reg->value == CPENC (3, 0, C6, C6, 1)
-       || reg->value == CPENC (3, 0, C6, C5, 0)
-       || reg->value == CPENC (3, 4, C6, C5, 0)
-       || reg->value == CPENC (3, 6, C6, C6, 0)
-       || reg->value == CPENC (3, 5, C6, C6, 0)
+       || reg->value == CPENC (3, 0, C5, C6, 1)
+       || reg->value == CPENC (3, 0, C5, C6, 0)
+       || reg->value == CPENC (3, 4, C5, C6, 0)
+       || reg->value == CPENC (3, 6, C5, C6, 0)
+       || reg->value == CPENC (3, 5, C5, C6, 0)
        || reg->value == CPENC (3, 0, C1, C0, 5)
        || reg->value == CPENC (3, 0, C1, C0, 6)
        || reg->value == CPENC (3, 1, C0, C0, 4))