[06/10] x86: improve handling of insns with ambiguous operand sizes

Message ID e5f4f194-fe71-e6dd-a268-38607a812d95@suse.com
State Superseded
Headers show
Series
  • x86: operand size handling improvements
Related show

Commit Message

Jan Beulich Aug. 6, 2019, 2:27 p.m.
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).

While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.

No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. The set of
"DefaultSize" one gets slightly widened for the purposes here.

As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid emitting of ambiguous operands (and hence triggering of the new
warning).

Note that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.

gas/
2019-08-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (process_suffix): Extend exclusion set for
	"defaultsize" processing. Re-write lack-of-suffix processing
	logic.
	* testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
	testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
	testsuite/gas/i386/x86-64-avx-scalar.s,
	testsuite/gas/i386/x86-64-avx.s,
	testsuite/gas/i386/x86-64-bundle.s,
	testsuite/gas/i386/x86-64-lock-1.s,
	testsuite/gas/i386/x86-64-opcode.s,
	testsuite/gas/i386/x86-64-sse2avx.s,
	testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
	* testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
	testsuite/gas/i386/x86-64-nops.s,
	testsuite/gas/i386/x86-64-ptwrite.s,
	testsuite/gas/i386/x86-64-simd.s,
	testsuite/gas/i386/x86-64-sse-noavx.s Drop bogus suffix-less
	insns.
	* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
	testsuite/gas/i386/noreg64.s: Add further tests.
	* testsuite/gas/i386/ilp32/x86-64-nops.d,
	testsuite/gas/i386/ilp32/x86-64-sse-noavx.d,
	testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
	testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
	testsuite/gas/i386/sse-noavx.d,
	testsuite/gas/i386/x86-64-nops.d,
	testsuite/gas/i386/x86-64-ptwrite-intel.d,
	testsuite/gas/i386/x86-64-ptwrite.d,
	testsuite/gas/i386/x86-64-simd-intel.d,
	testsuite/gas/i386/x86-64-simd-suffix.d,
	testsuite/gas/i386/x86-64-simd.d,
	testsuite/gas/i386/x86-64-sse-noavx.d: Adjust expectations.
	* testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
	testsuite/gas/i386/noreg64.l: New.
	* testsuite/gas/i386/i386.exp: Run new tests.

opcodes/
2019-08-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (jmp, ljmp): Add DefaultSize to indirect forms.
	(loop, loopz, loope, loopnz, loopne, lgdt, lidt, sgdt, sidt):
	Add DefaultSize.
	* i386-tbl.h: Re-generate.

Comments

H.J. Lu Aug. 6, 2019, 8:26 p.m. | #1
On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> Commit b76bc5d54e ("x86: don't default variable shift count insns to

> 8-bit operand size") pointed out a very bad case, but the underlying

> problem is, as mentioned on various occasions, much larger: Silently

> selecting a (nowhere documented afaict) certain default operand size

> when there's no "sizing" suffix and no suitable register operand(s) is

> simply dangerous (for the programmer to make mistakes).


If there may be an ambiguity, a size suffix can be used.  Assembler isn't
responsible for programmer's errors.

> While in Intel syntax mode such mistakes already lead to an error (which

> is going to remain that way), AT&T syntax mode now gains warnings in

> such cases by default, which can be suppressed or promoted to an error


This punishes the perfectly good assembly sources.

> if so desired by the programmer. Furthermore at least general purpose

> insns now consistently have a default applied (alongside the warning

> emission), rather than accepting some and refusing others.

>

> No warnings are (as before) to be generated for "DefaultSize" insns as

> well as ones acting on selector and other fixed-width values. The set of

> "DefaultSize" one gets slightly widened for the purposes here.


Widen the default size set avoids generate warnings.  It sounds to
me these warnings isn't really necessary.

> As set forth as a prereq when I first mentioned this intended change a

> few years back, Linux as well as gcc have meanwhile been patched to

> avoid emitting of ambiguous operands (and hence triggering of the new

> warning).

>

> Note that floating point operations with integer operands are an

> exception for now: They continue to use short (16-bit) operands by

> default even in 32- and 64-bit modes.

>

> gas/

> 2019-08-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * config/tc-i386.c (process_suffix): Extend exclusion set for

>         "defaultsize" processing. Re-write lack-of-suffix processing

>         logic.

>         * testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,

>         testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,

>         testsuite/gas/i386/x86-64-avx-scalar.s,

>         testsuite/gas/i386/x86-64-avx.s,

>         testsuite/gas/i386/x86-64-bundle.s,

>         testsuite/gas/i386/x86-64-lock-1.s,

>         testsuite/gas/i386/x86-64-opcode.s,

>         testsuite/gas/i386/x86-64-sse2avx.s,

>         testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.

>         * testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,

>         testsuite/gas/i386/x86-64-nops.s,

>         testsuite/gas/i386/x86-64-ptwrite.s,

>         testsuite/gas/i386/x86-64-simd.s,

>         testsuite/gas/i386/x86-64-sse-noavx.s Drop bogus suffix-less

>         insns.

>         * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,

>         testsuite/gas/i386/noreg64.s: Add further tests.

>         * testsuite/gas/i386/ilp32/x86-64-nops.d,

>         testsuite/gas/i386/ilp32/x86-64-sse-noavx.d,

>         testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,

>         testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,

>         testsuite/gas/i386/sse-noavx.d,

>         testsuite/gas/i386/x86-64-nops.d,

>         testsuite/gas/i386/x86-64-ptwrite-intel.d,

>         testsuite/gas/i386/x86-64-ptwrite.d,

>         testsuite/gas/i386/x86-64-simd-intel.d,

>         testsuite/gas/i386/x86-64-simd-suffix.d,

>         testsuite/gas/i386/x86-64-simd.d,

>         testsuite/gas/i386/x86-64-sse-noavx.d: Adjust expectations.

>         * testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,

>         testsuite/gas/i386/noreg64.l: New.

>         * testsuite/gas/i386/i386.exp: Run new tests.

>

> opcodes/

> 2019-08-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-opc.tbl (jmp, ljmp): Add DefaultSize to indirect forms.

>         (loop, loopz, loope, loopnz, loopne, lgdt, lidt, sgdt, sidt):

>         Add DefaultSize.

>         * i386-tbl.h: Re-generate.

>


-- 
H.J.
H.J. Lu Aug. 6, 2019, 9:38 p.m. | #2
On Tue, Aug 6, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:

> >

> > Commit b76bc5d54e ("x86: don't default variable shift count insns to

> > 8-bit operand size") pointed out a very bad case, but the underlying

> > problem is, as mentioned on various occasions, much larger: Silently

> > selecting a (nowhere documented afaict) certain default operand size

> > when there's no "sizing" suffix and no suitable register operand(s) is

> > simply dangerous (for the programmer to make mistakes).

>

> If there may be an ambiguity, a size suffix can be used.  Assembler isn't

> responsible for programmer's errors.

>

> > While in Intel syntax mode such mistakes already lead to an error (which

> > is going to remain that way), AT&T syntax mode now gains warnings in

> > such cases by default, which can be suppressed or promoted to an error

>

> This punishes the perfectly good assembly sources.

>

> > if so desired by the programmer. Furthermore at least general purpose

> > insns now consistently have a default applied (alongside the warning

> > emission), rather than accepting some and refusing others.

> >

> > No warnings are (as before) to be generated for "DefaultSize" insns as

> > well as ones acting on selector and other fixed-width values. The set of

> > "DefaultSize" one gets slightly widened for the purposes here.

>

> Widen the default size set avoids generate warnings.  It sounds to

> me these warnings isn't really necessary.

>

> > As set forth as a prereq when I first mentioned this intended change a

> > few years back, Linux as well as gcc have meanwhile been patched to

> > avoid emitting of ambiguous operands (and hence triggering of the new

> > warning).

> >

> > Note that floating point operations with integer operands are an

> > exception for now: They continue to use short (16-bit) operands by

> > default even in 32- and 64-bit modes.

> >


Instruction suffix has been an issue with AT&T syntax.  But improvements
shouldn't assemble current working assembly sources cleanly.  It is reasonable
to require that programmers should know what they are doing.  We should

1.  Require suffix if there may be ambiguity.
2.  Generate a warning if needed under a new option, (-mambiguity-check=?).
3.  Document the default operand size for AT&T syntax if there may be ambiguity.

-- 
H.J.
Jan Beulich Aug. 7, 2019, 8:11 a.m. | #3
On 06.08.2019 22:26,  H.J. Lu  wrote:
> On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> Commit b76bc5d54e ("x86: don't default variable shift count insns to

>> 8-bit operand size") pointed out a very bad case, but the underlying

>> problem is, as mentioned on various occasions, much larger: Silently

>> selecting a (nowhere documented afaict) certain default operand size

>> when there's no "sizing" suffix and no suitable register operand(s) is

>> simply dangerous (for the programmer to make mistakes).

> 

> If there may be an ambiguity, a size suffix can be used.  Assembler isn't

> responsible for programmer's errors.


But it should, as far as possible, aid him. Even more so when such
aid so far has been there in some cases, but not in others.

>> While in Intel syntax mode such mistakes already lead to an error (which

>> is going to remain that way), AT&T syntax mode now gains warnings in

>> such cases by default, which can be suppressed or promoted to an error

> 

> This punishes the perfectly good assembly sources.


What is "perfectly good" here? The lack of a disambiguating suffix is
is definitely not "perfectly good".

Furthermore - if you really mean to object to warnings in such cases,
then you should have said so when I first announced the plan for this
change. All you demanded back then was that gcc and Linux be adjusted
up front to not trigger any such new warnings (and you had offered to
take care of glibc yourself).

>> if so desired by the programmer. Furthermore at least general purpose

>> insns now consistently have a default applied (alongside the warning

>> emission), rather than accepting some and refusing others.

>>

>> No warnings are (as before) to be generated for "DefaultSize" insns as

>> well as ones acting on selector and other fixed-width values. The set of

>> "DefaultSize" one gets slightly widened for the purposes here.

> 

> Widen the default size set avoids generate warnings.  It sounds to

> me these warnings isn't really necessary.


I'm afraid I don't understand this reply of yours. As per the original
discussion a few years back the warnings are to be introduced, and
hence they want to be suppressed in sufficiently unambiguous cases
(like the branches getting DefaultSize added here, or the MOVSX/MOVSX
insns with 16-bit destinations in the later patch).

Jan
Jan Beulich Aug. 7, 2019, 8:27 a.m. | #4
On 06.08.2019 23:38,  H.J. Lu  wrote:
> On Tue, Aug 6, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:

>>

>> On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:

>>>

>>> Commit b76bc5d54e ("x86: don't default variable shift count insns to

>>> 8-bit operand size") pointed out a very bad case, but the underlying

>>> problem is, as mentioned on various occasions, much larger: Silently

>>> selecting a (nowhere documented afaict) certain default operand size

>>> when there's no "sizing" suffix and no suitable register operand(s) is

>>> simply dangerous (for the programmer to make mistakes).

>>

>> If there may be an ambiguity, a size suffix can be used.  Assembler isn't

>> responsible for programmer's errors.

>>

>>> While in Intel syntax mode such mistakes already lead to an error (which

>>> is going to remain that way), AT&T syntax mode now gains warnings in

>>> such cases by default, which can be suppressed or promoted to an error

>>

>> This punishes the perfectly good assembly sources.

>>

>>> if so desired by the programmer. Furthermore at least general purpose

>>> insns now consistently have a default applied (alongside the warning

>>> emission), rather than accepting some and refusing others.

>>>

>>> No warnings are (as before) to be generated for "DefaultSize" insns as

>>> well as ones acting on selector and other fixed-width values. The set of

>>> "DefaultSize" one gets slightly widened for the purposes here.

>>

>> Widen the default size set avoids generate warnings.  It sounds to

>> me these warnings isn't really necessary.

>>

>>> As set forth as a prereq when I first mentioned this intended change a

>>> few years back, Linux as well as gcc have meanwhile been patched to

>>> avoid emitting of ambiguous operands (and hence triggering of the new

>>> warning).

>>>

>>> Note that floating point operations with integer operands are an

>>> exception for now: They continue to use short (16-bit) operands by

>>> default even in 32- and 64-bit modes.

>>>

> 

> Instruction suffix has been an issue with AT&T syntax.  But improvements

> shouldn't assemble current working assembly sources cleanly.


I guess you mean "should", not "shouldn't"? And "cleanly" to me does
not imply without warnings, just without change to generated code
(unless the generated code was outright wrong). Pointing out possible
issues should not be restricted to cases that didn't assemble without
error so far. Or else this would be one more argument against e.g.
your recent "REP;" handling adjustment.

>  It is reasonable

> to require that programmers should know what they are doing.  We should

> 

> 1.  Require suffix if there may be ambiguity.


This would actively break existing code (reading "require" as "emit an
error if it is missing"). After all it's the present _inconsistency_
in behavior that this series tries to address.

> 2.  Generate a warning if needed under a new option, (-mambiguity-check=?).


First of all this contradicts 1 above: There's no point generating a
warning when we also generate an error. As to a separate option - if
you really don't want me to re-use the existing one (which is a pretty
good fit), I can certainly key this to a new one. But the default will
remain to be for the warning to be enabled.

> 3.  Document the default operand size for AT&T syntax if there may be ambiguity.


Will do.

Jan
H.J. Lu Aug. 7, 2019, 11:58 p.m. | #5
On Wed, Aug 7, 2019 at 1:27 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 06.08.2019 23:38,  H.J. Lu  wrote:

> > On Tue, Aug 6, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> >>

> >> On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>>

> >>> Commit b76bc5d54e ("x86: don't default variable shift count insns to

> >>> 8-bit operand size") pointed out a very bad case, but the underlying

> >>> problem is, as mentioned on various occasions, much larger: Silently

> >>> selecting a (nowhere documented afaict) certain default operand size

> >>> when there's no "sizing" suffix and no suitable register operand(s) is

> >>> simply dangerous (for the programmer to make mistakes).

> >>

> >> If there may be an ambiguity, a size suffix can be used.  Assembler isn't

> >> responsible for programmer's errors.

> >>

> >>> While in Intel syntax mode such mistakes already lead to an error (which

> >>> is going to remain that way), AT&T syntax mode now gains warnings in

> >>> such cases by default, which can be suppressed or promoted to an error

> >>

> >> This punishes the perfectly good assembly sources.

> >>

> >>> if so desired by the programmer. Furthermore at least general purpose

> >>> insns now consistently have a default applied (alongside the warning

> >>> emission), rather than accepting some and refusing others.

> >>>

> >>> No warnings are (as before) to be generated for "DefaultSize" insns as

> >>> well as ones acting on selector and other fixed-width values. The set of

> >>> "DefaultSize" one gets slightly widened for the purposes here.

> >>

> >> Widen the default size set avoids generate warnings.  It sounds to

> >> me these warnings isn't really necessary.

> >>

> >>> As set forth as a prereq when I first mentioned this intended change a

> >>> few years back, Linux as well as gcc have meanwhile been patched to

> >>> avoid emitting of ambiguous operands (and hence triggering of the new

> >>> warning).

> >>>

> >>> Note that floating point operations with integer operands are an

> >>> exception for now: They continue to use short (16-bit) operands by

> >>> default even in 32- and 64-bit modes.

> >>>

> >

> > Instruction suffix has been an issue with AT&T syntax.  But improvements

> > shouldn't assemble current working assembly sources cleanly.

>

> I guess you mean "should", not "shouldn't"? And "cleanly" to me does

> not imply without warnings, just without change to generated code

> (unless the generated code was outright wrong). Pointing out possible

> issues should not be restricted to cases that didn't assemble without

> error so far. Or else this would be one more argument against e.g.

> your recent "REP;" handling adjustment.

>

> >  It is reasonable

> > to require that programmers should know what they are doing.  We should

> >

> > 1.  Require suffix if there may be ambiguity.

>

> This would actively break existing code (reading "require" as "emit an

> error if it is missing"). After all it's the present _inconsistency_

> in behavior that this series tries to address.

>

> > 2.  Generate a warning if needed under a new option, (-mambiguity-check=?).

>

> First of all this contradicts 1 above: There's no point generating a

> warning when we also generate an error. As to a separate option - if

> you really don't want me to re-use the existing one (which is a pretty

> good fit), I can certainly key this to a new one. But the default will

> remain to be for the warning to be enabled.

>

> > 3.  Document the default operand size for AT&T syntax if there may be ambiguity.

>

> Will do.

>


Since AT&T syntax has no size info on memory operand, we can't tell memory
size when mnemonic supports more than one memory size.   Currently AT&T
syntax adds suffix to distinguish different memory sizes for these instructions.
For some instructions, there is a default memory size when there is no suffix.
In this sense, there is no ambiguity for assembler.   The only issue is that it
isn't easy for programmer to tell what the default memory size is.

To help programmers with these ambiguities when there is no suffix, we can

1. Document these ambiguities.
2. Issue warning when there is an exception in rules.   Warning should
be kept as few as possible.   For most parts, the default size is 32-bit.

add     $1, (%bx)

shouldn't generate a warning since the destination is 32-bit.  We can add
a pseudo prefix {imm32} to request 32-bit immediate operand.

--
H.J.
Jan Beulich Aug. 8, 2019, 7:54 a.m. | #6
On 08.08.2019 01:58,  H.J. Lu  wrote:
> On Wed, Aug 7, 2019 at 1:27 AM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> On 06.08.2019 23:38,  H.J. Lu  wrote:

>>> On Tue, Aug 6, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:

>>>>

>>>> On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:

>>>>>

>>>>> Commit b76bc5d54e ("x86: don't default variable shift count insns to

>>>>> 8-bit operand size") pointed out a very bad case, but the underlying

>>>>> problem is, as mentioned on various occasions, much larger: Silently

>>>>> selecting a (nowhere documented afaict) certain default operand size

>>>>> when there's no "sizing" suffix and no suitable register operand(s) is

>>>>> simply dangerous (for the programmer to make mistakes).

>>>>

>>>> If there may be an ambiguity, a size suffix can be used.  Assembler isn't

>>>> responsible for programmer's errors.

>>>>

>>>>> While in Intel syntax mode such mistakes already lead to an error (which

>>>>> is going to remain that way), AT&T syntax mode now gains warnings in

>>>>> such cases by default, which can be suppressed or promoted to an error

>>>>

>>>> This punishes the perfectly good assembly sources.

>>>>

>>>>> if so desired by the programmer. Furthermore at least general purpose

>>>>> insns now consistently have a default applied (alongside the warning

>>>>> emission), rather than accepting some and refusing others.

>>>>>

>>>>> No warnings are (as before) to be generated for "DefaultSize" insns as

>>>>> well as ones acting on selector and other fixed-width values. The set of

>>>>> "DefaultSize" one gets slightly widened for the purposes here.

>>>>

>>>> Widen the default size set avoids generate warnings.  It sounds to

>>>> me these warnings isn't really necessary.

>>>>

>>>>> As set forth as a prereq when I first mentioned this intended change a

>>>>> few years back, Linux as well as gcc have meanwhile been patched to

>>>>> avoid emitting of ambiguous operands (and hence triggering of the new

>>>>> warning).

>>>>>

>>>>> Note that floating point operations with integer operands are an

>>>>> exception for now: They continue to use short (16-bit) operands by

>>>>> default even in 32- and 64-bit modes.

>>>>>

>>>

>>> Instruction suffix has been an issue with AT&T syntax.  But improvements

>>> shouldn't assemble current working assembly sources cleanly.

>>

>> I guess you mean "should", not "shouldn't"? And "cleanly" to me does

>> not imply without warnings, just without change to generated code

>> (unless the generated code was outright wrong). Pointing out possible

>> issues should not be restricted to cases that didn't assemble without

>> error so far. Or else this would be one more argument against e.g.

>> your recent "REP;" handling adjustment.

>>

>>>   It is reasonable

>>> to require that programmers should know what they are doing.  We should

>>>

>>> 1.  Require suffix if there may be ambiguity.

>>

>> This would actively break existing code (reading "require" as "emit an

>> error if it is missing"). After all it's the present _inconsistency_

>> in behavior that this series tries to address.

>>

>>> 2.  Generate a warning if needed under a new option, (-mambiguity-check=?).

>>

>> First of all this contradicts 1 above: There's no point generating a

>> warning when we also generate an error. As to a separate option - if

>> you really don't want me to re-use the existing one (which is a pretty

>> good fit), I can certainly key this to a new one. But the default will

>> remain to be for the warning to be enabled.

>>

>>> 3.  Document the default operand size for AT&T syntax if there may be ambiguity.

>>

>> Will do.

>>

> 

> Since AT&T syntax has no size info on memory operand, we can't tell memory

> size when mnemonic supports more than one memory size.   Currently AT&T

> syntax adds suffix to distinguish different memory sizes for these instructions.

> For some instructions, there is a default memory size when there is no suffix.

> In this sense, there is no ambiguity for assembler.   The only issue is that it

> isn't easy for programmer to tell what the default memory size is.

> 

> To help programmers with these ambiguities when there is no suffix, we can

> 

> 1. Document these ambiguities.

> 2. Issue warning when there is an exception in rules.   Warning should

> be kept as few as possible.   For most parts, the default size is 32-bit.


"For most parts" is already telling enough, I think. Recall how

	shl	%cl, (%eax)

used to be wrongly deriving byte memory operand size from the
shift count register used? If things had been working flawlessly
so far, I'd maybe agree that there's no need for warnings by
default. But seeing how inconsistent _and broken_ things have
been, this is simply not an option.

> add     $1, (%bx)

> 

> shouldn't generate a warning since the destination is 32-bit.


Good example (but of course I don't agree with the "no warning"
statement). Why is it then that

	add	$0x89, (%eax)
	add	$0x12345678, (%eax)

fail to assemble without the patch applied? Once again - may I
ask that you look at the additions to noreg*.s that this and
the subsequent patches do? These are all cases not working
currently, but which should work (and according to you even
without warning), and which this series makes work.

>  We can add

> a pseudo prefix {imm32} to request 32-bit immediate operand.


I don't see how this relates here.

Jan
H.J. Lu Aug. 8, 2019, 4:19 p.m. | #7
On Thu, Aug 8, 2019 at 12:56 AM Jan Beulich <JBeulich@suse.com> wrote:
>

> On 08.08.2019 01:58,  H.J. Lu  wrote:

> > On Wed, Aug 7, 2019 at 1:27 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>

> >> On 06.08.2019 23:38,  H.J. Lu  wrote:

> >>> On Tue, Aug 6, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> >>>>

> >>>> On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>>>>

> >>>>> Commit b76bc5d54e ("x86: don't default variable shift count insns to

> >>>>> 8-bit operand size") pointed out a very bad case, but the underlying

> >>>>> problem is, as mentioned on various occasions, much larger: Silently

> >>>>> selecting a (nowhere documented afaict) certain default operand size

> >>>>> when there's no "sizing" suffix and no suitable register operand(s) is

> >>>>> simply dangerous (for the programmer to make mistakes).

> >>>>

> >>>> If there may be an ambiguity, a size suffix can be used.  Assembler isn't

> >>>> responsible for programmer's errors.

> >>>>

> >>>>> While in Intel syntax mode such mistakes already lead to an error (which

> >>>>> is going to remain that way), AT&T syntax mode now gains warnings in

> >>>>> such cases by default, which can be suppressed or promoted to an error

> >>>>

> >>>> This punishes the perfectly good assembly sources.

> >>>>

> >>>>> if so desired by the programmer. Furthermore at least general purpose

> >>>>> insns now consistently have a default applied (alongside the warning

> >>>>> emission), rather than accepting some and refusing others.

> >>>>>

> >>>>> No warnings are (as before) to be generated for "DefaultSize" insns as

> >>>>> well as ones acting on selector and other fixed-width values. The set of

> >>>>> "DefaultSize" one gets slightly widened for the purposes here.

> >>>>

> >>>> Widen the default size set avoids generate warnings.  It sounds to

> >>>> me these warnings isn't really necessary.

> >>>>

> >>>>> As set forth as a prereq when I first mentioned this intended change a

> >>>>> few years back, Linux as well as gcc have meanwhile been patched to

> >>>>> avoid emitting of ambiguous operands (and hence triggering of the new

> >>>>> warning).

> >>>>>

> >>>>> Note that floating point operations with integer operands are an

> >>>>> exception for now: They continue to use short (16-bit) operands by

> >>>>> default even in 32- and 64-bit modes.

> >>>>>

> >>>

> >>> Instruction suffix has been an issue with AT&T syntax.  But improvements

> >>> shouldn't assemble current working assembly sources cleanly.

> >>

> >> I guess you mean "should", not "shouldn't"? And "cleanly" to me does

> >> not imply without warnings, just without change to generated code

> >> (unless the generated code was outright wrong). Pointing out possible

> >> issues should not be restricted to cases that didn't assemble without

> >> error so far. Or else this would be one more argument against e.g.

> >> your recent "REP;" handling adjustment.

> >>

> >>>   It is reasonable

> >>> to require that programmers should know what they are doing.  We should

> >>>

> >>> 1.  Require suffix if there may be ambiguity.

> >>

> >> This would actively break existing code (reading "require" as "emit an

> >> error if it is missing"). After all it's the present _inconsistency_

> >> in behavior that this series tries to address.

> >>

> >>> 2.  Generate a warning if needed under a new option, (-mambiguity-check=?).

> >>

> >> First of all this contradicts 1 above: There's no point generating a

> >> warning when we also generate an error. As to a separate option - if

> >> you really don't want me to re-use the existing one (which is a pretty

> >> good fit), I can certainly key this to a new one. But the default will

> >> remain to be for the warning to be enabled.

> >>

> >>> 3.  Document the default operand size for AT&T syntax if there may be ambiguity.

> >>

> >> Will do.

> >>

> >

> > Since AT&T syntax has no size info on memory operand, we can't tell memory

> > size when mnemonic supports more than one memory size.   Currently AT&T

> > syntax adds suffix to distinguish different memory sizes for these instructions.

> > For some instructions, there is a default memory size when there is no suffix.

> > In this sense, there is no ambiguity for assembler.   The only issue is that it

> > isn't easy for programmer to tell what the default memory size is.

> >

> > To help programmers with these ambiguities when there is no suffix, we can

> >

> > 1. Document these ambiguities.

> > 2. Issue warning when there is an exception in rules.   Warning should

> > be kept as few as possible.   For most parts, the default size is 32-bit.

>

> "For most parts" is already telling enough, I think. Recall how

>

>         shl     %cl, (%eax)

>

> used to be wrongly deriving byte memory operand size from the

> shift count register used? If things had been working flawlessly

> so far, I'd maybe agree that there's no need for warnings by

> default. But seeing how inconsistent _and broken_ things have

> been, this is simply not an option.

>

> > add     $1, (%bx)

> >

> > shouldn't generate a warning since the destination is 32-bit.

>

> Good example (but of course I don't agree with the "no warning"

> statement). Why is it then that

>

>         add     $0x89, (%eax)

>         add     $0x12345678, (%eax)

>

> fail to assemble without the patch applied? Once again - may I

> ask that you look at the additions to noreg*.s that this and

> the subsequent patches do? These are all cases not working

> currently, but which should work (and according to you even

> without warning), and which this series makes work.


Given that in AT&T syntax needs the suffix for memory operand size,
we should document existing quirks and shouldn't accept more
instructions without suffix.

> >  We can add

> > a pseudo prefix {imm32} to request 32-bit immediate operand.

>

> I don't see how this relates here.

>


We can encode

{imm32} addl   $0x70,(%rax)

with 32-bit immediate.

-- 
H.J.
Jan Beulich Aug. 9, 2019, 7:50 a.m. | #8
On 08.08.2019 18:19,  H.J. Lu  wrote:
> On Thu, Aug 8, 2019 at 12:56 AM Jan Beulich <JBeulich@suse.com> wrote:

>>

>> On 08.08.2019 01:58,  H.J. Lu  wrote:

>>> On Wed, Aug 7, 2019 at 1:27 AM Jan Beulich <jbeulich@suse.com> wrote:

>>>>

>>>> On 06.08.2019 23:38,  H.J. Lu  wrote:

>>>>> On Tue, Aug 6, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:

>>>>>>

>>>>>> On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:

>>>>>>>

>>>>>>> Commit b76bc5d54e ("x86: don't default variable shift count insns to

>>>>>>> 8-bit operand size") pointed out a very bad case, but the underlying

>>>>>>> problem is, as mentioned on various occasions, much larger: Silently

>>>>>>> selecting a (nowhere documented afaict) certain default operand size

>>>>>>> when there's no "sizing" suffix and no suitable register operand(s) is

>>>>>>> simply dangerous (for the programmer to make mistakes).

>>>>>>

>>>>>> If there may be an ambiguity, a size suffix can be used.  Assembler isn't

>>>>>> responsible for programmer's errors.

>>>>>>

>>>>>>> While in Intel syntax mode such mistakes already lead to an error (which

>>>>>>> is going to remain that way), AT&T syntax mode now gains warnings in

>>>>>>> such cases by default, which can be suppressed or promoted to an error

>>>>>>

>>>>>> This punishes the perfectly good assembly sources.

>>>>>>

>>>>>>> if so desired by the programmer. Furthermore at least general purpose

>>>>>>> insns now consistently have a default applied (alongside the warning

>>>>>>> emission), rather than accepting some and refusing others.

>>>>>>>

>>>>>>> No warnings are (as before) to be generated for "DefaultSize" insns as

>>>>>>> well as ones acting on selector and other fixed-width values. The set of

>>>>>>> "DefaultSize" one gets slightly widened for the purposes here.

>>>>>>

>>>>>> Widen the default size set avoids generate warnings.  It sounds to

>>>>>> me these warnings isn't really necessary.

>>>>>>

>>>>>>> As set forth as a prereq when I first mentioned this intended change a

>>>>>>> few years back, Linux as well as gcc have meanwhile been patched to

>>>>>>> avoid emitting of ambiguous operands (and hence triggering of the new

>>>>>>> warning).

>>>>>>>

>>>>>>> Note that floating point operations with integer operands are an

>>>>>>> exception for now: They continue to use short (16-bit) operands by

>>>>>>> default even in 32- and 64-bit modes.

>>>>>>>

>>>>>

>>>>> Instruction suffix has been an issue with AT&T syntax.  But improvements

>>>>> shouldn't assemble current working assembly sources cleanly.

>>>>

>>>> I guess you mean "should", not "shouldn't"? And "cleanly" to me does

>>>> not imply without warnings, just without change to generated code

>>>> (unless the generated code was outright wrong). Pointing out possible

>>>> issues should not be restricted to cases that didn't assemble without

>>>> error so far. Or else this would be one more argument against e.g.

>>>> your recent "REP;" handling adjustment.

>>>>

>>>>>    It is reasonable

>>>>> to require that programmers should know what they are doing.  We should

>>>>>

>>>>> 1.  Require suffix if there may be ambiguity.

>>>>

>>>> This would actively break existing code (reading "require" as "emit an

>>>> error if it is missing"). After all it's the present _inconsistency_

>>>> in behavior that this series tries to address.

>>>>

>>>>> 2.  Generate a warning if needed under a new option, (-mambiguity-check=?).

>>>>

>>>> First of all this contradicts 1 above: There's no point generating a

>>>> warning when we also generate an error. As to a separate option - if

>>>> you really don't want me to re-use the existing one (which is a pretty

>>>> good fit), I can certainly key this to a new one. But the default will

>>>> remain to be for the warning to be enabled.

>>>>

>>>>> 3.  Document the default operand size for AT&T syntax if there may be ambiguity.

>>>>

>>>> Will do.

>>>>

>>>

>>> Since AT&T syntax has no size info on memory operand, we can't tell memory

>>> size when mnemonic supports more than one memory size.   Currently AT&T

>>> syntax adds suffix to distinguish different memory sizes for these instructions.

>>> For some instructions, there is a default memory size when there is no suffix.

>>> In this sense, there is no ambiguity for assembler.   The only issue is that it

>>> isn't easy for programmer to tell what the default memory size is.

>>>

>>> To help programmers with these ambiguities when there is no suffix, we can

>>>

>>> 1. Document these ambiguities.

>>> 2. Issue warning when there is an exception in rules.   Warning should

>>> be kept as few as possible.   For most parts, the default size is 32-bit.

>>

>> "For most parts" is already telling enough, I think. Recall how

>>

>>          shl     %cl, (%eax)

>>

>> used to be wrongly deriving byte memory operand size from the

>> shift count register used? If things had been working flawlessly

>> so far, I'd maybe agree that there's no need for warnings by

>> default. But seeing how inconsistent _and broken_ things have

>> been, this is simply not an option.

>>

>>> add     $1, (%bx)

>>>

>>> shouldn't generate a warning since the destination is 32-bit.

>>

>> Good example (but of course I don't agree with the "no warning"

>> statement). Why is it then that

>>

>>          add     $0x89, (%eax)

>>          add     $0x12345678, (%eax)

>>

>> fail to assemble without the patch applied? Once again - may I

>> ask that you look at the additions to noreg*.s that this and

>> the subsequent patches do? These are all cases not working

>> currently, but which should work (and according to you even

>> without warning), and which this series makes work.

> 

> Given that in AT&T syntax needs the suffix for memory operand size,

> we should document existing quirks and shouldn't accept more

> instructions without suffix.


Why would that be? Why should there not be a mode in which
things work like for the reference assembler (which years ago
you've indicated the Solaris one would be, where their doc
clearly states that insns without suffix default to "long"),
as far is it makes sense, emitting diagnostics whenever gas
behavior may not conform to those original rules (like is
already done in most cases when suffix and register selection
aren't in sync)?

As to documenting existing "quirks": The example above is well
suited to also demonstrate that trying to document such "quirks"
would likely result in even more of a mess. Rather than
documenting anomalies, eliminating them should be preferred, when
this can sensibly be done (which this series demonstrates it can
here).

>>>   We can add

>>> a pseudo prefix {imm32} to request 32-bit immediate operand.

>>

>> I don't see how this relates here.

>>

> 

> We can encode

> 

> {imm32} addl   $0x70,(%rax)

> 

> with 32-bit immediate.


Sure, but I still don't see how it relates here. The entire series
is unconcerned with control over immediate sizes.

Jan
H.J. Lu Aug. 9, 2019, 11:10 p.m. | #9
On Fri, Aug 9, 2019 at 12:50 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 08.08.2019 18:19,  H.J. Lu  wrote:

> > On Thu, Aug 8, 2019 at 12:56 AM Jan Beulich <JBeulich@suse.com> wrote:

> >>

> >> On 08.08.2019 01:58,  H.J. Lu  wrote:

> >>> On Wed, Aug 7, 2019 at 1:27 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>>>

> >>>> On 06.08.2019 23:38,  H.J. Lu  wrote:

> >>>>> On Tue, Aug 6, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> >>>>>>

> >>>>>> On Tue, Aug 6, 2019 at 7:27 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>>>>>>

> >>>>>>> Commit b76bc5d54e ("x86: don't default variable shift count insns to

> >>>>>>> 8-bit operand size") pointed out a very bad case, but the underlying

> >>>>>>> problem is, as mentioned on various occasions, much larger: Silently

> >>>>>>> selecting a (nowhere documented afaict) certain default operand size

> >>>>>>> when there's no "sizing" suffix and no suitable register operand(s) is

> >>>>>>> simply dangerous (for the programmer to make mistakes).

> >>>>>>

> >>>>>> If there may be an ambiguity, a size suffix can be used.  Assembler isn't

> >>>>>> responsible for programmer's errors.

> >>>>>>

> >>>>>>> While in Intel syntax mode such mistakes already lead to an error (which

> >>>>>>> is going to remain that way), AT&T syntax mode now gains warnings in

> >>>>>>> such cases by default, which can be suppressed or promoted to an error

> >>>>>>

> >>>>>> This punishes the perfectly good assembly sources.

> >>>>>>

> >>>>>>> if so desired by the programmer. Furthermore at least general purpose

> >>>>>>> insns now consistently have a default applied (alongside the warning

> >>>>>>> emission), rather than accepting some and refusing others.

> >>>>>>>

> >>>>>>> No warnings are (as before) to be generated for "DefaultSize" insns as

> >>>>>>> well as ones acting on selector and other fixed-width values. The set of

> >>>>>>> "DefaultSize" one gets slightly widened for the purposes here.

> >>>>>>

> >>>>>> Widen the default size set avoids generate warnings.  It sounds to

> >>>>>> me these warnings isn't really necessary.

> >>>>>>

> >>>>>>> As set forth as a prereq when I first mentioned this intended change a

> >>>>>>> few years back, Linux as well as gcc have meanwhile been patched to

> >>>>>>> avoid emitting of ambiguous operands (and hence triggering of the new

> >>>>>>> warning).

> >>>>>>>

> >>>>>>> Note that floating point operations with integer operands are an

> >>>>>>> exception for now: They continue to use short (16-bit) operands by

> >>>>>>> default even in 32- and 64-bit modes.

> >>>>>>>

> >>>>>

> >>>>> Instruction suffix has been an issue with AT&T syntax.  But improvements

> >>>>> shouldn't assemble current working assembly sources cleanly.

> >>>>

> >>>> I guess you mean "should", not "shouldn't"? And "cleanly" to me does

> >>>> not imply without warnings, just without change to generated code

> >>>> (unless the generated code was outright wrong). Pointing out possible

> >>>> issues should not be restricted to cases that didn't assemble without

> >>>> error so far. Or else this would be one more argument against e.g.

> >>>> your recent "REP;" handling adjustment.

> >>>>

> >>>>>    It is reasonable

> >>>>> to require that programmers should know what they are doing.  We should

> >>>>>

> >>>>> 1.  Require suffix if there may be ambiguity.

> >>>>

> >>>> This would actively break existing code (reading "require" as "emit an

> >>>> error if it is missing"). After all it's the present _inconsistency_

> >>>> in behavior that this series tries to address.

> >>>>

> >>>>> 2.  Generate a warning if needed under a new option, (-mambiguity-check=?).

> >>>>

> >>>> First of all this contradicts 1 above: There's no point generating a

> >>>> warning when we also generate an error. As to a separate option - if

> >>>> you really don't want me to re-use the existing one (which is a pretty

> >>>> good fit), I can certainly key this to a new one. But the default will

> >>>> remain to be for the warning to be enabled.

> >>>>

> >>>>> 3.  Document the default operand size for AT&T syntax if there may be ambiguity.

> >>>>

> >>>> Will do.

> >>>>

> >>>

> >>> Since AT&T syntax has no size info on memory operand, we can't tell memory

> >>> size when mnemonic supports more than one memory size.   Currently AT&T

> >>> syntax adds suffix to distinguish different memory sizes for these instructions.

> >>> For some instructions, there is a default memory size when there is no suffix.

> >>> In this sense, there is no ambiguity for assembler.   The only issue is that it

> >>> isn't easy for programmer to tell what the default memory size is.

> >>>

> >>> To help programmers with these ambiguities when there is no suffix, we can

> >>>

> >>> 1. Document these ambiguities.

> >>> 2. Issue warning when there is an exception in rules.   Warning should

> >>> be kept as few as possible.   For most parts, the default size is 32-bit.

> >>

> >> "For most parts" is already telling enough, I think. Recall how

> >>

> >>          shl     %cl, (%eax)

> >>

> >> used to be wrongly deriving byte memory operand size from the

> >> shift count register used? If things had been working flawlessly

> >> so far, I'd maybe agree that there's no need for warnings by

> >> default. But seeing how inconsistent _and broken_ things have

> >> been, this is simply not an option.

> >>

> >>> add     $1, (%bx)

> >>>

> >>> shouldn't generate a warning since the destination is 32-bit.

> >>

> >> Good example (but of course I don't agree with the "no warning"

> >> statement). Why is it then that

> >>

> >>          add     $0x89, (%eax)

> >>          add     $0x12345678, (%eax)

> >>

> >> fail to assemble without the patch applied? Once again - may I

> >> ask that you look at the additions to noreg*.s that this and

> >> the subsequent patches do? These are all cases not working

> >> currently, but which should work (and according to you even

> >> without warning), and which this series makes work.

> >

> > Given that in AT&T syntax needs the suffix for memory operand size,

> > we should document existing quirks and shouldn't accept more

> > instructions without suffix.

>

> Why would that be? Why should there not be a mode in which

> things work like for the reference assembler (which years ago

> you've indicated the Solaris one would be, where their doc

> clearly states that insns without suffix default to "long"),

> as far is it makes sense, emitting diagnostics whenever gas

> behavior may not conform to those original rules (like is

> already done in most cases when suffix and register selection

> aren't in sync)?

>

> As to documenting existing "quirks": The example above is well

> suited to also demonstrate that trying to document such "quirks"

> would likely result in even more of a mess. Rather than

> documenting anomalies, eliminating them should be preferred, when

> this can sensibly be done (which this series demonstrates it can

> here).

>


From assembly program and debug perspective, a suffix is very useful
when there may be different memory operand sizes.   Allowing more
cases without suffix isn't helping here.  We need a strong reason to
do that.

-- 
H.J.
Jan Beulich Aug. 12, 2019, 8:21 a.m. | #10
On 10.08.2019 01:10,  H.J. Lu  wrote:
>  From assembly program and debug perspective, a suffix is very useful

> when there may be different memory operand sizes.   Allowing more

> cases without suffix isn't helping here.  We need a strong reason to

> do that.


I've given this very simple and (imo) pretty strong reason:
Consistency. Programmers ought to be able to deduce from observed
behavior on one insn how another, similar insns is going to be
treated by the assembler. Once again, simply compare un-patched
gas behavior for

	add	$1, (%eax)
	bt	$1, (%eax)

vs

	add	$0x89, (%eax)
	shl	$1, (%eax)
	shl	$2, (%eax)
	shl	%cl, (%eax)

This is simply unacceptable.

Having put together this series I think I've managed to (mostly)
understand why this is, but the pattern behind it has absolutely
nothing to do with how programmers should write their code.

I wouldn't, btw., mind if we uniformly rejected ambiguous insns,
but it was my understanding from the original discussion (a few
years back) that you wouldn't accept this.

In any event, may I remind you that during said earlier discussion
you had agreed to the underlying concept, including setting forth
acceptance criteria? I view it as entirely unreasonable that
you've made me invest quite a bit of time to fulfill those
criteria (and to get the patch, which as you can see has ended up
as a series) into a shape where the result is actually making
sense, just to find now that all of the sudden you mean to block
all of this work.

Jan
H.J. Lu Aug. 13, 2019, 11:30 p.m. | #11
On Mon, Aug 12, 2019 at 1:21 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 10.08.2019 01:10,  H.J. Lu  wrote:

> >  From assembly program and debug perspective, a suffix is very useful

> > when there may be different memory operand sizes.   Allowing more

> > cases without suffix isn't helping here.  We need a strong reason to

> > do that.

>

> I've given this very simple and (imo) pretty strong reason:

> Consistency. Programmers ought to be able to deduce from observed

> behavior on one insn how another, similar insns is going to be

> treated by the assembler. Once again, simply compare un-patched

> gas behavior for

>

>         add     $1, (%eax)

>         bt      $1, (%eax)

>

> vs

>

>         add     $0x89, (%eax)

>         shl     $1, (%eax)

>         shl     $2, (%eax)

>         shl     %cl, (%eax)

>

> This is simply unacceptable.

>

> Having put together this series I think I've managed to (mostly)

> understand why this is, but the pattern behind it has absolutely

> nothing to do with how programmers should write their code.

>

> I wouldn't, btw., mind if we uniformly rejected ambiguous insns,

> but it was my understanding from the original discussion (a few

> years back) that you wouldn't accept this.

>

> In any event, may I remind you that during said earlier discussion

> you had agreed to the underlying concept, including setting forth

> acceptance criteria? I view it as entirely unreasonable that

> you've made me invest quite a bit of time to fulfill those

> criteria (and to get the patch, which as you can see has ended up

> as a series) into a shape where the result is actually making

> sense, just to find now that all of the sudden you mean to block

> all of this work.


My concerns are

1. AT&T syntax uses suffix for memory operand size.
2. Many instructions without suffix are accepted with default memory
size.
3. Default memory size isn't consistent.
4. Programmers have lived with inconsistency for years.

I'd like to require suffix when memory sizes are possible.  It certainly
won't happen.  But adding more default memory size doesn't help
AT&T syntax.

-- 
H.J.
Jan Beulich Aug. 28, 2019, 7:59 a.m. | #12
On 14.08.2019 01:30,  H.J. Lu  wrote:
> On Mon, Aug 12, 2019 at 1:21 AM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> On 10.08.2019 01:10,  H.J. Lu  wrote:

>>>   From assembly program and debug perspective, a suffix is very useful

>>> when there may be different memory operand sizes.   Allowing more

>>> cases without suffix isn't helping here.  We need a strong reason to

>>> do that.

>>

>> I've given this very simple and (imo) pretty strong reason:

>> Consistency. Programmers ought to be able to deduce from observed

>> behavior on one insn how another, similar insns is going to be

>> treated by the assembler. Once again, simply compare un-patched

>> gas behavior for

>>

>>          add     $1, (%eax)

>>          bt      $1, (%eax)

>>

>> vs

>>

>>          add     $0x89, (%eax)

>>          shl     $1, (%eax)

>>          shl     $2, (%eax)

>>          shl     %cl, (%eax)

>>

>> This is simply unacceptable.

>>

>> Having put together this series I think I've managed to (mostly)

>> understand why this is, but the pattern behind it has absolutely

>> nothing to do with how programmers should write their code.

>>

>> I wouldn't, btw., mind if we uniformly rejected ambiguous insns,

>> but it was my understanding from the original discussion (a few

>> years back) that you wouldn't accept this.

>>

>> In any event, may I remind you that during said earlier discussion

>> you had agreed to the underlying concept, including setting forth

>> acceptance criteria? I view it as entirely unreasonable that

>> you've made me invest quite a bit of time to fulfill those

>> criteria (and to get the patch, which as you can see has ended up

>> as a series) into a shape where the result is actually making

>> sense, just to find now that all of the sudden you mean to block

>> all of this work.

> 

> My concerns are

> 

> 1. AT&T syntax uses suffix for memory operand size.

> 2. Many instructions without suffix are accepted with default memory

> size.

> 3. Default memory size isn't consistent.


Is it? Afaict what's inconsistent is whether insns are accepted without
suffix.

> 4. Programmers have lived with inconsistency for years.


That's no excuse to keep things like this.

> I'd like to require suffix when memory sizes are possible.  It certainly

> won't happen.  But adding more default memory size doesn't help

> AT&T syntax.


I've said so before: I'd be happy to switch to a mode where the lack
of suffix is an error when otherwise there's an ambiguity (as is
already the case in Intel syntax mode). But considering prior behavior
this seems rather harsh, hence emitting warnings (and doing so
consistently) seems the better initial step. Switching these to being
errors instead could be considered a few releases later.

Jan

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6336,6 +6336,12 @@  process_suffix (void)
      }
    else if (i.tm.opcode_modifier.defaultsize
  	   && !i.suffix
+	   /* exclude jmp/ljmp */
+	   && strcmp (i.tm.name, "jmp") && strcmp (i.tm.name, "ljmp")
+	   /* exclude byte-displacement jumps */
+	   && !i.tm.opcode_modifier.jumpbyte
+	   /* exclude lgdt/lidt/sgdt/sidt */
+	   && (i.tm.base_opcode != 0x0f01 || i.tm.extension_opcode > 3)
  	   /* exclude fldenv/frstor/fsave/fstenv */
  	   && i.tm.opcode_modifier.no_ssuf)
      {
@@ -6383,40 +6389,47 @@  process_suffix (void)
  
    if (!i.suffix)
      {
-      if (!intel_syntax)
+      unsigned int suffixes;
+
+      suffixes = !i.tm.opcode_modifier.no_bsuf;
+      if (!i.tm.opcode_modifier.no_wsuf)
+	suffixes |= 1 << 1;
+      if (!i.tm.opcode_modifier.no_lsuf)
+	suffixes |= 1 << 2;
+      if (!i.tm.opcode_modifier.no_ldsuf)
+	suffixes |= 1 << 3;
+      if (!i.tm.opcode_modifier.no_ssuf)
+	suffixes |= 1 << 4;
+      if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
+	suffixes |= 1 << 5;
+
+      /* Are multiple suffixes allowed?  */
+      if ((suffixes & (suffixes - 1))
+	  && !i.tm.opcode_modifier.defaultsize
+	  && !i.tm.opcode_modifier.ignoresize)
  	{
-	  if (i.tm.opcode_modifier.w)
+	  if (intel_syntax)
  	    {
-	      as_bad (_("no instruction mnemonic suffix given and "
-			"no register operands; can't size instruction"));
+	      as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
  	      return 0;
  	    }
-	}
-      else
-	{
-	  unsigned int suffixes;
-
-	  suffixes = !i.tm.opcode_modifier.no_bsuf;
-	  if (!i.tm.opcode_modifier.no_wsuf)
-	    suffixes |= 1 << 1;
-	  if (!i.tm.opcode_modifier.no_lsuf)
-	    suffixes |= 1 << 2;
-	  if (!i.tm.opcode_modifier.no_ldsuf)
-	    suffixes |= 1 << 3;
-	  if (!i.tm.opcode_modifier.no_ssuf)
-	    suffixes |= 1 << 4;
-	  if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
-	    suffixes |= 1 << 5;
-
-	  /* There are more than suffix matches.  */
-	  if (i.tm.opcode_modifier.w
-	      || ((suffixes & (suffixes - 1))
-		  && !i.tm.opcode_modifier.defaultsize
-		  && !i.tm.opcode_modifier.ignoresize))
+	  if (operand_check == check_error)
  	    {
-	      as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+	      as_bad (_("no instruction mnemonic suffix given and "
+			"no register operands; can't size `%s'"), i.tm.name);
  	      return 0;
  	    }
+	  if (operand_check == check_warning)
+	    as_warn (_("no instruction mnemonic suffix given and "
+		       "no register operands; using default for `%s'"),
+		     i.tm.name);
+
+	  if (i.tm.opcode_modifier.floatmf)
+	    i.suffix = SHORT_MNEM_SUFFIX;
+	  else if (flag_code == CODE_16BIT)
+	    i.suffix = WORD_MNEM_SUFFIX;
+	  else
+	    i.suffix = LONG_MNEM_SUFFIX;
  	}
      }
  
--- a/gas/testsuite/gas/i386/bundle.s
+++ b/gas/testsuite/gas/i386/bundle.s
@@ -58,7 +58,7 @@ 
  	and $3,%eax
  .endm
  .macro test_4
-	lock and $3,(%eax)
+	lock andl $3,(%eax)
  .endm
  .macro test_5
  	mov $0xaabbccdd,%eax
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -129,7 +129,9 @@  if [expr ([istarget "i*86-*-*"] ||  [ist
      run_dump_test "nops-6"
      run_dump_test "nops-7"
      run_dump_test "noreg16"
+    run_list_test "noreg16"
      run_dump_test "noreg32"
+    run_list_test "noreg32"
      run_dump_test "addr16"
      run_dump_test "addr32"
      run_list_test "oversized16" "-al"
@@ -699,6 +701,7 @@  if [expr ([istarget "i*86-*-*"] || [ista
      run_dump_test "x86-64-nops-5-k8"
      run_dump_test "x86-64-nops-7"
      run_dump_test "noreg64"
+    run_list_test "noreg64"
      run_list_test "cvtsi2sX"
      run_dump_test "x86-64-sse4_1"
      run_dump_test "x86-64-sse4_1-intel"
--- a/gas/testsuite/gas/i386/ilp32/x86-64-nops.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops.d
@@ -42,7 +42,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	0f 1d 04 59          	nopl   \(%rcx,%rbx,2\)
  [ 	]*[a-f0-9]+:	0f 1e 04 59          	nopl   \(%rcx,%rbx,2\)
  [ 	]*[a-f0-9]+:	0f 1f 04 59          	nopl   \(%rcx,%rbx,2\)
-[ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%rax\)
  [ 	]*[a-f0-9]+:	48 0f 1f c0          	nop    %rax
  [ 	]*[a-f0-9]+:	0f 1f c0             	nop    %eax
  [ 	]*[a-f0-9]+:	66 0f 1f c0          	nop    %ax
@@ -52,7 +51,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	48 0f 1f c0          	nop    %rax
  [ 	]*[a-f0-9]+:	0f 1f c0             	nop    %eax
  [ 	]*[a-f0-9]+:	66 0f 1f c0          	nop    %ax
-[ 	]*[a-f0-9]+:	41 0f 1f 02          	nopl   \(%r10\)
  [ 	]*[a-f0-9]+:	49 0f 1f c2          	nop    %r10
  [ 	]*[a-f0-9]+:	41 0f 1f c2          	nop    %r10d
  [ 	]*[a-f0-9]+:	66 41 0f 1f c2       	nop    %r10w
--- a/gas/testsuite/gas/i386/ilp32/x86-64-sse-noavx.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-sse-noavx.d
@@ -17,7 +17,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2c dc          	cvttpd2pi %xmm4,%mm3
  [ 	]*[a-f0-9]+:	0f 2c dc             	cvttps2pi %xmm4,%mm3
  [ 	]*[a-f0-9]+:	df 08                	fisttps \(%rax\)
-[ 	]*[a-f0-9]+:	df 08                	fisttps \(%rax\)
  [ 	]*[a-f0-9]+:	db 08                	fisttpl \(%rax\)
  [ 	]*[a-f0-9]+:	dd 08                	fisttpll \(%rax\)
  [ 	]*[a-f0-9]+:	0f ae e8             	lfence
--- a/gas/testsuite/gas/i386/lock-1.s
+++ b/gas/testsuite/gas/i386/lock-1.s
@@ -3,17 +3,17 @@ 
  	.text
  foo:
  	lock add %eax, (%ebx)
-	lock add $0x64, (%ebx)
+	lock addl $0x64, (%ebx)
  	lock adc %eax, (%ebx)
-	lock adc $0x64, (%ebx)
+	lock adcl $0x64, (%ebx)
  	lock and %eax, (%ebx)
-	lock and $0x64, (%ebx)
+	lock andl $0x64, (%ebx)
  	lock btc %eax, (%ebx)
-	lock btc $0x64, (%ebx)
+	lock btcl $0x64, (%ebx)
  	lock btr %eax, (%ebx)
-	lock btr $0x64, (%ebx)
+	lock btrl $0x64, (%ebx)
  	lock bts %eax, (%ebx)
-	lock bts $0x64, (%ebx)
+	lock btsl $0x64, (%ebx)
  	lock cmpxchg %eax,(%ebx)
  	lock cmpxchg8b (%ebx)
  	lock decl (%ebx)
@@ -21,16 +21,16 @@  foo:
  	lock negl (%ebx)
  	lock notl (%ebx)
  	lock or %eax, (%ebx)
-	lock or $0x64, (%ebx)
+	lock orl $0x64, (%ebx)
  	lock sbb %eax, (%ebx)
-	lock sbb $0x64, (%ebx)
+	lock sbbl $0x64, (%ebx)
  	lock sub %eax, (%ebx)
-	lock sub $0x64, (%ebx)
+	lock subl $0x64, (%ebx)
  	lock xadd %eax, (%ebx)
  	lock xchg (%ebx), %eax
  	lock xchg %eax, (%ebx)
  	lock xor %eax, (%ebx)
-	lock xor $0x64, (%ebx)
+	lock xorl $0x64, (%ebx)
  
  	.intel_syntax noprefix
  	lock add DWORD PTR [ebx],eax
--- a/gas/testsuite/gas/i386/nops.d
+++ b/gas/testsuite/gas/i386/nops.d
@@ -41,7 +41,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	0f 1d 04 59          	nopl   \(%ecx,%ebx,2\)
  [ 	]*[a-f0-9]+:	0f 1e 04 59          	nopl   \(%ecx,%ebx,2\)
  [ 	]*[a-f0-9]+:	0f 1f 04 59          	nopl   \(%ecx,%ebx,2\)
-[ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%eax\)
  [ 	]*[a-f0-9]+:	0f 1f c0             	nop    %eax
  [ 	]*[a-f0-9]+:	66 0f 1f c0          	nop    %ax
  [ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%eax\)
--- a/gas/testsuite/gas/i386/nops.s
+++ b/gas/testsuite/gas/i386/nops.s
@@ -44,7 +44,6 @@ 
  	.byte 0x0f, 0x1e, 0x04, 0x59
  	.byte 0x0f, 0x1f, 0x04, 0x59
  
-	nop (%eax)
  	nop %eax
  	nop %ax
  	nopl (%eax)
--- a/gas/testsuite/gas/i386/noreg16.d
+++ b/gas/testsuite/gas/i386/noreg16.d
@@ -1,3 +1,4 @@ 
+#as: -moperand-check=none
  #objdump: -dwMi8086
  #name: 16-bit insns not sizeable through register operands
  
@@ -7,16 +8,28 @@  Disassembly of section .text:
  
  0+ <noreg>:
   *[a-f0-9]+:	83 17 01             	adcw   \$0x1,\(%bx\)
+ *[a-f0-9]+:	81 17 89 00          	adcw   \$0x89,\(%bx\)
+ *[a-f0-9]+:	81 17 34 12          	adcw   \$0x1234,\(%bx\)
   *[a-f0-9]+:	83 07 01             	addw   \$0x1,\(%bx\)
+ *[a-f0-9]+:	81 07 89 00          	addw   \$0x89,\(%bx\)
+ *[a-f0-9]+:	81 07 34 12          	addw   \$0x1234,\(%bx\)
   *[a-f0-9]+:	83 27 01             	andw   \$0x1,\(%bx\)
+ *[a-f0-9]+:	81 27 89 00          	andw   \$0x89,\(%bx\)
+ *[a-f0-9]+:	81 27 34 12          	andw   \$0x1234,\(%bx\)
   *[a-f0-9]+:	0f ba 27 01          	btw    \$0x1,\(%bx\)
   *[a-f0-9]+:	0f ba 3f 01          	btcw   \$0x1,\(%bx\)
   *[a-f0-9]+:	0f ba 37 01          	btrw   \$0x1,\(%bx\)
   *[a-f0-9]+:	0f ba 2f 01          	btsw   \$0x1,\(%bx\)
   *[a-f0-9]+:	ff 17                	call   \*\(%bx\)
   *[a-f0-9]+:	83 3f 01             	cmpw   \$0x1,\(%bx\)
+ *[a-f0-9]+:	81 3f 89 00          	cmpw   \$0x89,\(%bx\)
+ *[a-f0-9]+:	81 3f 34 12          	cmpw   \$0x1234,\(%bx\)
+ *[a-f0-9]+:	a7                   	cmpsw  %es:\(%di\),%ds:\(%si\)
+ *[a-f0-9]+:	67 a7                	cmpsw  %es:\(%edi\),%ds:\(%esi\)
   *[a-f0-9]+:	f2 0f 2a 07          	cvtsi2sdl \(%bx\),%xmm0
   *[a-f0-9]+:	f3 0f 2a 07          	cvtsi2ssl \(%bx\),%xmm0
+ *[a-f0-9]+:	ff 0f                	decw   \(%bx\)
+ *[a-f0-9]+:	f7 37                	divw   \(%bx\)
   *[a-f0-9]+:	d8 07                	fadds  \(%bx\)
   *[a-f0-9]+:	d8 17                	fcoms  \(%bx\)
   *[a-f0-9]+:	d8 1f                	fcomps \(%bx\)
@@ -40,22 +53,74 @@  Disassembly of section .text:
   *[a-f0-9]+:	d9 1f                	fstps  \(%bx\)
   *[a-f0-9]+:	d8 27                	fsubs  \(%bx\)
   *[a-f0-9]+:	d8 2f                	fsubrs \(%bx\)
+ *[a-f0-9]+:	f7 3f                	idivw  \(%bx\)
+ *[a-f0-9]+:	f7 2f                	imulw  \(%bx\)
+ *[a-f0-9]+:	ff 07                	incw   \(%bx\)
+ *[a-f0-9]+:	6d                   	insw   \(%dx\),%es:\(%di\)
+ *[a-f0-9]+:	67 6d                	insw   \(%dx\),%es:\(%edi\)
   *[a-f0-9]+:	ff 27                	jmp    \*\(%bx\)
   *[a-f0-9]+:	0f 01 17             	lgdtw  \(%bx\)
   *[a-f0-9]+:	0f 01 1f             	lidtw  \(%bx\)
   *[a-f0-9]+:	0f 00 17             	lldt   \(%bx\)
   *[a-f0-9]+:	0f 01 37             	lmsw   \(%bx\)
+ *[a-f0-9]+:	ad                   	lods   %ds:\(%si\),%ax
+ *[a-f0-9]+:	67 ad                	lods   %ds:\(%esi\),%ax
   *[a-f0-9]+:	0f 00 1f             	ltr    \(%bx\)
+ *[a-f0-9]+:	c7 07 12 00          	movw   \$0x12,\(%bx\)
+ *[a-f0-9]+:	c7 07 34 12          	movw   \$0x1234,\(%bx\)
   *[a-f0-9]+:	8c 07                	mov    %es,\(%bx\)
   *[a-f0-9]+:	8e 07                	mov    \(%bx\),%es
+ *[a-f0-9]+:	a5                   	movsw  %ds:\(%si\),%es:\(%di\)
+ *[a-f0-9]+:	67 a5                	movsw  %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+:	f7 27                	mulw   \(%bx\)
+ *[a-f0-9]+:	f7 1f                	negw   \(%bx\)
+ *[a-f0-9]+:	f7 17                	notw   \(%bx\)
   *[a-f0-9]+:	83 0f 01             	orw    \$0x1,\(%bx\)
+ *[a-f0-9]+:	81 0f 89 00          	orw    \$0x89,\(%bx\)
+ *[a-f0-9]+:	81 0f 34 12          	orw    \$0x1234,\(%bx\)
+ *[a-f0-9]+:	6f                   	outsw  %ds:\(%si\),\(%dx\)
+ *[a-f0-9]+:	67 6f                	outsw  %ds:\(%esi\),\(%dx\)
   *[a-f0-9]+:	8f 07                	popw   \(%bx\)
   *[a-f0-9]+:	07                   	pop    %es
   *[a-f0-9]+:	f3 0f ae 27          	ptwritel \(%bx\)
   *[a-f0-9]+:	ff 37                	pushw  \(%bx\)
   *[a-f0-9]+:	06                   	push   %es
+ *[a-f0-9]+:	d1 17                	rclw   \(%bx\)
+ *[a-f0-9]+:	c1 17 02             	rclw   \$0x2,\(%bx\)
+ *[a-f0-9]+:	d3 17                	rclw   %cl,\(%bx\)
+ *[a-f0-9]+:	d1 1f                	rcrw   \(%bx\)
+ *[a-f0-9]+:	c1 1f 02             	rcrw   \$0x2,\(%bx\)
+ *[a-f0-9]+:	d3 1f                	rcrw   %cl,\(%bx\)
+ *[a-f0-9]+:	d1 07                	rolw   \(%bx\)
+ *[a-f0-9]+:	c1 07 02             	rolw   \$0x2,\(%bx\)
+ *[a-f0-9]+:	d3 07                	rolw   %cl,\(%bx\)
+ *[a-f0-9]+:	d1 0f                	rorw   \(%bx\)
+ *[a-f0-9]+:	c1 0f 02             	rorw   \$0x2,\(%bx\)
+ *[a-f0-9]+:	d3 0f                	rorw   %cl,\(%bx\)
   *[a-f0-9]+:	83 1f 01             	sbbw   \$0x1,\(%bx\)
+ *[a-f0-9]+:	81 1f 89 00          	sbbw   \$0x89,\(%bx\)
+ *[a-f0-9]+:	81 1f 34 12          	sbbw   \$0x1234,\(%bx\)
+ *[a-f0-9]+:	af                   	scas   %es:\(%di\),%ax
+ *[a-f0-9]+:	67 af                	scas   %es:\(%edi\),%ax
+ *[a-f0-9]+:	d1 27                	shlw   \(%bx\)
+ *[a-f0-9]+:	c1 27 02             	shlw   \$0x2,\(%bx\)
+ *[a-f0-9]+:	d3 27                	shlw   %cl,\(%bx\)
+ *[a-f0-9]+:	d1 3f                	sarw   \(%bx\)
+ *[a-f0-9]+:	c1 3f 02             	sarw   \$0x2,\(%bx\)
+ *[a-f0-9]+:	d3 3f                	sarw   %cl,\(%bx\)
+ *[a-f0-9]+:	d1 27                	shlw   \(%bx\)
+ *[a-f0-9]+:	c1 27 02             	shlw   \$0x2,\(%bx\)
+ *[a-f0-9]+:	d3 27                	shlw   %cl,\(%bx\)
+ *[a-f0-9]+:	d1 2f                	shrw   \(%bx\)
+ *[a-f0-9]+:	c1 2f 02             	shrw   \$0x2,\(%bx\)
+ *[a-f0-9]+:	d3 2f                	shrw   %cl,\(%bx\)
+ *[a-f0-9]+:	ab                   	stos   %ax,%es:\(%di\)
+ *[a-f0-9]+:	67 ab                	stos   %ax,%es:\(%edi\)
   *[a-f0-9]+:	83 2f 01             	subw   \$0x1,\(%bx\)
+ *[a-f0-9]+:	81 2f 89 00          	subw   \$0x89,\(%bx\)
+ *[a-f0-9]+:	81 2f 34 12          	subw   \$0x1234,\(%bx\)
+ *[a-f0-9]+:	f7 07 89 00          	testw  \$0x89,\(%bx\)
+ *[a-f0-9]+:	f7 07 34 12          	testw  \$0x1234,\(%bx\)
   *[a-f0-9]+:	c5 fb 2a 07          	vcvtsi2sdl \(%bx\),%xmm0,%xmm0
   *[a-f0-9]+:	62 f1 7f 08 2a 07    	vcvtsi2sdl \(%bx\),%xmm0,%xmm0
   *[a-f0-9]+:	c5 fa 2a 07          	vcvtsi2ssl \(%bx\),%xmm0,%xmm0
@@ -63,4 +128,6 @@  Disassembly of section .text:
   *[a-f0-9]+:	62 f1 7f 08 7b 07    	vcvtusi2sdl \(%bx\),%xmm0,%xmm0
   *[a-f0-9]+:	62 f1 7e 08 7b 07    	vcvtusi2ssl \(%bx\),%xmm0,%xmm0
   *[a-f0-9]+:	83 37 01             	xorw   \$0x1,\(%bx\)
+ *[a-f0-9]+:	81 37 89 00          	xorw   \$0x89,\(%bx\)
+ *[a-f0-9]+:	81 37 34 12          	xorw   \$0x1234,\(%bx\)
  #pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg16.l
@@ -0,0 +1,102 @@ 
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg16.s
+++ b/gas/testsuite/gas/i386/noreg16.s
@@ -2,16 +2,28 @@ 
  	.code16
  noreg:
  	adc	$1, (%bx)
+	adc	$0x89, (%bx)
+	adc	$0x1234, (%bx)
  	add	$1, (%bx)
+	add	$0x89, (%bx)
+	add	$0x1234, (%bx)
  	and	$1, (%bx)
+	and	$0x89, (%bx)
+	and	$0x1234, (%bx)
  	bt	$1, (%bx)
  	btc	$1, (%bx)
  	btr	$1, (%bx)
  	bts	$1, (%bx)
  	call	*(%bx)
  	cmp	$1, (%bx)
+	cmp	$0x89, (%bx)
+	cmp	$0x1234, (%bx)
+	cmps
+	cmps	%es:(%edi), (%esi)
  	cvtsi2sd (%bx), %xmm0
  	cvtsi2ss (%bx), %xmm0
+	dec	(%bx)
+	div	(%bx)
  	fadd	(%bx)
  	fcom	(%bx)
  	fcomp	(%bx)
@@ -35,22 +47,74 @@  noreg:
  	fstp	(%bx)
  	fsub	(%bx)
  	fsubr	(%bx)
+	idiv	(%bx)
+	imul	(%bx)
+	inc	(%bx)
+	ins
+	ins	%dx, %es:(%edi)
  	jmp	*(%bx)
  	lgdt	(%bx)
  	lidt	(%bx)
  	lldt	(%bx)
  	lmsw	(%bx)
+	lods
+	lods	(%esi)
  	ltr	(%bx)
+	mov	$0x12, (%bx)
+	mov	$0x1234, (%bx)
  	mov	%es, (%bx)
  	mov	(%bx), %es
+	movs
+	movs	(%esi), %es:(%edi)
+	mul	(%bx)
+	neg	(%bx)
+	not	(%bx)
  	or	$1, (%bx)
+	or	$0x89, (%bx)
+	or	$0x1234, (%bx)
+	outs
+	outs	(%esi), %dx
  	pop	(%bx)
  	pop	%es
  	ptwrite	(%bx)
  	push	(%bx)
  	push	%es
+	rcl	$1, (%bx)
+	rcl	$2, (%bx)
+	rcl	%cl, (%bx)
+	rcr	$1, (%bx)
+	rcr	$2, (%bx)
+	rcr	%cl, (%bx)
+	rol	$1, (%bx)
+	rol	$2, (%bx)
+	rol	%cl, (%bx)
+	ror	$1, (%bx)
+	ror	$2, (%bx)
+	ror	%cl, (%bx)
  	sbb	$1, (%bx)
+	sbb	$0x89, (%bx)
+	sbb	$0x1234, (%bx)
+	scas
+	scas	%es:(%edi)
+	sal	$1, (%bx)
+	sal	$2, (%bx)
+	sal	%cl, (%bx)
+	sar	$1, (%bx)
+	sar	$2, (%bx)
+	sar	%cl, (%bx)
+	shl	$1, (%bx)
+	shl	$2, (%bx)
+	shl	%cl, (%bx)
+	shr	$1, (%bx)
+	shr	$2, (%bx)
+	shr	%cl, (%bx)
+	stos
+	stos	%es:(%edi)
  	sub	$1, (%bx)
+	sub	$0x89, (%bx)
+	sub	$0x1234, (%bx)
+	test	$0x89, (%bx)
+	test	$0x1234, (%bx)
  	vcvtsi2sd (%bx), %xmm0, %xmm0
  	{evex} vcvtsi2sd (%bx), %xmm0, %xmm0
  	vcvtsi2ss (%bx), %xmm0, %xmm0
@@ -58,3 +122,5 @@  noreg:
  	vcvtusi2sd (%bx), %xmm0, %xmm0
  	vcvtusi2ss (%bx), %xmm0, %xmm0
  	xor	$1, (%bx)
+	xor	$0x89, (%bx)
+	xor	$0x1234, (%bx)
--- a/gas/testsuite/gas/i386/noreg32.d
+++ b/gas/testsuite/gas/i386/noreg32.d
@@ -1,3 +1,4 @@ 
+#as: -moperand-check=none
  #objdump: -dw
  #name: 32-bit insns not sizeable through register operands
  
@@ -7,16 +8,32 @@  Disassembly of section .text:
  
  0+ <noreg>:
   *[a-f0-9]+:	83 10 01             	adcl   \$0x1,\(%eax\)
+ *[a-f0-9]+:	81 10 89 00 00 00    	adcl   \$0x89,\(%eax\)
+ *[a-f0-9]+:	81 10 34 12 00 00    	adcl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:	81 10 78 56 34 12    	adcl   \$0x12345678,\(%eax\)
   *[a-f0-9]+:	83 00 01             	addl   \$0x1,\(%eax\)
+ *[a-f0-9]+:	81 00 89 00 00 00    	addl   \$0x89,\(%eax\)
+ *[a-f0-9]+:	81 00 34 12 00 00    	addl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:	81 00 78 56 34 12    	addl   \$0x12345678,\(%eax\)
   *[a-f0-9]+:	83 20 01             	andl   \$0x1,\(%eax\)
+ *[a-f0-9]+:	81 20 89 00 00 00    	andl   \$0x89,\(%eax\)
+ *[a-f0-9]+:	81 20 34 12 00 00    	andl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:	81 20 78 56 34 12    	andl   \$0x12345678,\(%eax\)
   *[a-f0-9]+:	0f ba 20 01          	btl    \$0x1,\(%eax\)
   *[a-f0-9]+:	0f ba 38 01          	btcl   \$0x1,\(%eax\)
   *[a-f0-9]+:	0f ba 30 01          	btrl   \$0x1,\(%eax\)
   *[a-f0-9]+:	0f ba 28 01          	btsl   \$0x1,\(%eax\)
   *[a-f0-9]+:	ff 10                	call   \*\(%eax\)
   *[a-f0-9]+:	83 38 01             	cmpl   \$0x1,\(%eax\)
+ *[a-f0-9]+:	81 38 89 00 00 00    	cmpl   \$0x89,\(%eax\)
+ *[a-f0-9]+:	81 38 34 12 00 00    	cmpl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:	81 38 78 56 34 12    	cmpl   \$0x12345678,\(%eax\)
+ *[a-f0-9]+:	a7                   	cmpsl  %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+:	a7                   	cmpsl  %es:\(%edi\),%ds:\(%esi\)
   *[a-f0-9]+:	f2 0f 2a 00          	cvtsi2sdl \(%eax\),%xmm0
   *[a-f0-9]+:	f3 0f 2a 00          	cvtsi2ssl \(%eax\),%xmm0
+ *[a-f0-9]+:	ff 08                	decl   \(%eax\)
+ *[a-f0-9]+:	f7 30                	divl   \(%eax\)
   *[a-f0-9]+:	d8 00                	fadds  \(%eax\)
   *[a-f0-9]+:	d8 10                	fcoms  \(%eax\)
   *[a-f0-9]+:	d8 18                	fcomps \(%eax\)
@@ -40,22 +57,79 @@  Disassembly of section .text:
   *[a-f0-9]+:	d9 18                	fstps  \(%eax\)
   *[a-f0-9]+:	d8 20                	fsubs  \(%eax\)
   *[a-f0-9]+:	d8 28                	fsubrs \(%eax\)
+ *[a-f0-9]+:	f7 38                	idivl  \(%eax\)
+ *[a-f0-9]+:	f7 28                	imull  \(%eax\)
+ *[a-f0-9]+:	ff 00                	incl   \(%eax\)
+ *[a-f0-9]+:	6d                   	insl   \(%dx\),%es:\(%edi\)
+ *[a-f0-9]+:	6d                   	insl   \(%dx\),%es:\(%edi\)
   *[a-f0-9]+:	ff 20                	jmp    \*\(%eax\)
   *[a-f0-9]+:	0f 01 10             	lgdtl  \(%eax\)
   *[a-f0-9]+:	0f 01 18             	lidtl  \(%eax\)
   *[a-f0-9]+:	0f 00 10             	lldt   \(%eax\)
   *[a-f0-9]+:	0f 01 30             	lmsw   \(%eax\)
+ *[a-f0-9]+:	ad                   	lods   %ds:\(%esi\),%eax
+ *[a-f0-9]+:	ad                   	lods   %ds:\(%esi\),%eax
   *[a-f0-9]+:	0f 00 18             	ltr    \(%eax\)
+ *[a-f0-9]+:	c7 00 12 00 00 00    	movl   \$0x12,\(%eax\)
+ *[a-f0-9]+:	c7 00 34 12 00 00    	movl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:	c7 00 78 56 34 12    	movl   \$0x12345678,\(%eax\)
   *[a-f0-9]+:	8c 00                	mov    %es,\(%eax\)
   *[a-f0-9]+:	8e 00                	mov    \(%eax\),%es
+ *[a-f0-9]+:	a5                   	movsl  %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+:	a5                   	movsl  %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+:	f7 20                	mull   \(%eax\)
+ *[a-f0-9]+:	f7 18                	negl   \(%eax\)
+ *[a-f0-9]+:	f7 10                	notl   \(%eax\)
   *[a-f0-9]+:	83 08 01             	orl    \$0x1,\(%eax\)
+ *[a-f0-9]+:	81 08 89 00 00 00    	orl    \$0x89,\(%eax\)
+ *[a-f0-9]+:	81 08 34 12 00 00    	orl    \$0x1234,\(%eax\)
+ *[a-f0-9]+:	81 08 78 56 34 12    	orl    \$0x12345678,\(%eax\)
+ *[a-f0-9]+:	6f                   	outsl  %ds:\(%esi\),\(%dx\)
+ *[a-f0-9]+:	6f                   	outsl  %ds:\(%esi\),\(%dx\)
   *[a-f0-9]+:	8f 00                	popl   \(%eax\)
   *[a-f0-9]+:	07                   	pop    %es
   *[a-f0-9]+:	f3 0f ae 20          	ptwritel \(%eax\)
   *[a-f0-9]+:	ff 30                	pushl  \(%eax\)
   *[a-f0-9]+:	06                   	push   %es
+ *[a-f0-9]+:	d1 10                	rcll   \(%eax\)
+ *[a-f0-9]+:	c1 10 02             	rcll   \$0x2,\(%eax\)
+ *[a-f0-9]+:	d3 10                	rcll   %cl,\(%eax\)
+ *[a-f0-9]+:	d1 18                	rcrl   \(%eax\)
+ *[a-f0-9]+:	c1 18 02             	rcrl   \$0x2,\(%eax\)
+ *[a-f0-9]+:	d3 18                	rcrl   %cl,\(%eax\)
+ *[a-f0-9]+:	d1 00                	roll   \(%eax\)
+ *[a-f0-9]+:	c1 00 02             	roll   \$0x2,\(%eax\)
+ *[a-f0-9]+:	d3 00                	roll   %cl,\(%eax\)
+ *[a-f0-9]+:	d1 08                	rorl   \(%eax\)
+ *[a-f0-9]+:	c1 08 02             	rorl   \$0x2,\(%eax\)
+ *[a-f0-9]+:	d3 08                	rorl   %cl,\(%eax\)
   *[a-f0-9]+:	83 18 01             	sbbl   \$0x1,\(%eax\)
+ *[a-f0-9]+:	81 18 89 00 00 00    	sbbl   \$0x89,\(%eax\)
+ *[a-f0-9]+:	81 18 34 12 00 00    	sbbl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:	81 18 78 56 34 12    	sbbl   \$0x12345678,\(%eax\)
+ *[a-f0-9]+:	af                   	scas   %es:\(%edi\),%eax
+ *[a-f0-9]+:	af                   	scas   %es:\(%edi\),%eax
+ *[a-f0-9]+:	d1 20                	shll   \(%eax\)
+ *[a-f0-9]+:	c1 20 02             	shll   \$0x2,\(%eax\)
+ *[a-f0-9]+:	d3 20                	shll   %cl,\(%eax\)
+ *[a-f0-9]+:	d1 38                	sarl   \(%eax\)
+ *[a-f0-9]+:	c1 38 02             	sarl   \$0x2,\(%eax\)
+ *[a-f0-9]+:	d3 38                	sarl   %cl,\(%eax\)
+ *[a-f0-9]+:	d1 20                	shll   \(%eax\)
+ *[a-f0-9]+:	c1 20 02             	shll   \$0x2,\(%eax\)
+ *[a-f0-9]+:	d3 20                	shll   %cl,\(%eax\)
+ *[a-f0-9]+:	d1 28                	shrl   \(%eax\)
+ *[a-f0-9]+:	c1 28 02             	shrl   \$0x2,\(%eax\)
+ *[a-f0-9]+:	d3 28                	shrl   %cl,\(%eax\)
+ *[a-f0-9]+:	ab                   	stos   %eax,%es:\(%edi\)
+ *[a-f0-9]+:	ab                   	stos   %eax,%es:\(%edi\)
   *[a-f0-9]+:	83 28 01             	subl   \$0x1,\(%eax\)
+ *[a-f0-9]+:	81 28 89 00 00 00    	subl   \$0x89,\(%eax\)
+ *[a-f0-9]+:	81 28 34 12 00 00    	subl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:	81 28 78 56 34 12    	subl   \$0x12345678,\(%eax\)
+ *[a-f0-9]+:	f7 00 89 00 00 00    	testl  \$0x89,\(%eax\)
+ *[a-f0-9]+:	f7 00 34 12 00 00    	testl  \$0x1234,\(%eax\)
+ *[a-f0-9]+:	f7 00 78 56 34 12    	testl  \$0x12345678,\(%eax\)
   *[a-f0-9]+:	c5 fb 2a 00          	vcvtsi2sdl \(%eax\),%xmm0,%xmm0
   *[a-f0-9]+:	62 f1 7f 08 2a 00    	vcvtsi2sdl \(%eax\),%xmm0,%xmm0
   *[a-f0-9]+:	c5 fa 2a 00          	vcvtsi2ssl \(%eax\),%xmm0,%xmm0
@@ -63,4 +137,7 @@  Disassembly of section .text:
   *[a-f0-9]+:	62 f1 7f 08 7b 00    	vcvtusi2sdl \(%eax\),%xmm0,%xmm0
   *[a-f0-9]+:	62 f1 7e 08 7b 00    	vcvtusi2ssl \(%eax\),%xmm0,%xmm0
   *[a-f0-9]+:	83 30 01             	xorl   \$0x1,\(%eax\)
+ *[a-f0-9]+:	81 30 89 00 00 00    	xorl   \$0x89,\(%eax\)
+ *[a-f0-9]+:	81 30 34 12 00 00    	xorl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:	81 30 78 56 34 12    	xorl   \$0x12345678,\(%eax\)
  #pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg32.l
@@ -0,0 +1,112 @@ 
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg32.s
+++ b/gas/testsuite/gas/i386/noreg32.s
@@ -1,16 +1,32 @@ 
  	.text
  noreg:
  	adc	$1, (%eax)
+	adc	$0x89, (%eax)
+	adc	$0x1234, (%eax)
+	adc	$0x12345678, (%eax)
  	add	$1, (%eax)
+	add	$0x89, (%eax)
+	add	$0x1234, (%eax)
+	add	$0x12345678, (%eax)
  	and	$1, (%eax)
+	and	$0x89, (%eax)
+	and	$0x1234, (%eax)
+	and	$0x12345678, (%eax)
  	bt	$1, (%eax)
  	btc	$1, (%eax)
  	btr	$1, (%eax)
  	bts	$1, (%eax)
  	call	*(%eax)
  	cmp	$1, (%eax)
+	cmp	$0x89, (%eax)
+	cmp	$0x1234, (%eax)
+	cmp	$0x12345678, (%eax)
+	cmps
+	cmps	%es:(%edi), (%esi)
  	cvtsi2sd (%eax), %xmm0
  	cvtsi2ss (%eax), %xmm0
+	dec	(%eax)
+	div	(%eax)
  	fadd	(%eax)
  	fcom	(%eax)
  	fcomp	(%eax)
@@ -34,22 +50,79 @@  noreg:
  	fstp	(%eax)
  	fsub	(%eax)
  	fsubr	(%eax)
+	idiv	(%eax)
+	imul	(%eax)
+	inc	(%eax)
+	ins
+	ins	%dx, %es:(%edi)
  	jmp	*(%eax)
  	lgdt	(%eax)
  	lidt	(%eax)
  	lldt	(%eax)
  	lmsw	(%eax)
+	lods
+	lods	(%esi)
  	ltr	(%eax)
+	mov	$0x12, (%eax)
+	mov	$0x1234, (%eax)
+	mov	$0x12345678, (%eax)
  	mov	%es, (%eax)
  	mov	(%eax), %es
+	movs
+	movs	(%esi), %es:(%edi)
+	mul	(%eax)
+	neg	(%eax)
+	not	(%eax)
  	or	$1, (%eax)
+	or	$0x89, (%eax)
+	or	$0x1234, (%eax)
+	or	$0x12345678, (%eax)
+	outs
+	outs	(%esi), %dx
  	pop	(%eax)
  	pop	%es
  	ptwrite	(%eax)
  	push	(%eax)
  	push	%es
+	rcl	$1, (%eax)
+	rcl	$2, (%eax)
+	rcl	%cl, (%eax)
+	rcr	$1, (%eax)
+	rcr	$2, (%eax)
+	rcr	%cl, (%eax)
+	rol	$1, (%eax)
+	rol	$2, (%eax)
+	rol	%cl, (%eax)
+	ror	$1, (%eax)
+	ror	$2, (%eax)
+	ror	%cl, (%eax)
  	sbb	$1, (%eax)
+	sbb	$0x89, (%eax)
+	sbb	$0x1234, (%eax)
+	sbb	$0x12345678, (%eax)
+	scas
+	scas	%es:(%edi)
+	sal	$1, (%eax)
+	sal	$2, (%eax)
+	sal	%cl, (%eax)
+	sar	$1, (%eax)
+	sar	$2, (%eax)
+	sar	%cl, (%eax)
+	shl	$1, (%eax)
+	shl	$2, (%eax)
+	shl	%cl, (%eax)
+	shr	$1, (%eax)
+	shr	$2, (%eax)
+	shr	%cl, (%eax)
+	stos
+	stos	%es:(%edi)
  	sub	$1, (%eax)
+	sub	$0x89, (%eax)
+	sub	$0x1234, (%eax)
+	sub	$0x12345678, (%eax)
+	test	$0x89, (%eax)
+	test	$0x1234, (%eax)
+	test	$0x12345678, (%eax)
  	vcvtsi2sd (%eax), %xmm0, %xmm0
  	{evex} vcvtsi2sd (%eax), %xmm0, %xmm0
  	vcvtsi2ss (%eax), %xmm0, %xmm0
@@ -57,3 +130,6 @@  noreg:
  	vcvtusi2sd (%eax), %xmm0, %xmm0
  	vcvtusi2ss (%eax), %xmm0, %xmm0
  	xor	$1, (%eax)
+	xor	$0x89, (%eax)
+	xor	$0x1234, (%eax)
+	xor	$0x12345678, (%eax)
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -1,3 +1,4 @@ 
+#as: -moperand-check=none
  #objdump: -dw
  #name: 64-bit insns not sizeable through register operands
  
@@ -7,16 +8,32 @@  Disassembly of section .text:
  
  0+ <noreg>:
   *[a-f0-9]+:	83 10 01             	adcl   \$0x1,\(%rax\)
+ *[a-f0-9]+:	81 10 89 00 00 00    	adcl   \$0x89,\(%rax\)
+ *[a-f0-9]+:	81 10 34 12 00 00    	adcl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:	81 10 78 56 34 12    	adcl   \$0x12345678,\(%rax\)
   *[a-f0-9]+:	83 00 01             	addl   \$0x1,\(%rax\)
+ *[a-f0-9]+:	81 00 89 00 00 00    	addl   \$0x89,\(%rax\)
+ *[a-f0-9]+:	81 00 34 12 00 00    	addl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:	81 00 78 56 34 12    	addl   \$0x12345678,\(%rax\)
   *[a-f0-9]+:	83 20 01             	andl   \$0x1,\(%rax\)
+ *[a-f0-9]+:	81 20 89 00 00 00    	andl   \$0x89,\(%rax\)
+ *[a-f0-9]+:	81 20 34 12 00 00    	andl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:	81 20 78 56 34 12    	andl   \$0x12345678,\(%rax\)
   *[a-f0-9]+:	0f ba 20 01          	btl    \$0x1,\(%rax\)
   *[a-f0-9]+:	0f ba 38 01          	btcl   \$0x1,\(%rax\)
   *[a-f0-9]+:	0f ba 30 01          	btrl   \$0x1,\(%rax\)
   *[a-f0-9]+:	0f ba 28 01          	btsl   \$0x1,\(%rax\)
   *[a-f0-9]+:	ff 10                	callq  \*\(%rax\)
   *[a-f0-9]+:	83 38 01             	cmpl   \$0x1,\(%rax\)
+ *[a-f0-9]+:	81 38 89 00 00 00    	cmpl   \$0x89,\(%rax\)
+ *[a-f0-9]+:	81 38 34 12 00 00    	cmpl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:	81 38 78 56 34 12    	cmpl   \$0x12345678,\(%rax\)
+ *[a-f0-9]+:	a7                   	cmpsl  %es:\(%rdi\),%ds:\(%rsi\)
+ *[a-f0-9]+:	a7                   	cmpsl  %es:\(%rdi\),%ds:\(%rsi\)
   *[a-f0-9]+:	f2 0f 2a 00          	cvtsi2sdl \(%rax\),%xmm0
   *[a-f0-9]+:	f3 0f 2a 00          	cvtsi2ssl \(%rax\),%xmm0
+ *[a-f0-9]+:	ff 08                	decl   \(%rax\)
+ *[a-f0-9]+:	f7 30                	divl   \(%rax\)
   *[a-f0-9]+:	d8 00                	fadds  \(%rax\)
   *[a-f0-9]+:	d8 10                	fcoms  \(%rax\)
   *[a-f0-9]+:	d8 18                	fcomps \(%rax\)
@@ -40,22 +57,79 @@  Disassembly of section .text:
   *[a-f0-9]+:	d9 18                	fstps  \(%rax\)
   *[a-f0-9]+:	d8 20                	fsubs  \(%rax\)
   *[a-f0-9]+:	d8 28                	fsubrs \(%rax\)
+ *[a-f0-9]+:	f7 38                	idivl  \(%rax\)
+ *[a-f0-9]+:	f7 28                	imull  \(%rax\)
+ *[a-f0-9]+:	ff 00                	incl   \(%rax\)
+ *[a-f0-9]+:	6d                   	insl   \(%dx\),%es:\(%rdi\)
+ *[a-f0-9]+:	6d                   	insl   \(%dx\),%es:\(%rdi\)
   *[a-f0-9]+:	ff 20                	jmpq   \*\(%rax\)
   *[a-f0-9]+:	0f 01 10             	lgdt   \(%rax\)
   *[a-f0-9]+:	0f 01 18             	lidt   \(%rax\)
   *[a-f0-9]+:	0f 00 10             	lldt   \(%rax\)
   *[a-f0-9]+:	0f 01 30             	lmsw   \(%rax\)
+ *[a-f0-9]+:	ad                   	lods   %ds:\(%rsi\),%eax
+ *[a-f0-9]+:	ad                   	lods   %ds:\(%rsi\),%eax
   *[a-f0-9]+:	0f 00 18             	ltr    \(%rax\)
+ *[a-f0-9]+:	c7 00 12 00 00 00    	movl   \$0x12,\(%rax\)
+ *[a-f0-9]+:	c7 00 34 12 00 00    	movl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:	c7 00 78 56 34 12    	movl   \$0x12345678,\(%rax\)
   *[a-f0-9]+:	8c 00                	mov    %es,\(%rax\)
   *[a-f0-9]+:	8e 00                	mov    \(%rax\),%es
+ *[a-f0-9]+:	a5                   	movsl  %ds:\(%rsi\),%es:\(%rdi\)
+ *[a-f0-9]+:	a5                   	movsl  %ds:\(%rsi\),%es:\(%rdi\)
+ *[a-f0-9]+:	f7 20                	mull   \(%rax\)
+ *[a-f0-9]+:	f7 18                	negl   \(%rax\)
+ *[a-f0-9]+:	f7 10                	notl   \(%rax\)
   *[a-f0-9]+:	83 08 01             	orl    \$0x1,\(%rax\)
+ *[a-f0-9]+:	81 08 89 00 00 00    	orl    \$0x89,\(%rax\)
+ *[a-f0-9]+:	81 08 34 12 00 00    	orl    \$0x1234,\(%rax\)
+ *[a-f0-9]+:	81 08 78 56 34 12    	orl    \$0x12345678,\(%rax\)
+ *[a-f0-9]+:	6f                   	outsl  %ds:\(%rsi\),\(%dx\)
+ *[a-f0-9]+:	6f                   	outsl  %ds:\(%rsi\),\(%dx\)
   *[a-f0-9]+:	8f 00                	popq   \(%rax\)
   *[a-f0-9]+:	0f a1                	popq   %fs
   *[a-f0-9]+:	f3 0f ae 20          	ptwritel \(%rax\)
   *[a-f0-9]+:	ff 30                	pushq  \(%rax\)
   *[a-f0-9]+:	0f a0                	pushq  %fs
+ *[a-f0-9]+:	d1 10                	rcll   \(%rax\)
+ *[a-f0-9]+:	c1 10 02             	rcll   \$0x2,\(%rax\)
+ *[a-f0-9]+:	d3 10                	rcll   %cl,\(%rax\)
+ *[a-f0-9]+:	d1 18                	rcrl   \(%rax\)
+ *[a-f0-9]+:	c1 18 02             	rcrl   \$0x2,\(%rax\)
+ *[a-f0-9]+:	d3 18                	rcrl   %cl,\(%rax\)
+ *[a-f0-9]+:	d1 00                	roll   \(%rax\)
+ *[a-f0-9]+:	c1 00 02             	roll   \$0x2,\(%rax\)
+ *[a-f0-9]+:	d3 00                	roll   %cl,\(%rax\)
+ *[a-f0-9]+:	d1 08                	rorl   \(%rax\)
+ *[a-f0-9]+:	c1 08 02             	rorl   \$0x2,\(%rax\)
+ *[a-f0-9]+:	d3 08                	rorl   %cl,\(%rax\)
   *[a-f0-9]+:	83 18 01             	sbbl   \$0x1,\(%rax\)
+ *[a-f0-9]+:	81 18 89 00 00 00    	sbbl   \$0x89,\(%rax\)
+ *[a-f0-9]+:	81 18 34 12 00 00    	sbbl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:	81 18 78 56 34 12    	sbbl   \$0x12345678,\(%rax\)
+ *[a-f0-9]+:	af                   	scas   %es:\(%rdi\),%eax
+ *[a-f0-9]+:	af                   	scas   %es:\(%rdi\),%eax
+ *[a-f0-9]+:	d1 20                	shll   \(%rax\)
+ *[a-f0-9]+:	c1 20 02             	shll   \$0x2,\(%rax\)
+ *[a-f0-9]+:	d3 20                	shll   %cl,\(%rax\)
+ *[a-f0-9]+:	d1 38                	sarl   \(%rax\)
+ *[a-f0-9]+:	c1 38 02             	sarl   \$0x2,\(%rax\)
+ *[a-f0-9]+:	d3 38                	sarl   %cl,\(%rax\)
+ *[a-f0-9]+:	d1 20                	shll   \(%rax\)
+ *[a-f0-9]+:	c1 20 02             	shll   \$0x2,\(%rax\)
+ *[a-f0-9]+:	d3 20                	shll   %cl,\(%rax\)
+ *[a-f0-9]+:	d1 28                	shrl   \(%rax\)
+ *[a-f0-9]+:	c1 28 02             	shrl   \$0x2,\(%rax\)
+ *[a-f0-9]+:	d3 28                	shrl   %cl,\(%rax\)
+ *[a-f0-9]+:	ab                   	stos   %eax,%es:\(%rdi\)
+ *[a-f0-9]+:	ab                   	stos   %eax,%es:\(%rdi\)
   *[a-f0-9]+:	83 28 01             	subl   \$0x1,\(%rax\)
+ *[a-f0-9]+:	81 28 89 00 00 00    	subl   \$0x89,\(%rax\)
+ *[a-f0-9]+:	81 28 34 12 00 00    	subl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:	81 28 78 56 34 12    	subl   \$0x12345678,\(%rax\)
+ *[a-f0-9]+:	f7 00 89 00 00 00    	testl  \$0x89,\(%rax\)
+ *[a-f0-9]+:	f7 00 34 12 00 00    	testl  \$0x1234,\(%rax\)
+ *[a-f0-9]+:	f7 00 78 56 34 12    	testl  \$0x12345678,\(%rax\)
   *[a-f0-9]+:	c5 fb 2a 00          	vcvtsi2sdl \(%rax\),%xmm0,%xmm0
   *[a-f0-9]+:	62 61 7f 08 2a 38    	vcvtsi2sdl \(%rax\),%xmm0,%xmm31
   *[a-f0-9]+:	c5 fa 2a 00          	vcvtsi2ssl \(%rax\),%xmm0,%xmm0
@@ -63,4 +137,7 @@  Disassembly of section .text:
   *[a-f0-9]+:	62 f1 7f 08 7b 00    	vcvtusi2sdl \(%rax\),%xmm0,%xmm0
   *[a-f0-9]+:	62 f1 7e 08 7b 00    	vcvtusi2ssl \(%rax\),%xmm0,%xmm0
   *[a-f0-9]+:	83 30 01             	xorl   \$0x1,\(%rax\)
+ *[a-f0-9]+:	81 30 89 00 00 00    	xorl   \$0x89,\(%rax\)
+ *[a-f0-9]+:	81 30 34 12 00 00    	xorl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:	81 30 78 56 34 12    	xorl   \$0x12345678,\(%rax\)
  #pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -0,0 +1,121 @@ 
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `ptwrite'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `vcvtusi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtusi2ss'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -1,16 +1,32 @@ 
  	.text
  noreg:
  	adc	$1, (%rax)
+	adc	$0x89, (%rax)
+	adc	$0x1234, (%rax)
+	adc	$0x12345678, (%rax)
  	add	$1, (%rax)
+	add	$0x89, (%rax)
+	add	$0x1234, (%rax)
+	add	$0x12345678, (%rax)
  	and	$1, (%rax)
+	and	$0x89, (%rax)
+	and	$0x1234, (%rax)
+	and	$0x12345678, (%rax)
  	bt	$1, (%rax)
  	btc	$1, (%rax)
  	btr	$1, (%rax)
  	bts	$1, (%rax)
  	call	*(%rax)
  	cmp	$1, (%rax)
+	cmp	$0x89, (%rax)
+	cmp	$0x1234, (%rax)
+	cmp	$0x12345678, (%rax)
+	cmps
+	cmps	%es:(%rdi), (%rsi)
  	cvtsi2sd (%rax), %xmm0
  	cvtsi2ss (%rax), %xmm0
+	dec	(%rax)
+	div	(%rax)
  	fadd	(%rax)
  	fcom	(%rax)
  	fcomp	(%rax)
@@ -34,22 +50,79 @@  noreg:
  	fstp	(%rax)
  	fsub	(%rax)
  	fsubr	(%rax)
+	idiv	(%rax)
+	imul	(%rax)
+	inc	(%rax)
+	ins
+	ins	%dx, %es:(%rdi)
  	jmp	*(%rax)
  	lgdt	(%rax)
  	lidt	(%rax)
  	lldt	(%rax)
  	lmsw	(%rax)
+	lods
+	lods	(%rsi)
  	ltr	(%rax)
+	mov	$0x12, (%rax)
+	mov	$0x1234, (%rax)
+	mov	$0x12345678, (%rax)
  	mov	%es, (%rax)
  	mov	(%rax), %es
+	movs
+	movs	(%rsi), %es:(%rdi)
+	mul	(%rax)
+	neg	(%rax)
+	not	(%rax)
  	or	$1, (%rax)
+	or	$0x89, (%rax)
+	or	$0x1234, (%rax)
+	or	$0x12345678, (%rax)
+	outs
+	outs	(%rsi), %dx
  	pop	(%rax)
  	pop	%fs
  	ptwrite	(%rax)
  	push	(%rax)
  	push	%fs
+	rcl	$1, (%rax)
+	rcl	$2, (%rax)
+	rcl	%cl, (%rax)
+	rcr	$1, (%rax)
+	rcr	$2, (%rax)
+	rcr	%cl, (%rax)
+	rol	$1, (%rax)
+	rol	$2, (%rax)
+	rol	%cl, (%rax)
+	ror	$1, (%rax)
+	ror	$2, (%rax)
+	ror	%cl, (%rax)
  	sbb	$1, (%rax)
+	sbb	$0x89, (%rax)
+	sbb	$0x1234, (%rax)
+	sbb	$0x12345678, (%rax)
+	scas
+	scas	%es:(%rdi)
+	sal	$1, (%rax)
+	sal	$2, (%rax)
+	sal	%cl, (%rax)
+	sar	$1, (%rax)
+	sar	$2, (%rax)
+	sar	%cl, (%rax)
+	shl	$1, (%rax)
+	shl	$2, (%rax)
+	shl	%cl, (%rax)
+	shr	$1, (%rax)
+	shr	$2, (%rax)
+	shr	%cl, (%rax)
+	stos
+	stos	%es:(%rdi)
  	sub	$1, (%rax)
+	sub	$0x89, (%rax)
+	sub	$0x1234, (%rax)
+	sub	$0x12345678, (%rax)
+	test	$0x89, (%rax)
+	test	$0x1234, (%rax)
+	test	$0x12345678, (%rax)
  	vcvtsi2sd (%rax), %xmm0, %xmm0
  	vcvtsi2sd (%rax), %xmm0, %xmm31
  	vcvtsi2ss (%rax), %xmm0, %xmm0
@@ -57,3 +130,6 @@  noreg:
  	vcvtusi2sd (%rax), %xmm0, %xmm0
  	vcvtusi2ss (%rax), %xmm0, %xmm0
  	xor	$1, (%rax)
+	xor	$0x89, (%rax)
+	xor	$0x1234, (%rax)
+	xor	$0x12345678, (%rax)
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -211,8 +211,8 @@  foo:
   fistl  0x90909090(%eax)
   fcoml  0x90909090(%eax)
   fstl   0x90909090(%eax)
- ficom  0x90909090(%eax)
- fist   0x90909090(%eax)
+ ficoms 0x90909090(%eax)
+ fists  0x90909090(%eax)
   loopne .+2-0x70
   loope  .+2-0x70
   loop   .+2-0x70
--- a/gas/testsuite/gas/i386/sse-noavx.d
+++ b/gas/testsuite/gas/i386/sse-noavx.d
@@ -15,7 +15,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2c dc          	cvttpd2pi %xmm4,%mm3
  [ 	]*[a-f0-9]+:	0f 2c dc             	cvttps2pi %xmm4,%mm3
  [ 	]*[a-f0-9]+:	df 08                	fisttps \(%eax\)
-[ 	]*[a-f0-9]+:	df 08                	fisttps \(%eax\)
  [ 	]*[a-f0-9]+:	db 08                	fisttpl \(%eax\)
  [ 	]*[a-f0-9]+:	dd 08                	fisttpll \(%eax\)
  [ 	]*[a-f0-9]+:	0f ae e8             	lfence
--- a/gas/testsuite/gas/i386/sse-noavx.s
+++ b/gas/testsuite/gas/i386/sse-noavx.s
@@ -9,7 +9,6 @@  _start:
   cvtps2pi	%xmm7,%mm6
   cvttpd2pi	%xmm4,%mm3
   cvttps2pi	%xmm4,%mm3
- fisttp (%eax)
   fisttps (%eax)
   fisttpl (%eax)
   fisttpll (%eax)
--- a/gas/testsuite/gas/i386/sse3.s
+++ b/gas/testsuite/gas/i386/sse3.s
@@ -6,7 +6,7 @@  foo:
  	addsubpd	%xmm2,%xmm1
  	addsubps	(%ebx),%xmm2
  	addsubps	%xmm4,%xmm3
-	fisttp		0x90909090(%eax)
+	fisttps		0x90909090(%eax)
  	fisttpl		0x90909090(%eax)
  	fisttpll	0x90909090(%eax)
  	haddpd		0x0(%ebp),%xmm4
--- a/gas/testsuite/gas/i386/x86-64-avx-scalar.s
+++ b/gas/testsuite/gas/i386/x86-64-avx-scalar.s
@@ -234,9 +234,9 @@  _start:
  
  # Tests for op regl/mem32, xmm, xmm
  	vcvtsi2sd %ecx,%xmm4,%xmm6
-	vcvtsi2sd (%rcx),%xmm4,%xmm6
+	vcvtsi2sdl (%rcx),%xmm4,%xmm6
  	vcvtsi2ss %ecx,%xmm4,%xmm6
-	vcvtsi2ss (%rcx),%xmm4,%xmm6
+	vcvtsi2ssl (%rcx),%xmm4,%xmm6
  
  # Tests for op imm8, xmm/mem32, xmm, xmm
  	vcmpss $7,%xmm4,%xmm6,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-avx.s
+++ b/gas/testsuite/gas/i386/x86-64-avx.s
@@ -1222,9 +1222,9 @@  _start:
  
  # Tests for op regl/mem32, xmm, xmm
  	vcvtsi2sd %ecx,%xmm4,%xmm6
-	vcvtsi2sd (%rcx),%xmm4,%xmm6
+	vcvtsi2sdl (%rcx),%xmm4,%xmm6
  	vcvtsi2ss %ecx,%xmm4,%xmm6
-	vcvtsi2ss (%rcx),%xmm4,%xmm6
+	vcvtsi2ssl (%rcx),%xmm4,%xmm6
  
  # Tests for op imm8, xmm/mem32, xmm, xmm
  	vcmpss $7,%xmm4,%xmm6,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-bundle.s
+++ b/gas/testsuite/gas/i386/x86-64-bundle.s
@@ -58,7 +58,7 @@ 
  	and $3,%eax
  .endm
  .macro test_4
-	lock and $3,(%rax)
+	lock andl $3,(%rax)
  .endm
  .macro test_5
  	mov $0x11223344,%eax
--- a/gas/testsuite/gas/i386/x86-64-lock-1.s
+++ b/gas/testsuite/gas/i386/x86-64-lock-1.s
@@ -3,17 +3,17 @@ 
  	.text
  foo:
  	lock add %eax, (%rbx)
-	lock add $0x64, (%rbx)
+	lock addl $0x64, (%rbx)
  	lock adc %eax, (%rbx)
-	lock adc $0x64, (%rbx)
+	lock adcl $0x64, (%rbx)
  	lock and %eax, (%rbx)
-	lock and $0x64, (%rbx)
+	lock andl $0x64, (%rbx)
  	lock btc %eax, (%rbx)
-	lock btc $0x64, (%rbx)
+	lock btcl $0x64, (%rbx)
  	lock btr %eax, (%rbx)
-	lock btr $0x64, (%rbx)
+	lock btrl $0x64, (%rbx)
  	lock bts %eax, (%rbx)
-	lock bts $0x64, (%rbx)
+	lock btsl $0x64, (%rbx)
  	lock cmpxchg %eax,(%rbx)
  	lock cmpxchg8b (%rbx)
  	lock cmpxchg16b (%rbx)
@@ -22,16 +22,16 @@  foo:
  	lock negl (%rbx)
  	lock notl (%rbx)
  	lock or %eax, (%rbx)
-	lock or $0x64, (%rbx)
+	lock orl $0x64, (%rbx)
  	lock sbb %eax, (%rbx)
-	lock sbb $0x64, (%rbx)
+	lock sbbl $0x64, (%rbx)
  	lock sub %eax, (%rbx)
-	lock sub $0x64, (%rbx)
+	lock subl $0x64, (%rbx)
  	lock xadd %eax, (%rbx)
  	lock xchg (%rbx), %eax
  	lock xchg %eax, (%rbx)
  	lock xor %eax, (%rbx)
-	lock xor $0x64, (%rbx)
+	lock xorl $0x64, (%rbx)
  
  	.intel_syntax noprefix
  	lock add DWORD PTR [rbx],eax
--- a/gas/testsuite/gas/i386/x86-64-nops.d
+++ b/gas/testsuite/gas/i386/x86-64-nops.d
@@ -41,7 +41,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	0f 1d 04 59          	nopl   \(%rcx,%rbx,2\)
  [ 	]*[a-f0-9]+:	0f 1e 04 59          	nopl   \(%rcx,%rbx,2\)
  [ 	]*[a-f0-9]+:	0f 1f 04 59          	nopl   \(%rcx,%rbx,2\)
-[ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%rax\)
  [ 	]*[a-f0-9]+:	48 0f 1f c0          	nop    %rax
  [ 	]*[a-f0-9]+:	0f 1f c0             	nop    %eax
  [ 	]*[a-f0-9]+:	66 0f 1f c0          	nop    %ax
@@ -51,7 +50,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	48 0f 1f c0          	nop    %rax
  [ 	]*[a-f0-9]+:	0f 1f c0             	nop    %eax
  [ 	]*[a-f0-9]+:	66 0f 1f c0          	nop    %ax
-[ 	]*[a-f0-9]+:	41 0f 1f 02          	nopl   \(%r10\)
  [ 	]*[a-f0-9]+:	49 0f 1f c2          	nop    %r10
  [ 	]*[a-f0-9]+:	41 0f 1f c2          	nop    %r10d
  [ 	]*[a-f0-9]+:	66 41 0f 1f c2       	nop    %r10w
--- a/gas/testsuite/gas/i386/x86-64-nops.s
+++ b/gas/testsuite/gas/i386/x86-64-nops.s
@@ -44,7 +44,6 @@ 
  	.byte 0x0f, 0x1e, 0x04, 0x59
  	.byte 0x0f, 0x1f, 0x04, 0x59
  
-	nop (%rax)
  	nop %rax
  	nop %eax
  	nop %ax
@@ -54,7 +53,6 @@ 
  	nopq %rax
  	nopl %eax
  	nopw %ax
-	nop (%r10)
  	nop %r10
  	nop %r10d
  	nop %r10w
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -175,48 +175,48 @@ 
  	CVTTSS2SIq %xmm0,%r8	      #	 --  --	 F3 4C	 0f 2c c0	                 ; OVR 128-bit media instruction override Result is sign extended                          REX for 64-bit operand size                 REX to access upper reg.
  
          # CVTSI2SS
-	CVTSI2SS  (%r8),%xmm0	      #	 --  --	 F3 41	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper reg.
-	CVTSI2SS  (%rax),%xmm0	      #	 --  --	 F3 --	 0f 2a 00	 ; OVR 128-bit media instruction override
-	CVTSI2SS  (%r8),%xmm15	      #	 --  --	 F3 45	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
-	CVTSI2SS  (%rax),%xmm15	      #	 --  --	 F3 44	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
-	CVTSI2SS  (%r8),%xmm8	      #	 --  --	 F3 45	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
-	CVTSI2SS  (%rax),%xmm8	      #	 --  --	 F3 44	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
-	CVTSI2SS  (%r8),%xmm7	      #	 --  --	 F3 41	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper reg.
-	CVTSI2SS  (%rax),%xmm7	      #	 --  --	 F3 --	 0f 2a 38	                 ; OVR 128-bit media instruction override
+	CVTSI2SSl (%r8),%xmm0	      #	 --  --	 F3 41	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper reg.
+	CVTSI2SSl (%rax),%xmm0	      #	 --  --	 F3 --	 0f 2a 00	 ; OVR 128-bit media instruction override
+	CVTSI2SSl (%r8),%xmm15	      #	 --  --	 F3 45	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
+	CVTSI2SSl (%rax),%xmm15	      #	 --  --	 F3 44	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
+	CVTSI2SSl (%r8),%xmm8	      #	 --  --	 F3 45	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
+	CVTSI2SSl (%rax),%xmm8	      #	 --  --	 F3 44	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
+	CVTSI2SSl (%r8),%xmm7	      #	 --  --	 F3 41	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper reg.
+	CVTSI2SSl (%rax),%xmm7	      #	 --  --	 F3 --	 0f 2a 38	                 ; OVR 128-bit media instruction override
  	CVTSI2SS  %eax,%xmm0	      #	 --  --	 F3 --	 0f 2a c0	                 ; OVR 128-bit media instruction override
  	CVTSI2SS  %eax,%xmm15	      #	 --  --	 F3 44	 0f 2a f8	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
  	CVTSI2SS  %eax,%xmm8	      #	 --  --	 F3 44	 0f 2a c0	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
  	CVTSI2SS  %eax,%xmm7	      #	 --  --	 F3 --	 0f 2a f8	                 ; OVR 128-bit media instruction override
-	CVTSI2SS  (%r8),%xmm0	      #	 --  --	 F3 41	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper reg.
-	CVTSI2SS  (%rax),%xmm0	      #	 --  --	 F3 --	 0f 2a 00	                 ; OVR 128-bit media instruction override
-	CVTSI2SS  (%r8),%xmm15	      #	 --  --	 F3 45	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
-	CVTSI2SS  (%rax),%xmm15	      #	 --  --	 F3 44	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
-	CVTSI2SS  (%r8),%xmm8	      #	 --  --	 F3 45	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
-	CVTSI2SS  (%rax),%xmm8	      #	 --  --	 F3 44	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
-	CVTSI2SS  (%r8),%xmm7	      #	 --  --	 F3 41	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper reg.
-	CVTSI2SS  (%rax),%xmm7	      #	 --  --	 F3 --	 0f 2a 38	                 ; OVR 128-bit media instruction override
+	CVTSI2SSl (%r8),%xmm0	      #	 --  --	 F3 41	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper reg.
+	CVTSI2SSl (%rax),%xmm0	      #	 --  --	 F3 --	 0f 2a 00	                 ; OVR 128-bit media instruction override
+	CVTSI2SSl (%r8),%xmm15	      #	 --  --	 F3 45	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
+	CVTSI2SSl (%rax),%xmm15	      #	 --  --	 F3 44	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
+	CVTSI2SSl (%r8),%xmm8	      #	 --  --	 F3 45	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
+	CVTSI2SSl (%rax),%xmm8	      #	 --  --	 F3 44	 0f 2a 00	                 ; OVR 128-bit media instruction override REX to access upper XMM reg
+	CVTSI2SSl (%r8),%xmm7	      #	 --  --	 F3 41	 0f 2a 38	                 ; OVR 128-bit media instruction override REX to access upper reg.
+	CVTSI2SSl (%rax),%xmm7	      #	 --  --	 F3 --	 0f 2a 38	                 ; OVR 128-bit media instruction override
  
          # CVTSI2SD
-	CVTSI2SD  (%r8),%xmm0	      #	 --  --	 F2 41	 0F 2A 00			 ; REX to access upper reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%rax),%xmm0	      #	 --  --	 F2 --	 0F 2A 00			 ; OVR 128bit MMinstr.
-	CVTSI2SD  (%r8),%xmm15	      #	 --  --	 F2 45	 0F 2A 38			 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%rax),%xmm15	      #	 --  --	 F2 44	 0F 2A 38			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%r8),%xmm8	      #	 --  --	 F2 45	 0F 2A 00			 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%rax),%xmm8	      #	 --  --	 F2 44	 0F 2A 00			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%r8),%xmm7	      #	 --  --	 F2 41	 0F 2A 38			 ; REX to access upper reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%rax),%xmm7	      #	 --  --	 F2 --	 0F 2A 38			 ; OVR 128bit MMinstr.
+	CVTSI2SDl (%r8),%xmm0	      #	 --  --	 F2 41	 0F 2A 00			 ; REX to access upper reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%rax),%xmm0	      #	 --  --	 F2 --	 0F 2A 00			 ; OVR 128bit MMinstr.
+	CVTSI2SDl (%r8),%xmm15	      #	 --  --	 F2 45	 0F 2A 38			 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%rax),%xmm15	      #	 --  --	 F2 44	 0F 2A 38			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%r8),%xmm8	      #	 --  --	 F2 45	 0F 2A 00			 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%rax),%xmm8	      #	 --  --	 F2 44	 0F 2A 00			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%r8),%xmm7	      #	 --  --	 F2 41	 0F 2A 38			 ; REX to access upper reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%rax),%xmm7	      #	 --  --	 F2 --	 0F 2A 38			 ; OVR 128bit MMinstr.
  	CVTSI2SD  %eax,%xmm0	      #	 --  --	 F2 --	 0F 2A C0			 ; OVR 128bit MMinstr.
  	CVTSI2SD  %eax,%xmm15	      #	 --  --	 F2 44	 0F 2A F8			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
  	CVTSI2SD  %eax,%xmm8	      #	 --  --	 F2 44	 0F 2A C0			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
  	CVTSI2SD  %eax,%xmm7	      #	 --  --	 F2 --	 0F 2A F8			 ; OVR 128bit MMinstr.
-	CVTSI2SD  (%r8),%xmm0	      #	 --  --	 F2 41	 0F 2A 00			 ; REX to access upper reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%rax),%xmm0	      #	 --  --	 F2 --	 0F 2A 00			 ; OVR 128bit MMinstr.
-	CVTSI2SD  (%r8),%xmm15	      #	 --  --	 F2 45	 0F 2A 38			 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%rax),%xmm15	      #	 --  --	 F2 44	 0F 2A 38			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%r8),%xmm8	      #	 --  --	 F2 45	 0F 2A 00			 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%rax),%xmm8	      #	 --  --	 F2 44	 0F 2A 00			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%r8),%xmm7	      #	 --  --	 F2 41	 0F 2A 38			 ; REX to access upper reg. OVR 128bit MMinstr.
-	CVTSI2SD  (%rax),%xmm7	      #	 --  --	 F2 --	 0F 2A 38			 ; OVR 128bit MMinstr.
+	CVTSI2SDl (%r8),%xmm0	      #	 --  --	 F2 41	 0F 2A 00			 ; REX to access upper reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%rax),%xmm0	      #	 --  --	 F2 --	 0F 2A 00			 ; OVR 128bit MMinstr.
+	CVTSI2SDl (%r8),%xmm15	      #	 --  --	 F2 45	 0F 2A 38			 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%rax),%xmm15	      #	 --  --	 F2 44	 0F 2A 38			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%r8),%xmm8	      #	 --  --	 F2 45	 0F 2A 00			 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%rax),%xmm8	      #	 --  --	 F2 44	 0F 2A 00			 ; REX to access upper XMM reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%r8),%xmm7	      #	 --  --	 F2 41	 0F 2A 38			 ; REX to access upper reg. OVR 128bit MMinstr.
+	CVTSI2SDl (%rax),%xmm7	      #	 --  --	 F2 --	 0F 2A 38			 ; OVR 128bit MMinstr.
  
  	# MOVD
  	MOVD (%r8),%xmm0	      #	 --  --	 66 41	 0F 6E 00			 ; REX to access upper reg. Data128 = ZEXT(Data32). OVR 128bit MMinstr.
--- a/gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
@@ -14,7 +14,6 @@  Disassembly of section \.text:
   +[a-f0-9]+:	f3 48 0f ae e1       	ptwrite rcx
   +[a-f0-9]+:	f3 48 0f ae e1       	ptwrite rcx
   +[a-f0-9]+:	f3 0f ae 21          	ptwrite DWORD PTR \[rcx\]
- +[a-f0-9]+:	f3 0f ae 21          	ptwrite DWORD PTR \[rcx\]
   +[a-f0-9]+:	f3 48 0f ae 21       	ptwrite QWORD PTR \[rcx\]
   +[a-f0-9]+:	f3 0f ae e1          	ptwrite ecx
   +[a-f0-9]+:	f3 48 0f ae e1       	ptwrite rcx
--- a/gas/testsuite/gas/i386/x86-64-ptwrite.d
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite.d
@@ -14,7 +14,6 @@  Disassembly of section \.text:
   +[a-f0-9]+:	f3 48 0f ae e1       	ptwrite %rcx
   +[a-f0-9]+:	f3 48 0f ae e1       	ptwrite %rcx
   +[a-f0-9]+:	f3 0f ae 21          	ptwritel \(%rcx\)
- +[a-f0-9]+:	f3 0f ae 21          	ptwritel \(%rcx\)
   +[a-f0-9]+:	f3 48 0f ae 21       	ptwriteq \(%rcx\)
   +[a-f0-9]+:	f3 0f ae e1          	ptwrite %ecx
   +[a-f0-9]+:	f3 48 0f ae e1       	ptwrite %rcx
--- a/gas/testsuite/gas/i386/x86-64-ptwrite.s
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite.s
@@ -6,7 +6,6 @@  _start:
  	ptwritel %ecx
  	ptwrite %rcx
  	ptwriteq %rcx
-	ptwrite (%rcx)
  	ptwritel (%rcx)
  	ptwriteq (%rcx)
  
--- a/gas/testsuite/gas/i386/x86-64-simd-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-intel.d
@@ -25,8 +25,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	f2 48 0f 2a c8       	cvtsi2sd xmm1,rax
  [ 	]*[a-f0-9]+:	f3 0f 2a 08          	cvtsi2ss xmm1,DWORD PTR \[rax\]
  [ 	]*[a-f0-9]+:	f2 0f 2a 08          	cvtsi2sd xmm1,DWORD PTR \[rax\]
-[ 	]*[a-f0-9]+:	f3 0f 2a 08          	cvtsi2ss xmm1,DWORD PTR \[rax\]
-[ 	]*[a-f0-9]+:	f2 0f 2a 08          	cvtsi2sd xmm1,DWORD PTR \[rax\]
  [ 	]*[a-f0-9]+:	f3 48 0f 2a 08       	cvtsi2ss xmm1,QWORD PTR \[rax\]
  [ 	]*[a-f0-9]+:	f2 48 0f 2a 08       	cvtsi2sd xmm1,QWORD PTR \[rax\]
  [ 	]*[a-f0-9]+:	f2 0f 7c 0d 78 56 34 12 	haddps xmm1,XMMWORD PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
--- a/gas/testsuite/gas/i386/x86-64-simd-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-suffix.d
@@ -25,8 +25,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	f2 48 0f 2a c8       	cvtsi2sdq %rax,%xmm1
  [ 	]*[a-f0-9]+:	f3 0f 2a 08          	cvtsi2ssl \(%rax\),%xmm1
  [ 	]*[a-f0-9]+:	f2 0f 2a 08          	cvtsi2sdl \(%rax\),%xmm1
-[ 	]*[a-f0-9]+:	f3 0f 2a 08          	cvtsi2ssl \(%rax\),%xmm1
-[ 	]*[a-f0-9]+:	f2 0f 2a 08          	cvtsi2sdl \(%rax\),%xmm1
  [ 	]*[a-f0-9]+:	f3 48 0f 2a 08       	cvtsi2ssq \(%rax\),%xmm1
  [ 	]*[a-f0-9]+:	f2 48 0f 2a 08       	cvtsi2sdq \(%rax\),%xmm1
  [ 	]*[a-f0-9]+:	f2 0f 7c 0d 78 56 34 12 	haddps 0x12345678\(%rip\),%xmm1        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
--- a/gas/testsuite/gas/i386/x86-64-simd.d
+++ b/gas/testsuite/gas/i386/x86-64-simd.d
@@ -24,8 +24,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	f2 48 0f 2a c8       	cvtsi2sd %rax,%xmm1
  [ 	]*[a-f0-9]+:	f3 0f 2a 08          	cvtsi2ssl \(%rax\),%xmm1
  [ 	]*[a-f0-9]+:	f2 0f 2a 08          	cvtsi2sdl \(%rax\),%xmm1
-[ 	]*[a-f0-9]+:	f3 0f 2a 08          	cvtsi2ssl \(%rax\),%xmm1
-[ 	]*[a-f0-9]+:	f2 0f 2a 08          	cvtsi2sdl \(%rax\),%xmm1
  [ 	]*[a-f0-9]+:	f3 48 0f 2a 08       	cvtsi2ssq \(%rax\),%xmm1
  [ 	]*[a-f0-9]+:	f2 48 0f 2a 08       	cvtsi2sdq \(%rax\),%xmm1
  [ 	]*[a-f0-9]+:	f2 0f 7c 0d 78 56 34 12 	haddps 0x12345678\(%rip\),%xmm1        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
--- a/gas/testsuite/gas/i386/x86-64-simd.s
+++ b/gas/testsuite/gas/i386/x86-64-simd.s
@@ -15,8 +15,6 @@  _start:
  	cvtsi2sd %rax, %xmm1
  	cvtsi2ssq %rax, %xmm1
  	cvtsi2sdq %rax, %xmm1
-	cvtsi2ss (%rax), %xmm1
-	cvtsi2sd (%rax), %xmm1
  	cvtsi2ssl (%rax), %xmm1
  	cvtsi2sdl (%rax), %xmm1
  	cvtsi2ssq (%rax), %xmm1
--- a/gas/testsuite/gas/i386/x86-64-sse-noavx.d
+++ b/gas/testsuite/gas/i386/x86-64-sse-noavx.d
@@ -16,7 +16,6 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2c dc          	cvttpd2pi %xmm4,%mm3
  [ 	]*[a-f0-9]+:	0f 2c dc             	cvttps2pi %xmm4,%mm3
  [ 	]*[a-f0-9]+:	df 08                	fisttps \(%rax\)
-[ 	]*[a-f0-9]+:	df 08                	fisttps \(%rax\)
  [ 	]*[a-f0-9]+:	db 08                	fisttpl \(%rax\)
  [ 	]*[a-f0-9]+:	dd 08                	fisttpll \(%rax\)
  [ 	]*[a-f0-9]+:	0f ae e8             	lfence
--- a/gas/testsuite/gas/i386/x86-64-sse-noavx.s
+++ b/gas/testsuite/gas/i386/x86-64-sse-noavx.s
@@ -10,7 +10,6 @@  _start:
   cvtps2pi	%xmm7,%mm6
   cvttpd2pi	%xmm4,%mm3
   cvttps2pi	%xmm4,%mm3
- fisttp (%rax)
   fisttps (%rax)
   fisttpl (%rax)
   fisttpll (%rax)
--- a/gas/testsuite/gas/i386/x86-64-sse2avx.s
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx.s
@@ -720,9 +720,9 @@  _start:
  
  # Tests for op regl/mem32, xmm[, xmm]
  	cvtsi2sd %ecx,%xmm4
-	cvtsi2sd (%rcx),%xmm4
+	cvtsi2sdl (%rcx),%xmm4
  	cvtsi2ss %ecx,%xmm4
-	cvtsi2ss (%rcx),%xmm4
+	cvtsi2ssl (%rcx),%xmm4
  
  # Tests for op imm8, xmm/mem32, xmm[, xmm]
  	cmpss $100,%xmm4,%xmm6
--- a/gas/testsuite/gas/i386/x86-64-sse3.s
+++ b/gas/testsuite/gas/i386/x86-64-sse3.s
@@ -6,7 +6,7 @@  foo:
  	addsubpd	%xmm2,%xmm1
  	addsubps	(%rbx),%xmm2
  	addsubps	%xmm4,%xmm3
-	fisttp		0x909090(%rax)
+	fisttps		0x909090(%rax)
  	fisttpl		0x909090(%rax)
  	fisttpll	0x909090(%rax)
  	haddpd		0x0(%rbp),%xmm4
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -348,15 +348,15 @@  lcall, 1, 0xff, 0x3, 1, 0, Modrm|Default
  jmp, 1, 0xeb, None, 1, CpuNo64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
  jmp, 1, 0xeb, None, 1, Cpu64, AMD64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32S }
  jmp, 1, 0xeb, None, 1, Cpu64, Intel64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp32S }
-jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|JumpAbsolute }
-jmp, 1, 0xff, 0x4, 1, Cpu64, AMD64|Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|JumpAbsolute }
-jmp, 1, 0xff, 0x4, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Qword|Unspecified|BaseIndex|JumpAbsolute }
+jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|JumpAbsolute }
+jmp, 1, 0xff, 0x4, 1, Cpu64, AMD64|Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|JumpAbsolute }
+jmp, 1, 0xff, 0x4, 1, Cpu64, Intel64|Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Qword|Unspecified|BaseIndex|JumpAbsolute }
  // Intel Syntax.
-jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
+jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
  // Intel Syntax.
-jmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex|JumpAbsolute }
-ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
-ljmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|JumpAbsolute }
+jmp, 1, 0xff, 0x5, 1, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex|JumpAbsolute }
+ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
+ljmp, 1, 0xff, 0x5, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|JumpAbsolute }
  
  ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { 0 }
  ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
@@ -414,16 +414,16 @@  jrcxz, 1, 0xe3, None, 1, Cpu64, JumpByte
  // %cx rather than %ecx for the loop count, so the `w' form of these
  // instructions emit an address size prefix rather than a data size
  //  prefix.
-loop, 1, 0xe2, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loop, 1, 0xe2, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
-loopz, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopz, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
-loope, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loope, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
-loopnz, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopnz, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
-loopne, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopne, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
+loop, 1, 0xe2, None, 1, CpuNo64, JumpByte|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
+loop, 1, 0xe2, None, 1, Cpu64, JumpByte|DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
+loopz, 1, 0xe1, None, 1, CpuNo64, JumpByte|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
+loopz, 1, 0xe1, None, 1, Cpu64, JumpByte|DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
+loope, 1, 0xe1, None, 1, CpuNo64, JumpByte|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
+loope, 1, 0xe1, None, 1, Cpu64, JumpByte|DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
+loopnz, 1, 0xe0, None, 1, CpuNo64, JumpByte|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
+loopnz, 1, 0xe0, None, 1, Cpu64, JumpByte|DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
+loopne, 1, 0xe0, None, 1, CpuNo64, JumpByte|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
+loopne, 1, 0xe0, None, 1, Cpu64, JumpByte|DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
  
  // Set byte on flag instructions.
  seto, 1, 0xf90, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex }
@@ -526,18 +526,18 @@  nop, 0, 0x90, None, 1, 0, No_bSuf|No_wSu
  // Protection control.
  arpl, 2, 0x63, None, 1, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
  lar, 2, 0xf02, None, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lgdt, 1, 0xf01, 0x2, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
+lgdt, 1, 0xf01, 0x2, 2, Cpu286|CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
  lgdt, 1, 0xf01, 0x2, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-lidt, 1, 0xf01, 0x3, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
+lidt, 1, 0xf01, 0x3, 2, Cpu286|CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
  lidt, 1, 0xf01, 0x3, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
  lldt, 1, 0xf00, 0x2, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
  lmsw, 1, 0xf01, 0x6, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
  lsl, 2, 0xf03, None, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
  ltr, 1, 0xf00, 0x3, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
  
-sgdt, 1, 0xf01, 0x0, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
+sgdt, 1, 0xf01, 0x0, 2, Cpu286|CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
  sgdt, 1, 0xf01, 0x0, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-sidt, 1, 0xf01, 0x1, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
+sidt, 1, 0xf01, 0x1, 2, Cpu286|CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
  sidt, 1, 0xf01, 0x1, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
  sldt, 1, 0xf00, 0x0, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64 }
  sldt, 1, 0xf00, 0x0, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }