[03/10] x86: produce suffix in suffix-always mode for {,V}CVT{,T}S{S,D}2SI

Message ID 0cac45ac-9339-bed6-7a90-0a643cf48e0f@suse.com
State New
Headers show
Series
  • x86: operand size handling improvements
Related show

Commit Message

Jan Beulich Aug. 6, 2019, 2:25 p.m.
Not doing so is simple inconsistent - the mode is specifically intended
to emit suffixes wherever applicable.

gas/
2019-08-XX  Jan Beulich  <jbeulich@suse.com>

	* testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,
	testsuite/gas/i386/simd-suffix.d,
	testsuite/gas/i386/x86-64-simd-suffix.d: Adjust expectations.

opcodes/
2019-08-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-dis-evex-prefix.h (vcvtss2si, vcvtsd2si, vcvttss2si,
	vcvttsd2si, vcvtss2usi, vcvtsd2usi, vcvttss2usi, and
	vcvttsd2usi): Add S suffix.
	i386-dis.c (prefix_table): Add S suffix to cvtss2si, cvtsd2si,
	cvttss2si, cvttsd2si, vcvtss2si, vcvtsd2si, vcvttss2si, and
	vcvttsd2si.

Comments

H.J. Lu Aug. 6, 2019, 7:41 p.m. | #1
On Tue, Aug 6, 2019 at 7:25 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> Not doing so is simple inconsistent - the mode is specifically intended

> to emit suffixes wherever applicable.

>

> gas/

> 2019-08-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,

>         testsuite/gas/i386/simd-suffix.d,

>         testsuite/gas/i386/x86-64-simd-suffix.d: Adjust expectations.

>

> opcodes/

> 2019-08-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-dis-evex-prefix.h (vcvtss2si, vcvtsd2si, vcvttss2si,

>         vcvttsd2si, vcvtss2usi, vcvtsd2usi, vcvttss2usi, and

>         vcvttsd2usi): Add S suffix.

>         i386-dis.c (prefix_table): Add S suffix to cvtss2si, cvtsd2si,

>         cvttss2si, cvttsd2si, vcvtss2si, vcvtsd2si, vcvttss2si, and

>         vcvttsd2si.

>


For vector instructions, we output suffix only when there is an
ambiguity.  Are there ambiguities in these instructions?

-- 
H.J.
Jan Beulich Aug. 7, 2019, 7:30 a.m. | #2
On 06.08.2019 21:41,  H.J. Lu  wrote:
> On Tue, Aug 6, 2019 at 7:25 AM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> Not doing so is simple inconsistent - the mode is specifically intended

>> to emit suffixes wherever applicable.

>>

>> gas/

>> 2019-08-XX  Jan Beulich  <jbeulich@suse.com>

>>

>>          * testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,

>>          testsuite/gas/i386/simd-suffix.d,

>>          testsuite/gas/i386/x86-64-simd-suffix.d: Adjust expectations.

>>

>> opcodes/

>> 2019-08-XX  Jan Beulich  <jbeulich@suse.com>

>>

>>          * i386-dis-evex-prefix.h (vcvtss2si, vcvtsd2si, vcvttss2si,

>>          vcvttsd2si, vcvtss2usi, vcvtsd2usi, vcvttss2usi, and

>>          vcvttsd2usi): Add S suffix.

>>          i386-dis.c (prefix_table): Add S suffix to cvtss2si, cvtsd2si,

>>          cvttss2si, cvttsd2si, vcvtss2si, vcvtsd2si, vcvttss2si, and

>>          vcvttsd2si.

>>

> 

> For vector instructions, we output suffix only when there is an

> ambiguity.  Are there ambiguities in these instructions?


I think we'd been there before, and as you can see this is now the
second time that this inconsistency has made me invest time in
fixing it. There are no ambiguities here, just like there aren't
on various non-SIMD insns that get a suffix in suffix-always mode.

May I ask where exactly it is clearly and prominently stated that
such (pseudo-)SIMD instructions should not _ever_ get suffixes
emitted for them? This is especially with the assembler accepting
suffixes for at least some of them (in which case, in suffix-
always mode, I'd consider it a legitimate expectation that the
input suffixes should then also be reflected as output ones). And
I think it goes without saying that this "some of them" (assuming
I recall correctly that this is the case) is yet another anomaly
that ought to be fixed (and iirc I had submitted a patch to this
effect before).

Jan
H.J. Lu Aug. 15, 2019, 10:21 p.m. | #3
On Wed, Aug 7, 2019 at 12:30 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 06.08.2019 21:41,  H.J. Lu  wrote:

> > On Tue, Aug 6, 2019 at 7:25 AM Jan Beulich <jbeulich@suse.com> wrote:

> >>

> >> Not doing so is simple inconsistent - the mode is specifically intended

> >> to emit suffixes wherever applicable.

> >>

> >> gas/

> >> 2019-08-XX  Jan Beulich  <jbeulich@suse.com>

> >>

> >>          * testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,

> >>          testsuite/gas/i386/simd-suffix.d,

> >>          testsuite/gas/i386/x86-64-simd-suffix.d: Adjust expectations.

> >>

> >> opcodes/

> >> 2019-08-XX  Jan Beulich  <jbeulich@suse.com>

> >>

> >>          * i386-dis-evex-prefix.h (vcvtss2si, vcvtsd2si, vcvttss2si,

> >>          vcvttsd2si, vcvtss2usi, vcvtsd2usi, vcvttss2usi, and

> >>          vcvttsd2usi): Add S suffix.

> >>          i386-dis.c (prefix_table): Add S suffix to cvtss2si, cvtsd2si,

> >>          cvttss2si, cvttsd2si, vcvtss2si, vcvtsd2si, vcvttss2si, and

> >>          vcvttsd2si.

> >>

> >

> > For vector instructions, we output suffix only when there is an

> > ambiguity.  Are there ambiguities in these instructions?

>

> I think we'd been there before, and as you can see this is now the

> second time that this inconsistency has made me invest time in

> fixing it. There are no ambiguities here, just like there aren't

> on various non-SIMD insns that get a suffix in suffix-always mode.

>

> May I ask where exactly it is clearly and prominently stated that

> such (pseudo-)SIMD instructions should not _ever_ get suffixes

> emitted for them? This is especially with the assembler accepting

> suffixes for at least some of them (in which case, in suffix-

> always mode, I'd consider it a legitimate expectation that the

> input suffixes should then also be reflected as output ones). And

> I think it goes without saying that this "some of them" (assuming

> I recall correctly that this is the case) is yet another anomaly

> that ought to be fixed (and iirc I had submitted a patch to this

> effect before).

>


For newer instructions, we should have an exact match when
searching SDM.  In some cases, if it is impossible, we require
suffixes to distinguish them.   Adding superfluous suffix doesn't
help much.

-- 
H.J.

Patch

--- a/gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d
@@ -60,16 +60,16 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%rax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2si \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2si \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2siq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2siq \(%rax\),%rax
  [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%rax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2si \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2si \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2siq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2siq \(%rax\),%rax
  [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f2 0f 5f 00          	maxsd  \(%rax\),%xmm0
@@ -179,16 +179,16 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%rax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2si \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2si \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2siq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2siq \(%rax\),%rax
  [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%rax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2si \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2si \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2siq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2siq \(%rax\),%rax
  [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f2 0f 5f 00          	maxsd  \(%rax\),%xmm0
--- a/gas/testsuite/gas/i386/simd-suffix.d
+++ b/gas/testsuite/gas/i386/simd-suffix.d
@@ -44,12 +44,12 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%eax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%eax\),%eax
  [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%eax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%eax\),%eax
  [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	f2 0f 5f 00          	maxsd  \(%eax\),%xmm0
@@ -137,12 +137,12 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%eax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%eax\),%eax
  [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%eax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%eax\),%eax
  [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%eax\),%xmm0
  [ 	]*[a-f0-9]+:	f2 0f 5f 00          	maxsd  \(%eax\),%xmm0
--- a/gas/testsuite/gas/i386/x86-64-simd-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-suffix.d
@@ -60,16 +60,16 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%rax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2si \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2si \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2siq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2siq \(%rax\),%rax
  [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%rax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2si \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2si \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2siq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2siq \(%rax\),%rax
  [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f2 0f 5f 00          	maxsd  \(%rax\),%xmm0
@@ -179,16 +179,16 @@  Disassembly of section .text:
  [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%rax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2si \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2si \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2siq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2siq \(%rax\),%rax
  [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%rax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2si \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%rax\),%eax
-[ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2si \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2siq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2siq \(%rax\),%rax
  [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%rax\),%xmm0
  [ 	]*[a-f0-9]+:	f2 0f 5f 00          	maxsd  \(%rax\),%xmm0
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -77,16 +77,16 @@ 
    /* PREFIX_EVEX_0F2C */
    {
      { Bad_Opcode },
-    { "vcvttss2si",	{ Gdq, EXxmm_md, EXxEVexS }, 0 },
+    { "vcvttss2siS",	{ Gdq, EXxmm_md, EXxEVexS }, 0 },
      { Bad_Opcode },
-    { "vcvttsd2si",	{ Gdq, EXxmm_mq, EXxEVexS }, 0 },
+    { "vcvttsd2siS",	{ Gdq, EXxmm_mq, EXxEVexS }, 0 },
    },
    /* PREFIX_EVEX_0F2D */
    {
      { Bad_Opcode },
-    { "vcvtss2si",	{ Gdq, EXxmm_md, EXxEVexR }, 0 },
+    { "vcvtss2siS",	{ Gdq, EXxmm_md, EXxEVexR }, 0 },
      { Bad_Opcode },
-    { "vcvtsd2si",	{ Gdq, EXxmm_mq, EXxEVexR }, 0 },
+    { "vcvtsd2siS",	{ Gdq, EXxmm_mq, EXxEVexR }, 0 },
    },
    /* PREFIX_EVEX_0F2E */
    {
@@ -383,16 +383,16 @@ 
    /* PREFIX_EVEX_0F78 */
    {
      { VEX_W_TABLE (EVEX_W_0F78_P_0) },
-    { "vcvttss2usi",	{ Gdq, EXxmm_md, EXxEVexS }, 0 },
+    { "vcvttss2usiS",	{ Gdq, EXxmm_md, EXxEVexS }, 0 },
      { VEX_W_TABLE (EVEX_W_0F78_P_2) },
-    { "vcvttsd2usi",	{ Gdq, EXxmm_mq, EXxEVexS }, 0 },
+    { "vcvttsd2usiS",	{ Gdq, EXxmm_mq, EXxEVexS }, 0 },
    },
    /* PREFIX_EVEX_0F79 */
    {
      { VEX_W_TABLE (EVEX_W_0F79_P_0) },
-    { "vcvtss2usi",	{ Gdq, EXxmm_md, EXxEVexR }, 0 },
+    { "vcvtss2usiS",	{ Gdq, EXxmm_md, EXxEVexR }, 0 },
      { VEX_W_TABLE (EVEX_W_0F79_P_2) },
-    { "vcvtsd2usi",	{ Gdq, EXxmm_mq, EXxEVexR }, 0 },
+    { "vcvtsd2usiS",	{ Gdq, EXxmm_mq, EXxEVexR }, 0 },
    },
    /* PREFIX_EVEX_0F7A */
    {
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3731,17 +3731,17 @@  static const struct dis386 prefix_table[
    /* PREFIX_0F2C */
    {
      { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
-    { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
+    { "cvttss2siS", { Gdq, EXd }, PREFIX_OPCODE },
      { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
-    { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
+    { "cvttsd2siS", { Gdq, EXq }, PREFIX_OPCODE },
    },
  
    /* PREFIX_0F2D */
    {
      { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
-    { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
+    { "cvtss2siS", { Gdq, EXd }, PREFIX_OPCODE },
      { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
-    { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
+    { "cvtsd2siS", { Gdq, EXq }, PREFIX_OPCODE },
    },
  
    /* PREFIX_0F2E */
@@ -4696,17 +4696,17 @@  static const struct dis386 prefix_table[
    /* PREFIX_VEX_0F2C */
    {
      { Bad_Opcode },
-    { "vcvttss2si",	{ Gdq, EXdScalar }, 0 },
+    { "vcvttss2siS",	{ Gdq, EXdScalar }, 0 },
      { Bad_Opcode },
-    { "vcvttsd2si",	{ Gdq, EXqScalar }, 0 },
+    { "vcvttsd2siS",	{ Gdq, EXqScalar }, 0 },
    },
  
    /* PREFIX_VEX_0F2D */
    {
      { Bad_Opcode },
-    { "vcvtss2si",	{ Gdq, EXdScalar }, 0 },
+    { "vcvtss2siS",	{ Gdq, EXdScalar }, 0 },
      { Bad_Opcode },
-    { "vcvtsd2si",	{ Gdq, EXqScalar }, 0 },
+    { "vcvtsd2siS",	{ Gdq, EXqScalar }, 0 },
    },
  
    /* PREFIX_VEX_0F2E */