[v2,5/5] RISC-V: Add r4 format for r type with 4 register operands

Message ID 20190702095801.32062-5-kito.cheng@sifive.com
State New
Headers show
Series
  • [v2,1/5] RISC-V: Fix doc for .insn
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Commit Message

Kito Cheng July 2, 2019, 9:58 a.m.
gas/ChangeLog:

	* doc/c-riscv.texi (Instruction Formats): Add r4 type.
	* testsuite/gas/riscv/insn.d: Add testcase for r4 type.
	* testsuite/gas/riscv/insn.s: Ditto.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_insn_types): Add r4 type.
---
 gas/doc/c-riscv.texi           |  1 +
 gas/testsuite/gas/riscv/insn.d |  5 +++++
 gas/testsuite/gas/riscv/insn.s |  7 ++++++-
 opcodes/riscv-opc.c            | 17 +++++++++++++++++
 4 files changed, 29 insertions(+), 1 deletion(-)

-- 
2.17.1

Comments

Jim Wilson July 5, 2019, 4:32 a.m. | #1
On Tue, Jul 2, 2019 at 5:58 PM Kito Cheng <kito.cheng@sifive.com> wrote:
> gas/ChangeLog:

>         * doc/c-riscv.texi (Instruction Formats): Add r4 type.

>         * testsuite/gas/riscv/insn.d: Add testcase for r4 type.

>         * testsuite/gas/riscv/insn.s: Ditto.

> opcodes/ChangeLog:

>         * riscv-opc.c (riscv_insn_types): Add r4 type.


This is OK.

Jim

Patch

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index a280ea216d..9bc8c82ab1 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -318,6 +318,7 @@  with the @samp{.insn} pseudo directive:
 @end verbatim
 
 @item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
+@itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3
 @verbatim
 +-----+-------+-----+-----+-------+----+-------------+
 | rs3 | func2 | rs2 | rs1 | func3 | rd |      opcode |
diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
index 0a2afa8dd8..47b3a8e11c 100644
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -51,6 +51,11 @@  Disassembly of section .text:
 [^:]+:[ 	]+bf71[ 	]+j[ 	]+0 \<target\>
 [^:]+: R_RISCV_RVC_JUMP[	]+target
 [^:]+:[ 	]+68c58543[ 	]+fmadd.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd.s[ 	]+fa0,fa1,fa2,fa3,rne
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
index ce78bdf71c..6c08f49d43 100644
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -34,7 +34,12 @@  target:
 	.insn cb C1, 0x6, a1, target
 	.insn cj C1, 0x5, target
 
-	.insn r MADD, 0, 0, a0, a1, a2, a3
+	.insn r  MADD, 0, 0, a0, a1, a2, a3
+	.insn r4 MADD, 0, 0, a0, a1, a2, a3
+	.insn r4 MADD, 0, 0, fa0, a1, a2, a3
+	.insn r4 MADD, 0, 0, fa0, fa1, a2, a3
+	.insn r4 MADD, 0, 0, fa0, fa1, fa2, a3
+	.insn r4 MADD, 0, 0, fa0, fa1, fa2, fa3
 	.insn r  0x33,  0,  0, fa0, a1, a2
 	.insn r  0x33,  0,  0, a0, fa1, a2
 	.insn r  0x33,  0,  0, fa0, fa1, a2
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index aa57cc950a..113d1a58c1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -812,6 +812,23 @@  const struct riscv_opcode riscv_insn_types[] =
 {"r",       0, {"I", 0},  "O4,F3,F2,d,S,T,R",   0,    0,  match_opcode, 0 },
 {"r",       0, {"I", 0},  "O4,F3,F2,D,S,T,R",   0,    0,  match_opcode, 0 },
 
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,s,t,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,s,t,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,S,t,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,S,t,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,s,T,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,s,T,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,S,T,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,S,T,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,s,t,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,s,t,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,S,t,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,S,t,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,s,T,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,s,T,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,S,T,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,S,T,R",   0,    0,  match_opcode, 0 },
+
 {"i",       0, {"I", 0},  "O4,F3,d,s,j",        0,    0,  match_opcode, 0 },
 {"i",       0, {"I", 0},  "O4,F3,D,s,j",        0,    0,  match_opcode, 0 },
 {"i",       0, {"I", 0},  "O4,F3,d,S,j",        0,    0,  match_opcode, 0 },