[2/2,powerpc] Use faster means to access FPSCR when possible in some cases

Message ID 1560361254-14067-3-git-send-email-pc@us.ibm.com
State New
Headers show
Series
  • utilize faster method to get FPSCR
Related show

Commit Message

Paul Clarke June 12, 2019, 5:40 p.m.
From: "Paul A. Clarke" <pc@us.ibm.com>


Using 'mffs' instruction to read the Floating Point Status Control Register
(FPSCR) can force a processor flush in some cases, with undesirable
performance impact.  If the values of the bits in the FPSCR which force the
flush are not needed, an instruction that is new to POWER9 (ISA version 3.0),
'mffsl' can be used instead.

Cases included:  get_rounding_mode, fegetround, fegetmode, fegetexcept.

2019-06-12  Paul A. Clarke  <pc@us.ibm.com>

	* sysdeps/powerpc/fpu_control.h (IS_ISA300): New.
	(_FPU_MFFS): Move implementation...
	(_FPU_GETCW): Here.
	(_FPU_MFFSL): Move implementation....
	(_FPU_GET_RC_FAST): Here. New.
	(_FPU_GET_RC): Change to use _FPU_GET_RC_FAST or _FPU_GETCW.
	* sysdeps/powerpc/bits/fenvinline.h (__fegetround_ISA300): New.
	(__fegetround): Use 'mffsl' when possible.
	* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status): New.
	* sysdeps/powerpc/fpu/fegetmode.c (fegetmode): Use fegetenv_status()
	instead of fegetenv_register().
	* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Likewise.

v2: This incorporates the suggestion from Adhemerval in the patch
    "[powerpc] fegetmode: utilize faster method to get rounding mode"
    that was not committed.
---
 sysdeps/powerpc/bits/fenvinline.h | 29 +++++++++++++++++++++++------
 sysdeps/powerpc/fpu/fegetexcept.c |  2 +-
 sysdeps/powerpc/fpu/fegetmode.c   |  2 +-
 sysdeps/powerpc/fpu/fenv_libc.h   | 17 +++++++++++++++++
 sysdeps/powerpc/fpu_control.h     | 39 ++++++++++++++++++++-------------------
 5 files changed, 62 insertions(+), 27 deletions(-)

-- 
1.8.3.1

Patch

diff --git a/sysdeps/powerpc/bits/fenvinline.h b/sysdeps/powerpc/bits/fenvinline.h
index 7079d1a..dc06565 100644
--- a/sysdeps/powerpc/bits/fenvinline.h
+++ b/sysdeps/powerpc/bits/fenvinline.h
@@ -19,12 +19,29 @@ 
 #if defined __GNUC__ && !defined _SOFT_FLOAT && !defined __NO_FPRS__
 
 /* Inline definition for fegetround.  */
-# define __fegetround() \
-  (__extension__  ({ int __fegetround_result;				      \
-		     __asm__ __volatile__				      \
-		       ("mcrfs 7,7 ; mfcr %0"				      \
-			: "=r"(__fegetround_result) : : "cr7");		      \
-		     __fegetround_result & 3; }))
+# define __fegetround_ISA300()						\
+  __extension__  ({							\
+    union { double __d; unsigned long long __ll; } __u;			\
+    __asm__ __volatile__ ("mffsl %0" : "=f" (__u.__d));			\
+    __u.__ll & 0x0000000000000003LL;					\
+  })
+
+#ifdef _ARCH_PWR9
+# define __fegetround() __fegetround_ISA300 ()
+#else
+# define __fegetround()							\
+  (__extension__ ({							\
+    if (__glibc_likely(GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))	\
+      __fegetround_ISA300 {};						\
+    else								\
+      {									\
+        int __fegetround_result;					\
+        __asm__ __volatile__ ("mcrfs 7,7 ; mfcr %0"			\
+                              : "=r"(__fegetround_result) : : "cr7");	\
+        __fegetround_result & 3;					\
+      }									\
+  }))
+#endif
 # define fegetround() __fegetround ()
 
 # ifndef __NO_MATH_INLINES
diff --git a/sysdeps/powerpc/fpu/fegetexcept.c b/sysdeps/powerpc/fpu/fegetexcept.c
index 2173d77..10a37f0 100644
--- a/sysdeps/powerpc/fpu/fegetexcept.c
+++ b/sysdeps/powerpc/fpu/fegetexcept.c
@@ -24,7 +24,7 @@  __fegetexcept (void)
 {
   fenv_union_t fe;
 
-  fe.fenv = fegetenv_register ();
+  fe.fenv = fegetenv_status ();
 
   return fenv_reg_to_exceptions (fe.l);
 }
diff --git a/sysdeps/powerpc/fpu/fegetmode.c b/sysdeps/powerpc/fpu/fegetmode.c
index f43ab60..466f5b7 100644
--- a/sysdeps/powerpc/fpu/fegetmode.c
+++ b/sysdeps/powerpc/fpu/fegetmode.c
@@ -21,6 +21,6 @@ 
 int
 fegetmode (femode_t *modep)
 {
-  *modep = fegetenv_register ();
+  *modep = fegetenv_status ();
   return 0;
 }
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
index f66bf24..e257da7 100644
--- a/sysdeps/powerpc/fpu/fenv_libc.h
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -33,6 +33,23 @@  extern const fenv_t *__fe_mask_env (void) attribute_hidden;
 /* Equivalent to fegetenv, but returns a fenv_t instead of taking a
    pointer.  */
 #define fegetenv_register() __builtin_mffs()
+ 
+#ifdef _ARCH_PWR9
+#define IS_ISA300() 1
+#else
+#define IS_ISA300() (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)
+#endif
+
+/* Equivalent to fegetenv_register, but only returns bits for
+   status, exception enables, and mode.  */
+#define fegetenv_status()				\
+  ({register double __fr;				\
+    if (__glibc_likely(IS_ISA300())) 			\
+      __asm__ __volatile__ ("mffsl %0" : "=f" (__fr));	\
+    else						\
+      __fr = __builtin_mffs();				\
+    __fr;						\
+  })
 
 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
 #define fesetenv_register(env) \
diff --git a/sysdeps/powerpc/fpu_control.h b/sysdeps/powerpc/fpu_control.h
index 0ab9331..8910dba 100644
--- a/sysdeps/powerpc/fpu_control.h
+++ b/sysdeps/powerpc/fpu_control.h
@@ -23,6 +23,12 @@ 
 # error "SPE/e500 is no longer supported"
 #endif
 
+#ifdef _ARCH_PWR9
+#define IS_ISA300() 1
+#else
+#define IS_ISA300() (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)
+#endif
+
 #ifdef _SOFT_FLOAT
 
 # define _FPU_RESERVED 0xffffffff
@@ -65,36 +71,31 @@  extern fpu_control_t __fpu_control;
 typedef unsigned int fpu_control_t;
 
 /* Macros for accessing the hardware control word.  */
-# define __FPU_MFFS()						\
-  ({register double __fr;					\
-    __asm__ __volatile__("mffs %0" : "=f" (__fr));				\
-    __fr;							\
-  })
-
 # define _FPU_GETCW(cw)						\
   ({union { double __d; unsigned long long __ll; } __u;		\
-    __u.__d = __FPU_MFFS();					\
+    register double __fr;					\
+    __asm__ __volatile__("mffs %0" : "=f" (__fr));		\
+    __u.__d = __fr;						\
     (cw) = (fpu_control_t) __u.__ll;				\
     (fpu_control_t) __u.__ll;					\
   })
 
-#ifdef _ARCH_PWR9
-# define __FPU_MFFSL()						\
-  ({register double __fr;					\
-    __asm__ __volatile__("mffsl %0" : "=f" (__fr));				\
-    __fr;							\
-  })
-#else
-# define __FPU_MFFSL() __FPU_MFFS()
-#endif
-    
-# define _FPU_GET_RC()						\
+# define _FPU_GET_RC_FAST()					\
   ({union { double __d; unsigned long long __ll; } __u;		\
-    __u.__d = __FPU_MFFSL();					\
+    register double __fr;					\
+    __asm__ __volatile__("mffsl %0" : "=f" (__fr));		\
+    __u.__d = __fr;						\
     __u.__ll &= _FPU_MASK_RC;					\
     (fpu_control_t) __u.__ll;					\
   })
 
+# define _FPU_GET_RC()						\
+  ({fpu_control_t rc = IS_ISA300()				\
+    ? _FPU_GET_RC_FAST()					\
+    : _FPU_GETCW(rc);						\
+    rc;								\
+  })
+
 # define _FPU_SETCW(cw)						\
   { union { double __d; unsigned long long __ll; } __u;		\
     register double __fr;					\