[3/3] RISC-V: Add r4 format for r type with 4 register operands

Message ID 1558939175-51429-3-git-send-email-kito@andestech.com
State New
Headers show
Series
  • [1/3] RISC-V: Fix doc for .insn
Related show

Commit Message

Kito Cheng May 27, 2019, 6:39 a.m.
From: Kito Cheng <kito.cheng@gmail.com>


gas/ChangeLog:

	* doc/c-riscv.texi (Instruction Formats): Add r4 type.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_insn_types): Add r4 type.
---
 gas/doc/c-riscv.texi |  1 +
 opcodes/riscv-opc.c  | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

-- 
1.8.3.1

Comments

Jim Wilson May 29, 2019, 6:49 a.m. | #1
On Sun, May 26, 2019 at 11:37 PM Kito Cheng <kito@andestech.com> wrote:
> gas/ChangeLog:

>         * doc/c-riscv.texi (Instruction Formats): Add r4 type.

> opcodes/ChangeLog:

>         * riscv-opc.c (riscv_insn_types): Add r4 type.


There should be testcases added for the new r4 type.  Otherwise this looks OK.

Jim

Patch

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index a280ea2..9bc8c82 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -318,6 +318,7 @@  with the @samp{.insn} pseudo directive:
 @end verbatim
 
 @item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
+@itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3
 @verbatim
 +-----+-------+-----+-----+-------+----+-------------+
 | rs3 | func2 | rs2 | rs1 | func3 | rd |      opcode |
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 03f0cd1..d4ccc7c 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -812,6 +812,23 @@  const struct riscv_opcode riscv_insn_types[] =
 {"r",       0, {"I", 0},  "O4,F3,F2,d,S,T,R",   0,    0,  match_opcode, 0 },
 {"r",       0, {"I", 0},  "O4,F3,F2,D,S,T,R",   0,    0,  match_opcode, 0 },
 
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,s,t,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,s,t,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,S,t,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,S,t,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,s,T,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,s,T,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,S,T,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,S,T,r",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,s,t,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,s,t,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,S,t,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,S,t,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,s,T,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,s,T,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,d,S,T,R",   0,    0,  match_opcode, 0 },
+{"r4",      0, {"I", 0},  "O4,F3,F2,D,S,T,R",   0,    0,  match_opcode, 0 },
+
 {"i",       0, {"I", 0},  "O4,F3,d,s,j",        0,    0,  match_opcode, 0 },
 {"i",       0, {"I", 0},  "O4,F3,D,s,j",        0,    0,  match_opcode, 0 },
 {"i",       0, {"I", 0},  "O4,F3,d,S,j",        0,    0,  match_opcode, 0 },