[2/3] RISC-V: sb/uj format named b/j in latest spec

Message ID 1558939175-51429-2-git-send-email-kito@andestech.com
State New
Headers show
Series
  • [1/3] RISC-V: Fix doc for .insn
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Commit Message

Kito Cheng May 27, 2019, 6:39 a.m.
From: Kito Cheng <kito.cheng@gmail.com>


 - We also keep sb and uj for backward compatibility.

gas/ChangeLog:

	* doc/c-riscv.texi (Instruction Formats): Add b and j type.

opcode/ChangeLog:

	* riscv-opc.c (riscv_insn_types): Add b and j type.
---
 gas/doc/c-riscv.texi |  3 +++
 opcodes/riscv-opc.c  | 11 +++++++++++
 2 files changed, 14 insertions(+)

-- 
1.8.3.1

Comments

Jim Wilson May 29, 2019, 6:47 a.m. | #1
On Sun, May 26, 2019 at 11:37 PM Kito Cheng <kito@andestech.com> wrote:
> gas/ChangeLog:

>         * doc/c-riscv.texi (Instruction Formats): Add b and j type.

> opcode/ChangeLog:

>         * riscv-opc.c (riscv_insn_types): Add b and j type.


There should be tests added to the testcase for the new b and j types,
which can just be copies of the existing sb and uj tests.

The new b type should not support stores, e.g. the last two with q(s),
as that is a bug in the original implementation.  Similarly, there
should not be testcases added for stores using the b type.

Jim

Patch

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 5c30db1..a280ea2 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -343,6 +343,8 @@  with the @samp{.insn} pseudo directive:
 
 @item SB type: .insn sb opcode, func3, rd, rs1, symbol
 @itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
+@itemx B type: .insn s opcode, func3, rd, rs1, symbol
+@itemx B type: .insn s opcode, func3, rd, simm12(rs1)
 @verbatim
 +------------+--------------+-----+-----+-------+-------------+-------------+--------+
 | simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
@@ -359,6 +361,7 @@  with the @samp{.insn} pseudo directive:
 @end verbatim
 
 @item UJ type: .insn uj opcode, rd, symbol
+@itemx J type: .insn j opcode, rd, symbol
 @verbatim
 +------------+--------------+------------+---------------+----+-------------+
 | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd |      opcode |
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bd65259..03f0cd1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -831,12 +831,23 @@  const struct riscv_opcode riscv_insn_types[] =
 {"sb",      0, {"I", 0},  "O4,F3,t,q(s)",       0,    0,  match_opcode, 0 },
 {"sb",      0, {"I", 0},  "O4,F3,T,q(s)",       0,    0,  match_opcode, 0 },
 
+{"b",      0, {"I", 0},  "O4,F3,s,t,p",        0,    0,  match_opcode, 0 },
+{"b",      0, {"I", 0},  "O4,F3,S,t,p",        0,    0,  match_opcode, 0 },
+{"b",      0, {"I", 0},  "O4,F3,s,T,p",        0,    0,  match_opcode, 0 },
+{"b",      0, {"I", 0},  "O4,F3,S,T,p",        0,    0,  match_opcode, 0 },
+
+{"b",      0, {"I", 0},  "O4,F3,t,q(s)",       0,    0,  match_opcode, 0 },
+{"b",      0, {"I", 0},  "O4,F3,T,q(s)",       0,    0,  match_opcode, 0 },
+
 {"u",       0, {"I", 0},  "O4,d,u",             0,    0,  match_opcode, 0 },
 {"u",       0, {"I", 0},  "O4,D,u",             0,    0,  match_opcode, 0 },
 
 {"uj",      0, {"I", 0},  "O4,d,a",             0,    0,  match_opcode, 0 },
 {"uj",      0, {"I", 0},  "O4,D,a",             0,    0,  match_opcode, 0 },
 
+{"j",      0, {"I", 0},  "O4,d,a",             0,    0,  match_opcode, 0 },
+{"j",      0, {"I", 0},  "O4,D,a",             0,    0,  match_opcode, 0 },
+
 {"cr",      0, {"C", 0},  "O2,CF4,d,CV",        0,    0,  match_opcode, 0 },
 {"cr",      0, {"C", 0},  "O2,CF4,D,CV",        0,    0,  match_opcode, 0 },
 {"cr",      0, {"C", 0},  "O2,CF4,d,CT",        0,    0,  match_opcode, 0 },