[53/57,Arm,OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls, vclz and vctp

Message ID 3f343cd3-c03e-cdc8-9209-96212de15ed6@arm.com
State New
Headers show
Series
  • : Add support for Armv8.1-M Mainline MVE instructions
Related show

Commit Message

Andre Vieira (lists) May 1, 2019, 5:49 p.m.
Hello,

This patch adds support for MVE instructions: VAND, VBRSR, VCLS, VCLZ, 
and VCTP.

opcodes/ChangeLog:

2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>
             Michael Collison <michael.collison@arm.com>

	* arm-dis.c (thumb32_opcodes): Add new instructions.
	(enum mve_instructions): Likewise.
	(is_mve_encoding_conflict): Handle new instructions.
	(is_mve_undefined): Likewise.
	(is_mve_unpredictable): Likewise.
	(print_mve_size): Likewise.

Patch

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 4222bdda0400826de86f32167b91c6fe8dd17427..8f2e541b1c1ad4f7d1ef1c3c8f4edddba551d00e 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -223,6 +223,11 @@  enum mve_instructions
   MVE_VSUB_FP_T2,
   MVE_VSUB_VEC_T1,
   MVE_VSUB_VEC_T2,
+  MVE_VAND,
+  MVE_VBRSR,
+  MVE_VCLS,
+  MVE_VCLZ,
+  MVE_VCTP,
   MVE_NONE
 };
 
@@ -2147,6 +2152,18 @@  static const struct mopcode32 mve_opcodes[] =
    0xee300f00, 0xffb10f51,
    "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
 
+  /* Vector VAND.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VAND,
+   0xef000150, 0xffb11f51,
+   "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+  /* Vector VBRSR register.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VBRSR,
+   0xfe011e60, 0xff811f70,
+   "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
   /* Vector VCADD floating point.  */
   {ARM_FEATURE_COPROC (FPU_MVE_FP),
    MVE_VCADD_FP,
@@ -2159,6 +2176,18 @@  static const struct mopcode32 mve_opcodes[] =
    0xfe000f00, 0xff810f51,
    "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
 
+  /* Vector VCLS.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VCLS,
+   0xffb00440, 0xffb31fd1,
+   "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
+
+  /* Vector VCLZ.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VCLZ,
+   0xffb004c0, 0xffb31fd1,
+   "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
+
   /* Vector VCMLA.  */
   {ARM_FEATURE_COPROC (FPU_MVE_FP),
    MVE_VCMLA_FP,
@@ -2274,6 +2303,12 @@  static const struct mopcode32 mve_opcodes[] =
    0xee300e00, 0xefb10f50,
    "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
 
+   /* Vector VCTP.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VCTP,
+   0xf000e801, 0xffc0ffff,
+   "vctp%v.%20-21s\t%16-19r"},
+
   /* Vector VDUP.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_VDUP,
@@ -5029,6 +5064,7 @@  is_mve_encoding_conflict (unsigned long given,
       else
 	return FALSE;
 
+    case MVE_VBRSR:
     case MVE_VADD_VEC_T2:
     case MVE_VSUB_VEC_T2:
     case MVE_VABAV:
@@ -5206,6 +5242,12 @@  is_mve_encoding_conflict (unsigned long given,
       else
 	return FALSE;
 
+    case MVE_VCTP:
+    if (arm_decode_field (given, 16, 19) == 0xf)
+      return TRUE;
+    else
+      return FALSE;
+
     default:
     case MVE_VADD_FP_T1:
     case MVE_VADD_FP_T2:
@@ -5650,6 +5692,16 @@  is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	else
 	  return FALSE;
 
+    case MVE_VCLS:
+    case MVE_VCLZ:
+      if (arm_decode_field (given, 18, 19) == 3)
+	{
+	  *undefined_code = UNDEF_SIZE_3;
+	  return TRUE;
+	}
+      else
+	return FALSE;
+
     default:
       return FALSE;
     }
@@ -5709,6 +5761,7 @@  is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	return FALSE;
       }
 
+    case MVE_VBRSR:
     case MVE_VADD_FP_T2:
     case MVE_VSUB_FP_T2:
     case MVE_VADD_VEC_T2:
@@ -6097,6 +6150,15 @@  is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 
       }
 
+    case MVE_VCTP:
+      if (arm_decode_field (given, 16, 19) == 0xd)
+	{
+	  *unpredictable_code = UNPRED_R13;
+	  return TRUE;
+	}
+      else
+	return FALSE;
+
     default:
       return FALSE;
     }
@@ -6780,13 +6842,17 @@  print_mve_size (struct disassemble_info *info,
     case MVE_VADD_VEC_T1:
     case MVE_VADD_VEC_T2:
     case MVE_VADDV:
+    case MVE_VBRSR:
     case MVE_VCADD_VEC:
+    case MVE_VCLS:
+    case MVE_VCLZ:
     case MVE_VCMP_VEC_T1:
     case MVE_VCMP_VEC_T2:
     case MVE_VCMP_VEC_T3:
     case MVE_VCMP_VEC_T4:
     case MVE_VCMP_VEC_T5:
     case MVE_VCMP_VEC_T6:
+    case MVE_VCTP:
     case MVE_VDDUP:
     case MVE_VDWDUP:
     case MVE_VHADD_T1: