[51/57,Arm,OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp

Message ID 7c85111c-1e25-a51c-052b-8f7e1bfdd26a@arm.com
State New
Headers show
  • : Add support for Armv8.1-M Mainline MVE instructions
Related show

Commit Message

Andre Vieira (lists) May 1, 2019, 5:48 p.m.

This patch adds support for MVE low-overhead loop tail predicated 
instructions: LCTP, LETP, WLSTP, and DLSTP.


2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>
             Michael Collison <michael.collison@arm.com>

	* arm-dis.c (thumb32_opcodes): Add new instructions.
         (print_insn_thumb32): Handle new instructions.


diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 6564e41f8d479f5146c040830056cf21e1b0d1db..a2051a9b738237b80cc9044f883ed6a77b734807 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -3949,13 +3949,21 @@  static const struct opcode32 thumb32_opcodes[] =
   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
      instructions.  */
-    0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
-    0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+    0xf00fe001, 0xffffffff, "lctp%c"},
     0xf02fc001, 0xfffff001, "le\t%P"},
     0xf00fc001, 0xfffff001, "le\tlr, %P"},
+    0xf01fc001, 0xfffff001, "letp\tlr, %P"},
+    0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+    0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
+    0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+    0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
@@ -10171,6 +10179,13 @@  print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 		  switch (*c)
+		    case 's':
+		      if (val <= 3)
+			func (stream, "%s", mve_vec_sizename[val]);
+		      else
+			func (stream, "<undef size>");
+		      break;
 		    case 'd':
 		      func (stream, "%lu", val);
 		      value_in_comment = val;